JPH09260208A - Manufacture of laminated capacitor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of a laminated capacitor which can improve lamination accuracy. SOLUTION: A laminated capacitor is formed by using a green sheet 5 wherein a plurality of conductor layers 6 are formed in a matrix at an equal interval, laminating a plurality of green sheets 5 shifting the conductor layers 6 in a width direction thereof each fixed number thereof so that the conductor layers 6 of upper and lower layers face each other slightly unevenly in a width direction thereof and thereafter forming a lamination body by cutting it in a layer direction in a fixed position and forming a plurality of outside electrodes which are conductive to a fixed inside electrode in an outer surface of a lamination body. Therefore, even if misregistration is generated in a lamination position of the green sheet 5 in a width direction of the conductor layer 6 over a prescribed value when a plurality of green sheets 5 are laminated, the magnitude of the misregistration is the same in all the conductor layers 6. Therefore, capacity distribution in a laminated capacitor thereby obtained is narrowed, an electrostatic capacity value is almost the same value and a yield can be improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a multilayer capacitor, and more particularly to a method for manufacturing a multilayer capacitor with improved stacking accuracy.

[0002]

2. Description of the Related Art As is well known in the art, a multilayer capacitor 1
As shown in FIG. 2, a plurality of internal electrodes 3 which are overlapped with each other with a dielectric ceramic layer interposed therebetween are arranged in a sintered body 2 made of a dielectric ceramic.
The A and B layers 3B are alternately connected to a pair of external electrodes 4 formed on the end faces of the sintered body.

In the high frequency region (several 100 MHz to several G)
Hz), a capacitor used in
As shown in the multilayer capacitor by using the trigonometry in each of (b), the stress distribution pattern in which the internal electrodes 3 are alternately staggered and stacked is used. By using this stress distribution pattern, it is possible to improve the Q value in the high frequency region and suppress the occurrence of delamination.

In manufacturing the multilayer capacitor 1 in which the internal electrodes are laminated by such a stress distribution pattern,
Rectangular green sheet 5 made of dielectric ceramics
A plurality of conductor layers 6 forming the internal electrodes are printed and formed in a matrix with a printing pattern as shown in FIG.
The conductor layer 6 is made of, for example, Ag, Pd, Ag-Pd, N.
i, Cu, etc., and this metal paste is printed on the green sheet.

As shown in FIGS. 5A and 5B, the printed pattern of the conductor layer forming these internal electrodes is the A layer 3
In the A and B layers 3B, the conductor layers of different patterns are printed on the green sheet by using the screens of the layer A and the screen of the layer B, respectively. It has been staggered. Here, the screen pattern is set such that the large column spacing Sb and the small column spacing Ss are alternately present between the adjacent conductor layers 6.

As shown in FIG. 6, the green sheets 5 on which the conductor layers 6 are printed are arranged so that the A layers 3A and the B layers 3B are alternately arranged according to the set capacitance, or two green sheets are arranged according to the purpose. Alternatively, the sheets are stacked at random to form a sheet laminate.

Thereafter, the entire sheet laminate is thermocompression bonded,
The sheet laminate is cut in a lattice along cutting lines 7 in two directions determined based on the width and length of a single component to obtain a laminated chip. Further, after firing the multilayer chip, the external electrodes 4 are formed on the end faces of the multilayer chip 1 to form the multilayer capacitor 1.
Are manufactured.

The conductor layer 6 has a length twice that of the internal electrode, and is divided into two pieces at the time of cutting to expose the cut edge on the end face of the laminated chip, which is connected to the external electrode 4. To be done.

On the other hand, in a high-capacity type capacitor such as the B characteristic, E characteristic, and F characteristic of the JIS standard, the printed area of the internal electrodes is designed to be large in order to maximize the capacitance. In addition, the temperature compensating capacitor such as CH characteristic and RH characteristic and the capacitor used in the high frequency range are
The printed thickness of the internal electrodes is set thick in order to improve the value.

[0010]

However, if the printing accuracy of the conductor layer 6 is lowered as described above, the crossing area (opposing area) of the conductor layer 6 in every other row as shown in FIG.
A large column and a small column are generated, resulting in a large capacity distribution and a decrease in yield.

In view of the above problems, it is an object of the present invention to provide a method of manufacturing a multilayer capacitor which can improve the stacking accuracy.

[0012]

In order to achieve the above-mentioned object, the present invention cuts into a predetermined shape a laminate in which a plurality of green sheets each having a plurality of conductor layers serving as internal electrodes formed in a matrix are laminated. In the method for producing a multilayer capacitor, the conductor layer is formed such that the upper and lower conductor layers face each other with a slight deviation in the width direction, using a green sheet in which a plurality of conductor layers are formed in a matrix at equal intervals. The green sheets are shifted by a predetermined number in the width direction to form a sheet laminate by laminating a plurality of layers, and then the sheet laminate is cut in a layer direction at a predetermined position to form a laminate. A method of manufacturing a multilayer capacitor is proposed in which a plurality of external electrodes that are electrically connected to predetermined internal electrodes are formed on the outer surface of the multilayer body.

According to the method for manufacturing the multilayer capacitor, since the green sheet in which a plurality of conductor layers are formed in a matrix at equal intervals is used, the conductor layers face each other with a slight offset in the width direction. When a plurality of the green sheets are laminated by shifting the conductor layer by a predetermined number in the width direction and the stacking position of the green sheets is deviated from the specified value in the width direction of the conductor layer, this deviation The size is the same in all conductor layers. Therefore, the capacitance distribution in the obtained multilayer capacitor is narrowed, the capacitance values thereof are almost the same, and the yield can be improved.

[0014]

DETAILED DESCRIPTION OF THE INVENTION An example of an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing an example of a green sheet on which a metal paste to be an internal electrode according to the present embodiment is printed. In the figure, the same components as those of the conventional example are denoted by the same reference numerals, and description thereof will be omitted. Further, the difference between the conventional example and this example is that the green sheet 5
This is because when the conductor layer 6 was formed thereon, the conductor layers 6 were formed in a matrix shape at equal intervals.

That is, the green sheet 5 is made of Mg ₂ TiO _2.
It is made of a ceramic material containing _4- ZnTiO ₃ as a main component and having a dielectric constant of 20 and a CH characteristic of a temperature characteristic, and its thickness is set to 28 μm after chip sintering.

The conductor layer 6 formed on the green sheet 5 is made of, for example, Ag, Pd, Ag-Pd, Ni, Cu or the like, and its printed film thickness is 3 μm to 10 μm (after drying).
Set to about.

Further, conductor layers 6 are formed on the green sheet 5 at regular intervals in a matrix.

The green sheets 5 on which the conductor layers 6 are formed in a matrix form are stacked with the same row spacing Sc, cut along the cutting lines 7, fired, and then attached with external electrodes. The size of the multilayer capacitor is 1.0 mm (length) x 0.5 mm (height) x 0.5 mm (width). Here, when the conductor layers 6 are preliminarily printed such that the upper and lower conductor layers 6 face each other with a slight deviation in the width direction, or when the conductor layers 6 have the same print pattern, they are stacked. In, the green sheets are shifted and stacked.

When the green sheets 5 on which the conductor layers 6 are formed with the same row spacing Sc as described above are stacked and thermocompression-bonded, when the opposing positions of the upper and lower conductor layers 6 deviate from a specified value, The magnitude of the shift has the same value in each conductor layer 6.

Therefore, the capacitance distribution in the multilayer capacitor 1 thus obtained is narrowed, the capacitance values thereof are almost the same, and the yield can be improved.

In order to compare the variation in capacitance between the conventional example and this example, the multilayer capacitor 1 was manufactured by using each printing pattern. The print patterns used for this comparison are the print pattern shown in FIG. 1 as an example and the print pattern shown in FIG. 3 as a conventional example.

100 multilayer capacitors manufactured by using these printing patterns were sampled, and the variation in capacitance was determined. FIG. 8 shows the measurement results.

As can be seen from the results of this experiment, by forming the conductor layers 6 in a matrix form on the green sheet 5 at equal intervals Sc, it is possible to narrow the capacitance distribution of the manufactured multilayer capacitor, It has been proved that the capacity yield of the multilayer capacitor 1 can be improved. This reduces the variation in capacitance,
Since it is possible to prevent the yield from decreasing, it is possible to manufacture the highly accurate multilayer capacitor 1.

The above-described embodiment is merely an example, and the present invention is not limited to this. Further, in the present embodiment, the shift in the width direction of the conductor layer 6 has been described, but it goes without saying that the same effect can be obtained also in the shift in the length direction of the conductor layer 6.

[0025]

As described above, according to the present invention, since the green sheet in which a plurality of conductor layers are formed in a matrix at equal intervals is used, the conductor layers face each other with a slight deviation in the width direction. When a plurality of green sheets are laminated by shifting the conductor layer by a predetermined number in the width direction so that the laminated position of the green sheets is deviated from the specified value in the width direction of the conductor layer, Since the magnitude of this shift is the same in all conductor layers, the capacitance distribution in the resulting multilayer capacitor is narrowed,
The electrostatic capacitance value becomes almost the same value, and the yield can be improved.

[Brief description of drawings]

FIG. 1 is a diagram showing a conductor layer printing pattern according to an embodiment of the present invention.

FIG. 2 is a partially cutaway sectional perspective view showing a multilayer capacitor.

FIG. 3 is a diagram illustrating a stress distribution pattern in a conventional example.

FIG. 4 is a diagram showing a conductor layer printing pattern of a conventional example.

FIG. 5 is a view showing a conductor layer printing pattern of a conventional example.

FIG. 6 is a diagram illustrating a stacked state of green sheets on which conductor layers are formed.

FIG. 7 is a diagram illustrating a state of stacking deviation in a conventional example.

FIG. 8 is a diagram showing a capacity distribution of an example of the present invention and a conventional example.

[Explanation of symbols]

1 ... Multilayer capacitor, 2 ... Sintered body, 3 ... Internal electrode, 3A
... A layer, 3B ... B layer, 4 ... External electrode, 5 ... Green sheet, 6 ... Conductor layer, 7 ... Cutting line.

Claims (1)

[Claims] 1. A method of manufacturing a multilayer capacitor, comprising cutting a laminate, which is obtained by laminating a plurality of green sheets each having a plurality of conductor layers serving as internal electrodes formed in a matrix, into a predetermined shape. A plurality of green sheets are formed in a matrix, and the conductor layers are shifted in the width direction by a predetermined number so that the upper and lower conductor layers face each other with a slight deviation in the width direction. After stacking layers to form a sheet laminate, the sheet laminate is cut in a layer direction at predetermined positions to form a laminate, and a plurality of external electrodes electrically connected to predetermined internal electrodes on the outer surface of the laminate. A method of manufacturing a multilayer capacitor, which comprises: