JPH09258988A - Interruption control system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide interruption control method/circuit by which multiple interruptions to CPU can be received and circuit/device constitution can be facilitated. SOLUTION: An interruption control circuit is provided with plural interruption control parts 1, 2...N and a high-order interruption control part 20 arbitrating interruption coming from plural interruption lines. The interruption control part 1 is provided with plural interruption request parts 1, 2...M having interruption generation circuits for an interruption request pulse signal 101, a clock generation part 10 generating a clock signal 600, an interruption request pulse detection part 11 detecting the interruption request pulse signal 101 and detecting a pulse position (M), an interruption request number register 12 where the interruption request number (M) being a number allocated to the interruption generation circuit is set, an interruption line control part 14 arbitrating interruption coming within one interruption line and an interruption response pulse generation part 13 generating an interruption response pulse signal 102 in a pulse position.

Description

Detailed Description of the Invention

[0001]

The present invention relates to an interrupt control method and an interrupt control circuit for a CPU, and more particularly to an interrupt control method and an interrupt control circuit for a CPU that receives and arbitrates a plurality of interrupts.

[0002]

2. Description of the Related Art In the prior art, when N interrupt generating circuits are accommodated, N interrupt signal lines of the interrupt generating circuits must be prepared.

[0003] Alternatively, as in the "interrupt request priority control system" disclosed in Japanese Patent Application Laid-Open No. 57-83839, an interrupt generation request section is serially cascaded in order to reduce the number of signal lines to one (hereinafter referred to as a daisy chain). ) To make the connection.

[0004]

A first problem in the prior art is that the number of interrupt generating units is limited to about several due to the restriction on the signal lines of the normal connector.

A second problem is that in the case of the daisy chain, all the interrupt generation units are in a state where signals can be relayed, and when the number is large, the delay becomes large and fixed priority is given. there were.

A third problem is that the number of signal lines cannot be increased because it is necessary to reduce changes to existing devices.

An object of the present invention is to provide an interrupt control method and an interrupt control circuit capable of accepting a large number of interrupts to a CPU and simplifying a circuit / device configuration.

[0008]

According to the present invention, there is provided an interrupt control circuit for a CPU, wherein the interrupt control circuit includes a plurality of interrupt control units each having one interrupt line, and a plurality of interrupt lines. And an upper-level interrupt controller that arbitrates incoming interrupts.The interrupt control circuit transmits a plurality of interrupt request units having an interrupt generation circuit to the interrupt request pulse signal line, and interrupt request pulse signals and interrupt response pulse signals. A clock generator for generating a clock signal for synchronization, an interrupt request pulse detector having an interrupt request pulse detector and a pulse position detector, and an interrupt request number assigned to the interrupt generator are set. Interrupt request number register
Means for arbitrating an interrupt coming from one interrupt line and notifying an interrupt request number from the CPU bus to a higher-level interrupt control unit using an interrupt request pulse signal, and generating an interrupt response pulse from the CPU bus using an interrupt response pulse signal And an interrupt response pulse generator for generating an interrupt response pulse signal in synchronization with a clock signal at a pulse position which is a time slot corresponding to an interrupt response number from the CPU. The interrupt request unit generates an interrupt request pulse signal by synchronizing the interrupt with a clock signal when an interrupt occurs simultaneously, and generates an interrupt request at a pulse position, which is a time slot corresponding to the interrupt request number. Multiple interrupts can be accepted by sending a pulse signal Means for detecting an interrupt request pulse signal, an interrupt request pulse detection circuit for detecting an interrupt request pulse signal, a pulse position detector for detecting a pulse position as a time slot portion, and an interrupt request number corresponding to the pulse position. In the interrupt request number register, and a means for notifying the interrupt request number from the CPU bus to the interrupt line control unit by an interrupt request pulse signal, and the higher-order interrupt control unit arbitrates interrupts coming from a plurality of interrupt lines. CPU by interrupt request pulse signal
Means for notifying the CPU of an interrupt request number from the bus, means for receiving an interrupt response number from the CPU from the CPU by an interrupt response pulse signal, and means for interrupting an interrupt response number from the CPU from the CPU bus by an interrupt response pulse signal Means for notifying the line control unit.

[0009] A mode switching unit may be provided for switching for each interrupt request pulse signal line to a method which enables interrupt acceptance without using a time slot portion.

[0010] The interrupt control method for the CPU by the interrupt control circuit for the CPU is the same as the interrupt control method for the CPU by the interrupt control circuit for the CPU. By generating an interrupt request pulse signal in synchronization with a signal and transmitting an interrupt request pulse signal to a pulse position that is a time slot portion corresponding to an interrupt request number that is a number assigned to the interrupt generation circuit, The interrupt request pulse detector detects an interrupt request pulse signal by an interrupt request pulse detection circuit, detects a pulse position as a time slot by a pulse position detector, and outputs an interrupt request corresponding to the pulse position. Number in the interrupt request number register, The interrupt request number is notified from the CPU bus to the interrupt line controller by a request pulse signal. The interrupt line controller arbitrates an interrupt from one interrupt line, and the interrupt request number is higher from the CPU bus by the interrupt request pulse signal. The upper-level interrupt controller arbitrates interrupts coming from a plurality of interrupt lines, notifies the CPU of an interrupt request number from the CPU bus by an interrupt request pulse signal, and the CPU responds by an interrupt response pulse signal. An interrupt response number from the CPU is notified from the CPU bus to a higher-level interrupt control unit.
To the interrupt line control unit, and the interrupt line control unit sends an interrupt response pulse signal to the CPU.
The interrupt response number is notified from the bus to the interrupt response pulse generator, and the interrupt response pulse generator synchronizes the interrupt response pulse signal with the clock signal at a pulse position that is a time slot corresponding to the interrupt response number from the CPU. Generate.

Therefore, according to the present invention, when an interrupt occurs simultaneously, the number of interrupt request signal lines is set to N, and each of the signal lines is divided into M by time slots, and the interrupt pulse position ( M), it is possible to accept a plurality of interrupts up to a maximum of N × M.

[0012]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a timing chart of an interrupt request signal of an interrupt line 1.

In the figure, reference numeral 1 denotes an interrupt controller of the interrupt line 1, 10 denotes a clock generator, 11 denotes an interrupt request pulse detector # 1, 12 denotes an interrupt request number register # 1, and 13 denotes an interrupt response pulse generator # 1. , 14 is an interrupt line 1 control unit # 1, 15 is an interrupt request unit 1, 16 is an interrupt request unit 2, 17 is an interrupt request unit M, 20 is an upper interrupt control unit, and 101 is an interrupt request pulse detection unit # 1. , An interrupt request pulse signal from the interrupt response pulse generation unit # 1, an interrupt request pulse signal for the interrupt line 1 to the interrupt line 1 control unit, and an interrupt line 1 control for the interrupt line 1 , An interrupt response pulse signal from the upper-level interrupt controller, an interrupt request pulse signal from the upper-level interrupt controller, and an interrupt request pulse signal from the upper-level interrupt controller. Signal, 401 is an interrupt request pulse signal of CPU vi, 402 interrupt response pulse signal from the CPU, the 501 CPU bus, the 600 clock signal, N represents an interrupt controller interrupt line N.

As shown in FIG. 1, an interrupt control circuit for a CPU according to the present invention comprises a plurality of interrupt controllers 1, 2,..., N each having one interrupt line, and a plurality of interrupt lines 1, 2,. , N,..., And an upper-level interrupt controller 20 that arbitrates interrupts coming from N. That is, the higher-level interrupt control unit 20 transmits the interrupt control unit 1 of the interrupt line 1,
.., Interrupt line N of interrupt line 2
Arbitrates for the interrupt coming from the interrupt control unit N of FIG.

The interrupt controller 1 of the interrupt line 1 includes a clock generator 10, an interrupt request pulse detector # 1 11, an interrupt request number register # 1 12, an interrupt response pulse generator # 1 13, and an interrupt line 1 controller # , An interrupt request unit 115, an interrupt request unit 216, an interrupt request unit 3,..., An interrupt request unit M17.

Each of the interrupt request units 1, 2,..., M has an interrupt generation circuit for an interrupt request pulse signal line.
The interrupt request pulse detection unit # 111 has an interrupt request pulse detection circuit and a pulse position detection unit.

As shown in FIG. 2, interrupt request units 1, 2,.
.., M, when an interrupt occurs simultaneously, the interrupt request pulse signal 101 is synchronized with the clock signal 600 and the time slot corresponding to the interrupt request number (M), which is the number assigned to the interrupt generation circuit. The request is made by activating the interrupt request pulse signal 101 in the portion. That is, a plurality of interrupts can be accepted by transmitting the interrupt request pulse signal 101 to the pulse position (M), which is the time slot corresponding to the interrupt request number (M).

The interrupt request pulse detecting section # 1 11 detects the interrupt request pulse signal 101 by the interrupt request pulse detecting circuit, detects the pulse position (M) as a time slot by the pulse position detecting section, and outputs the pulse position (M). The interrupt request number (M) corresponding to M) is set in the interrupt request number register # 1 12 and the interrupt request number (M) is sent from the CPU bus 501 to the interrupt line 1 control unit # 114 by the interrupt request pulse signal 201. Notice.

The interrupt line 1 control unit # 114 arbitrates an interrupt from one interrupt line 1 and notifies the interrupt request number (M) from the CPU bus 501 to the higher-level interrupt control unit 20 by the interrupt request pulse signal 301. I do.

The upper-level interrupt control unit 20 arbitrates between N interrupt lines coming from a plurality of interrupt lines 1, 2,..., N, and sends an interrupt request number (M ) To the CPU.

The CPU notifies the higher-level interrupt controller 20 of the interrupt response number (M) from the CPU from the CPU bus 501 by the interrupt response pulse signal 402.

The higher-level interrupt control unit 20 receives the interrupt response number (M) from the CPU from the CPU bus 501 by the interrupt response pulse signal 302 and outputs the interrupt line 1 control unit # 114.
Notify to

The interrupt line 1 control unit # 1 14 outputs the interrupt response number (M) from the CPU bus 501 by the interrupt response pulse signal 202 to the interrupt response pulse generation unit # 1 13
Notify to

The interrupt response pulse generation unit # 1 13
An interrupt response pulse signal 102 is generated in synchronization with the clock signal 600 at a pulse position (M) which is a time slot portion corresponding to the interrupt response number (M) from the PU.

Further, by providing the mode switching unit,
It is possible to switch to a conventional method that enables interrupt acceptance without using a time slot portion for each interrupt request pulse signal line.

[0026]

As described above, according to the present invention, when an interrupt occurs simultaneously, the number of interrupt request signal lines is set to N, and each of the signal lines is divided into M by time slots to generate an interrupt. Identification by the interrupt pulse position (M) of the circuit has an effect that a plurality of interrupts can be received up to N × M.

Further, since the circuit / device configuration can be simplified, there is an effect that the delay in interrupt request acceptance is reduced.

In this way, it is possible to realize an interrupt control circuit capable of accepting a large number of interrupts to the CPU and simplifying the circuit / device configuration, and a method of controlling an interrupt to the CPU by the interrupt control circuit.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of an embodiment of the present invention.

FIG. 2 is a timing chart of an interrupt request pulse signal of an interrupt line 1;

[Explanation of symbols]

Reference Signs List 1 Interrupt control unit of interrupt line 1 10 Clock generation unit 11 Interrupt request pulse detection unit # 1 12 Interrupt request number register # 1 13 Interrupt response pulse generation unit # 1 14 Interrupt line 1 control unit # 1 15 Interrupt request unit 1 16 Interrupt Request unit 2 17 Interrupt request unit M 20 Upper interrupt control unit 101 Interrupt request pulse signal of interrupt line 1 to interrupt request pulse detection unit # 1 102 Interrupt response pulse signal from interrupt response pulse generation unit # 1 201 Interrupt line 1 Interrupt request pulse signal of interrupt line 1 to control unit 202 Interrupt response pulse signal of interrupt line 1 control unit 301 Interrupt request pulse signal of interrupt line 1 to interrupt control unit 302 Interrupt response pulse signal of interrupt control unit 401 CPU Interrupt request pulse signal 402 Interrupt response from CPU The interrupt control unit of the pulse signal 501 CPU bus 600 clock signal N interrupt line N

Claims (3)

[Claims] 1. An interrupt control circuit for a CPU, comprising: a plurality of interrupt control units each having one interrupt line; and a higher-order interrupt control unit for arbitrating interrupts coming from the plurality of interrupt lines. The interrupt control unit includes: a plurality of interrupt request units having an interrupt generation circuit for an interrupt request pulse signal line; and a clock generation unit that generates a clock signal for synchronizing an interrupt request pulse signal and an interrupt response pulse signal. An interrupt request pulse detection unit having an interrupt request pulse detection circuit and a pulse position detection unit; an interrupt request number register in which an interrupt request number which is a number assigned to the interrupt generation circuit is set; Arbitrates the interrupt coming from the CPU and the interrupt request number from the CPU bus by the interrupt request pulse signal. An interrupt line control unit comprising means for notifying the higher-order interrupt control unit, and means for notifying an interrupt response number from the CPU bus to the interrupt response pulse generation unit using an interrupt response pulse signal; and the interrupt response number from the CPU. An interrupt response pulse generating unit that generates the interrupt response pulse signal in synchronization with the clock signal at a pulse position that is a time slot corresponding to the interrupt request unit. By synchronizing the interrupt with the clock signal to generate an interrupt request pulse signal and transmitting the interrupt request pulse signal to a pulse position that is a time slot corresponding to the interrupt request number, a plurality of interrupt requests can be received. Means for enabling, the interrupt request pulse detection unit, The interrupt request pulse detection circuit for detecting the interrupt request pulse signal; the pulse position detection unit for detecting the pulse position which is the time slot portion; and the interrupt request number register for the interrupt request number corresponding to the pulse position. Means for notifying the interrupt request number from the CPU bus to the interrupt line control unit by the interrupt request pulse signal, wherein the higher-order interrupt control unit arbitrates interrupts coming from a plurality of interrupt lines. Means for notifying the CPU of the interrupt request number from the CPU bus by the interrupt request pulse signal; means for receiving the interrupt response number from the CPU from the CPU bus from the CPU by the interrupt response pulse signal; The CPU receives the interrupt response pulse signal from the CPU bus. Means for notifying the interrupt line control unit of the interrupt response number from a CPU.
Interrupt control circuit to PU. 2. The interrupt control circuit for a CPU according to claim 1, further comprising: a mode switching unit configured to switch for each of the interrupt request pulse signal lines to a method that enables an interrupt to be accepted without using the time slot part. C characterized by being
Interrupt control circuit to PU. 3. The interrupt control method for a CPU by an interrupt control circuit for a CPU according to claim 1 or 2, wherein the interrupt request unit synchronizes the interrupt with the clock signal when the interrupts occur simultaneously. And generating the interrupt request pulse signal, and transmitting the interrupt request pulse signal to a pulse position that is a time slot portion corresponding to the interrupt request number that is a number assigned to the interrupt generation circuit. The interrupt request pulse detecting unit detects the interrupt request pulse signal by the interrupt request pulse detecting circuit, detects the pulse position which is the time slot part by the pulse position detecting unit, and The interrupt request number corresponding to the position is stored in the interrupt request number register. And the interrupt request pulse signal is used to notify the interrupt request number from the CPU bus to the interrupt line control unit. The interrupt line control unit arbitrates an interrupt coming from one interrupt line, and By the pulse signal, the C
The upper-level interrupt controller notifies the upper-level interrupt controller of the interrupt request number from the PU bus. The upper-level interrupt controller arbitrates interrupts coming from a plurality of interrupt lines, and uses the interrupt request pulse signal to control the C level.
The CPU notifies the CPU of the interrupt request number from a PU bus, and the CPU notifies an interrupt response number from the CPU to an upper interrupt control unit from the CPU bus by an interrupt response pulse signal. Notifying an interrupt response number from the CPU to the interrupt line control unit from the CPU bus using an interrupt response pulse signal, the interrupt line control unit transmitting the interrupt response number from the CPU bus using the interrupt response pulse signal Notifying an interrupt response pulse generator, the interrupt response pulse generator synchronizes the interrupt response pulse signal with the clock signal at a pulse position that is a time slot portion corresponding to the interrupt response number from the CPU. Interrupt to CPU by interrupt control circuit to CPU characterized by generating Control method.