JPH01173255A - Synchronizing system for plural cpu's - Google Patents

Abstract

PURPOSE:To acquire synchronism free from difference in a minimum time unit used for data processing by detecting the time difference between respective internal clocks of a main CPU and a sub-CPU, which perform the same processing for the same data, to switch the transmission of a processing output. CONSTITUTION:Internal clocks in the minimum time unit used for data processing are generated by respective internal clock means 110 and 120 of a main CPU 11 and a sub-CPU 12 synchronously with the clock from a fundamental clock generating means 10. Each of time difference detecting means 111 and 121 detects the time difference between the internal clock of corresponding one of CPUs 12 and 11 and that of the other; and when the internal clock of the other CPU is delayed by the minimum time unit or longer, an interruption occurs by the detection output and the processing output passing an I/O device 14 is switched to the output of one CPU through a switching means 13, and a timer counter is counted up by corresponding one of counting-up means 112 and 122 of one CPU. Thus, plural CPUs are so synchronized that the difference is not generated in the minimum time unit used for data processing.

Description

Detailed Description of the Invention [Summary Regarding a processing synchronization method for multiple CPUs that perform data processing online, multiple CPUs equipped with internal clock means synchronized with an external basic clock are mutually used for data processing. Multiple CPUs that are synchronized so that there are no differences in time units
The purpose is to provide a synchronization method for the main CP that performs the same processing on the same data.
In an online data processing device in which the U and sub-CPU execute processing that includes a time element based on their respective internal clocks on the same data, each CPU has an internal clock that synchronizes in minimum time units from an external basic clock generation means. means, and compares the outputs of the internal clock means of the other CPU and the internal clock means of the own CPU, and waits for a predetermined time or longer.
and time difference detection means that generates an output when the time of the internal clock of the PU lags behind the internal clock time of the CPU of its own system, and when the time difference detection means generates an output, the CPU
The CPU is configured to increment an internal timer and switch to send the processing output of its own CPU to an external input/output device.

[Industrial Field of Application] The present invention is directed to a plurality of CPUs that perform online data processing.
Regarding the processing synchronization method.

Online data processing is widely used in various fields, including process control for plants (power control, network control, etc.) that processes input data in real time and generates output, and real-time data processing such as online data services. Services that process data manually and output constantly changing data at the request of users, such as when providing paid data services to the public at large, have come to be implemented.

When performing data processing in such cases, in order to improve the reliability of the system, install multiple CPUs, use one as the main system and the other as a subsystem, each performing the same processing, and A method is adopted in which the CPU of the subsystem has a function to continue outputting when the CPU of the subsystem stops.

However, in the case of such a system equipped with multiple CPUs, the CPU
When switching occurs, there must be no difference or contradiction in the contents of the processed data. In other words, the processing results of multiple CPUs are the same at any point in time (this is called processing synchronization)
This is required.

In particular, when the information to be processed includes a real-time element, it is required that clocks providing time information serving as a reference for performing time processing of a plurality of CPUs be synchronized. Moreover, in order to synchronize the processing, it is necessary to use the reference clock for each CPU in the minimum time unit of time used for processing.

Note that this clock is different from a computer's machine clock (used for operating system processing), and refers to the generation of time information (clock by a hard timer) used when processing data that includes a time element. When the machine clock is synchronized with a periodic basic clock from the outside in a dual-system CPU, there is a possibility that the machine clock changes at regular intervals,
This can interfere with the operation of operating systems that use machine clocks for various controls.

However, if the minimum time unit is set to 1 second, for example, an interrupt will be generated for each CPU for clock synchronization processing every 1 second of the reference clock output, which will affect the online data processing that the CPUs are supposed to process. will give.

Therefore, the cycle of the basic clock for synchronization supplied from the outside is 1 minute (60 seconds), and a signal generated every minute is used as the basic clock.

However, with such a one-minute basic clock, the internal clocks of both the main and sub CPUs do not necessarily match in the minimum time unit (at least seconds) used for online data processing.

Therefore, it has been desired to realize a system that synchronizes both CPUs in minimum time units.

[Conventional technology] FIG. 3 shows a block configuration of a conventional example.

In FIG. 3, 30 is a basic clock generation circuit, 31 is a main CPU, 32 is a sub-CPU, and 33 is a main CPU.
3 Which data processing result of L and sub CPU32 is I1?
0 device 34; 34 is a device that accepts and uses the data processed by the CPU; in the case of process control, it is a device that inputs control data; In the case of a service, it represents an I10 device such as a keyboard terminal with a display device.

In the conventional configuration, the main CPU 31 and the sub CPU
The 32 clock circuits 310 and 320 are both synchronized by pulses generated from the basic clock generation circuit 30 at regular intervals (1 minute), and each generates an internal clock in a minimum unit time (second).

The main system CPU 31 and the sub system CPU 32 execute data processing using time elements on the same data using the minimum unit time of internal clock circuits 310 and 320, respectively.

Then, when the main system clock stops or processing stops, the switching circuit 33 is driven and switches, and the sub CPU
32 processing results are supplied to the I10 device 34.

[Problems to be Solved by the Invention] According to the conventional system, the main system CPU 31 and the sub system CPU
This configuration synchronizes both internal clock circuits 310 and 320 of U32.

For this reason, data that needs to be processed in a minimum time unit shorter than the basic clock cycle, such as information that includes a short time element for processing (information - time (time): speed information, for example)
), the respective internal clocks 310 and 320 must be used as the basis.

However, the internal clocks 310 and 320 have the drawback that they are asynchronous with each other in the pulse interval of the basic clock and clock errors are added, so that the results of each data processing will not be the same.

In such a case, the output data of the two CPUs do not match, resulting in a problem that the output data is not continuous when switching from one CPU system to the other CPU system.

The present invention provides a synchronization method for multiple CPUs that synchronizes a plurality of CPtJs, each of which is equipped with an internal clock/clockwise means that synchronizes with an external basic clock, so that there is no difference in the minimum time unit used for mutual data processing. The purpose is to

[Means for solving problems] The basic configuration of the present invention is shown in FIG.

In FIG. 1, 10 is an external basic clock generating means;
11 is the main CPU, and 12 is the sub CPU.

13 is a switching means, and 14 is an I10 device.

Main CPU 1 and sub CPU have the same configuration,
Internal clock means 110, 120, time difference detection means 11
1,121 and stepping means 112,122.

Note that although this basic configuration in FIG. 1 shows the case where two CPUs are installed, the configuration can be similarly configured in the case of three or more CPUs.

In the present invention, the times of the internal clock means of the main CPU and the sub-CPU, which are synchronized at regular intervals by an external basic clock generation means, are compared in the time difference detection means in both the main and sub-CPUs, and When it is detected that the internal clock of the CPU is delayed by more than the minimum time unit than the internal clock of its own system, the result of its own data processing is
It switches the output to the device, generates an interrupt, and increments its own timer counter.

[Operation] In FIG. 1, from the basic clock 10 there is a constant period (1
A synchronization pulse is generated at the main CP
The UII and sub CPU 12 each have an internal clock means 110.
and 120 to execute synchronization processing. Internal clock means 11
0.120 each starts from this synchronization pulse and independently generates a clock (for example, in seconds) for the minimum time unit of processing to execute time counting (hard timer).

The time of this internal clock means is mutually determined by each CPU 11 and 1.
The time difference detection means 111 and 121 provided in 2 are constantly compared. In this comparison, the own CPU
When it is detected that the time of the internal clock means of U of the other system C is delayed by a certain period of time or more than the time of the internal clock means of the other system C, an output is generated, and the output is supplied to the switching means 13 and also to the own stepping means. (112 or 122).

If the switching means 13 is supplying the output data, which is the processing result of the CPU equipped with the time difference detection means that generated the output, to the I10 device 14, the switching means 13 maintains that state, and at that time, the CPU of the other system switches to the I10 device. If the data has been output to l10ii14, switching is performed and the output data of the own system CPU is output to l10ii14.

Further, the stepping means 112 and 122 receive the short outputs of the internal clock means of the own system and the other system when no output is generated from the respective time difference detecting means, and generate an interrupt in the minimum time unit. A timer (interval timer format) set in the memory area of the CPU is incremented (count amplifier) to increment the time count value by one.

The timer incremented by this step is set to be usable as necessary in application processing.

Detection of the time difference by such a time difference detection means is performed in an intermediate interval after the synchronization pulse is generated from the basic clock generation means 10 until the arrival of the synchronization pulse of the next cycle. will not become very large (because it will synchronize with the next basic clock pulse).

Furthermore, by comparing the time differences between the mutual internal clock means using the time difference detection means, it is possible to monitor failures in the internal clocks of the own system, and also to monitor whether the CPUs of other systems have stopped operating.

[Example] FIG. 2 shows a block configuration of an embodiment of the present invention.

In FIG. 2, 20 is a basic clock generation circuit, 21
is the main CPU, 22 is the sub CPU, 23 is the switching circuit,
24 represents the I10 device.

To explain the operation of the configuration of the embodiment, clock pulses generated at one minute intervals from the basic clock generation circuit 20 are supplied to the second conversion clock circuits 210 and 220 of the main CPU 21 and the sub CPU 22, and synchronization processing is performed each time. It will be done. Thereafter, the second-equivalent clock time circuits 210 and 220 generate independent clock times in seconds, but microscopic differences may occur, and these differences may be added up to produce a difference in seconds. be.

The status output of each second conversion clock circuit is provided by the time output circuit 212.
．． 223 to the time input circuit 21 in each other CPU system.
It will be powered by humans on 1.221. The time input circuits 211 and 2
The time information of 21 is supplied to the time difference detection circuits 212 and 222 as inputs of other systems, and receives the time information of the second conversion clock circuits 210 and 220 of the own system, and calculates the time information of the own system. Detects whether there is a delay of 1 second or more in other system time information.

To explain the case of the main CPU 21, the time difference detection circuit 212 outputs an output signal when the time information of the other system of the time input circuit 211 lags the time information of the second conversion clock circuit 210 of the own system by a minimum time unit (1 second) or more. is generated and supplied to the switching signal sending circuit 214.

This switching signal sending circuit 214 responds to this output signal by
A signal is sent to the switching circuit 23. The switching circuit 23 is C
When the switching signal from the PU 21 is received, if the processing result data to be output to the I10 device 24 is supplied from the other system CPU 22, it is switched so that the output data of the own system CPU 21 is supplied.

In the normal state, the interrupt circuit 215 (225) uses an interrupt generated by the time input circuit, and at this point, both the main CPU 21 and the sub CPU 22 are completely synchronized in the minimum time unit.

On the other hand, when the sub CPU 22 stops, the main CPU 21 performs an interrupt operation in the minimum time unit of the clock circuit 210 in terms of seconds.

Furthermore, the output of the switching signal sending circuit 214 is transmitted to the interrupt circuit 21.
5 is input.

That is, the output of the time input circuit 211 is at a high level,
When there is an output from the time output circuit 223 of the partner sub CPU 22, it turns on and off accordingly.

On the other hand, the switching signal sending circuit 214 outputs “0” for self-system switching.
When the signal is being output, the ON/OFF state of the signal from the second conversion clock circuit 210 becomes valid, and the output of the interrupt circuit 215 is applied to the CPU as an interrupt signal.

[Effects of the Invention] According to the present invention, it is possible to synchronize the internal clock circuits of the main CPU and the sub-CPU, and it is possible to completely match processing information including a time element in the outputs of both CPUs. Further, when switching is performed, the switching can be performed in synchronization with the minimum time unit, so the I10 device (utilizing device) can be switched and connected to the own system without delay, and the influence on the outside can be minimized.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the basic configuration of the present invention, FIG. 2 is a diagram showing the configuration of an embodiment of the present invention, and FIG. 3 is a diagram showing the block configuration of a conventional example. In Fig. 1, 10: External basic clock generation means 11: Main CPU 12: Sub CPU 13: Switching means 14: I/O device 110.120: Internal clock means 111.121: Time difference detection means 112.122: stepping means

Claims (1)

[Claims] Main CP that executes the same processing on the same data
In an online data processing device in which a U (11) and a sub CPU (12) execute processing including a time element based on their respective internal clocks on the same data, each CPU (11, 12) has an external basic clock generation means. Internal clock means (110, 120) that synchronizes in the minimum time unit from (10) and the internal clock of the other CPU for a predetermined time or more by comparing the outputs of the internal clock means of the other CPU and the internal clock means of the own CPU. The time of the local CPU
and a time difference detection means (111, 121) that generates an output when it lags behind the internal clock time of the system, and when an output is generated from the time difference detection means (111, 121), the processing output of the CPU of its own system is sent to the external input/output. A synchronization method for multiple CPUs characterized by switching to send data to a device.