JPH09252434A - Solid-state image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce KTC noise generated in a photodiode part by resetting the photodiode by injecting and discharging electric charges to/from the photodiode. SOLUTION: The wiring (RD line) 15 (15-1-15-3) of the drain of a reset transistor 4 is not connected to a power supply line Vdd connected to the drain of an amplification transistor 2 through a selection transistor 3 and is provided independent of the power supply line. Further, the RD line 15 is independent in respective rows. Also, the other end of a vertical signal line 8 is connected to a separation transistor 12 (12-1-12-3) and an amplification capacitance 13 (13-1-13-3) is connected between the separation transistor 12 and a horizontal selection transistor 19. Thus, by injection/discharge operations for turning the RD line 15 to 'L' and discharging the electric charges, the photodiodes 1 of the respective rows are reset independently for the respective rows.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device, and more particularly to an amplification type solid-state image pickup device having an amplification transistor in a unit cell.

[0002]

2. Description of the Related Art In recent years, a solid-state imaging device using an amplification type MOS sensor has been proposed as one of the solid-state imaging devices. This device amplifies an optical signal detected by a photodiode for each cell with a transistor and has a characteristic of high sensitivity.

FIG. 10 is a circuit diagram showing a conventional solid-state image pickup device using an amplification type MOS sensor. Photodiode 1 (1-1-1, 1-1-2, ..., 1-3-3)
Amplification transistor 2 (2-1-) that amplifies the detection signal of
1, 2-1-2,..., 2-3-3), a vertical selection transistor 3 (3-1-1, 1-1) for selecting a line from which a signal is read.
3-1-2,..., 3-3-3), reset transistor 4 (4-1-1, 4-1-2, resetting signal charges)
, 4-3-3) are arranged in a two-dimensional matrix. Although 3 × 3 cells are arranged in the figure, actually more unit cells are arranged.

[0004] Horizontal address lines 6 (6-1, 6-2, 6-
3) is connected to the gate of the vertical selection transistor 3 and determines a line from which a signal is read. Similarly, the reset line 7 wired in the horizontal direction from the vertical shift register 5
(7-1, 7-2, 7-3) is connected to the gate of the reset transistor 4. The source of the amplification transistor 2 is a vertical signal line 8 (8-1, 8-) arranged in the column direction.
2, 8-3), and a load transistor 9 (9-1, 9-2, 9-3) is provided at one end thereof.

The other end of the vertical signal line 8 is connected to the horizontal signal line 11 via a horizontal selection transistor 19 (19-1, 19-2, 19-3) driven by a selection pulse of the horizontal shift register 10. ing.

FIG. 11 is a timing chart showing the operation of this device. When the address pulse 101 for setting the horizontal address line 6-1 to the high level is applied, only the vertical selection transistor 3 of this line is turned on, and the amplification transistor 2 and the load transistor 9 of this line form a source follower circuit. Then, a voltage substantially equal to the gate voltage of the amplification transistor 2, that is, the voltage of the photodiode 1 appears on the vertical signal line 8.

Next, horizontal selection pulses 102 (102-1,..., 102-3) are sequentially applied from the horizontal shift register 10 to the horizontal selection transistor 19, and the horizontal signal line 11
, The signals for one line are sequentially extracted. When the reading of the signal for one line is completed, the reset pulse 103 that sets the reset line 7-1 to the high level is applied, and the reset transistor 4 of this line is turned on to reset the signal charge.

By continuing this operation sequentially on the next line and the next line, all the two-dimensional signals can be read. Here, a voltage corresponding to a change substantially equal to the change in the potential of the photodiode 1 appears on the vertical signal line 8. Assuming that the capacitance of the photodiode 1 is Cs and the capacitance of the vertical signal line 8 is Cv, the signal charge is amplified by Cv / Cs times. Generally, Cv is much larger than Cs.

However, this type of device has the following problems. That is, the characteristic of the conventional type is that the drain wiring of the reset transistor is common to all the lines and is connected to the power supply line Vdd. In this configuration, since the reset transistor is strongly inverted when resetting the photodiode, the noise generated in the photodiode is 2/3 KTC (K: Boltzmann constant,
(T: absolute temperature, C: capacitance of photodiode). And this noise reduces the sensitivity of the solid-state imaging device.

Further, since it is necessary to install the load transistor at the edge of the image pickup region, there is a problem that the element area is large and the element manufacturing process is complicated accordingly. further,
In the source follower operation, since current flows through all the vertical signal lines through the load transistor, there is a problem that the power consumed by the resistance of the load transistor increases the power consumption of the element. Furthermore, although one load transistor is provided for each column, if the characteristics of the load transistor vary, the characteristics of the source follower composed of the load transistor and the pixel amplification transistor will vary from column to column, and thus vertical columns will appear on the playback screen. Output becomes uneven,
There is a problem that the image quality is significantly deteriorated.

In addition to the above problems, there are the following problems. First, there is a difference in sensitivity because the signal storage time differs in the horizontal direction. This is because the reset times are all the same in one line, but the signal read times are different. In FIG. 6, the signal accumulation time 104- of the photodiodes 1-1-1, ..., 1-1-3
1, to 104-3 are not only shorter than the time 105 of one cycle but also different from each other.

Second, even if the potential of the photodiode 1 is the same, a difference in threshold voltage of the amplification transistor 2 appears in the vertical signal line 8. Therefore, two-dimensional noise (fixed noise) corresponding to variations in threshold voltage (fixed This is called pattern noise). The threshold voltage is measured in a state where the drain current of the amplification transistor 2 hardly flows (about 1 microampere). However, the amplification transistor 2 is connected to the load transistor 9 of the current supply source 20 times to 1000 times.
The drain current is doubled. Therefore, not only the variation in the threshold voltage but also the variation in the transistor characteristics at the large drain current becomes fixed pattern noise.

[0013]

As described above, conventionally, in the amplification type solid-state image pickup device, there is KTC noise generated in the photodiode part when the photodiode is reset, and this is a major factor that reduces the sensitivity of the solid-state image pickup device. It was.

Further, it is necessary to install a load transistor in each vertical signal line, which causes a problem that the element area increases and the power consumption increases. The present invention has been made in view of the above circumstances, and an object thereof is to provide an amplification type solid-state imaging device capable of reducing KTC noise generated in a photodiode section and having a high S / N. To do.

Another object of the present invention is to provide an amplification type solid-state imaging device in which the load transistor connected to the source of the amplification transistor can be omitted and the element area and power consumption can be reduced. Especially.

[0016]

[Means for Solving the Problems]

(Structure) In order to solve the above problem, the present invention employs the following structure. That is, the present invention (claim 1)
Solid-state imaging including an imaging region formed by arranging unit cells including photodiodes and means for resetting the diode in a two-dimensional matrix on a semiconductor substrate, and vertical selection means for selecting a readout row of the imaging region In the device, the reset means of the photodiode is characterized by injecting and discharging electric charges from the photodiode.

Further, the present invention (claim 2) includes, on a semiconductor substrate, a photodiode for photoelectric conversion, an amplification transistor for inputting the output of the photodiode to a gate, and a reset transistor for resetting the photodiode. An image pickup area formed by arranging unit cells in a matrix two-dimensional form, a vertical selection means for selecting a read row of the image pickup area, and a column direction for reading a detection signal of a photodiode corresponding to the selected row are arranged. In a solid-state image pickup device including a vertical signal line connected to a source of an amplification transistor and a horizontal selection transistor that sequentially reads a detection signal from these vertical signal lines to horizontal signal lines arranged in a row direction, Wiring of the terminal opposite to the terminal connected to the photodiode (reset drain wiring) Extending in the row direction, and each line of wiring is characterized in that the electrically independent.

Preferred embodiments of the present invention include the following (1) The reset drain wiring is common to the wiring connected to the drains of the amplification transistors in the same row. (2) The reset drain wiring is common to the wiring connected to the drains of the amplification transistors in the adjacent upper or lower rows. (3) By changing the potential of the drain wiring of the reset transistor, charges are injected into and discharged from the photodiode to reset the photodiode. (4) The photodiode is connected to the gate of the amplification transistor via the readout transistor. (5) The photodiode is an embedded photodiode.

Further, according to the present invention (claim 3), unit cells each having a photodiode for photoelectric conversion and an amplification transistor for inputting an output of the photodiode to a gate are arranged in a matrix two-dimensional array on a semiconductor substrate. Image pickup area, vertical selection means for selecting a readout row of the image pickup area, and a plurality of plurality of elements arranged in the column direction for reading the detection signal of the cell corresponding to the selected row and connected to the source of the amplification transistor. In the solid-state image pickup device including the vertical signal lines and horizontal selection transistors for sequentially reading detection signals from the vertical signal lines to the horizontal signal lines arranged in the row direction, the drains of the amplification transistors are independently provided for each row. The signal of the selected row is connected in common to the installed charge injection line in the row direction, and the charge injection line potential is the gate of the amplification transistor. After being set lower than the channel potential potential of, characterized in that it is carried out by being set higher than the vertical signal line potential potential. (Operation) According to the present invention (Claims 1 and 2), the reset transistor is reset in the weak inversion state by resetting the photodiode by the charge injection / discharge operation, so that the noise is reduced to 1/2 KTC. To do.

More specifically, the drain wiring of the reset transistor (reset drain wiring: RD line) is
By forming the wiring independently of the wiring connected to the drain of the amplification transistor through the selection transistor and arranging it independently in each row, the RD line is set to “L” to inject charges and the RD line is set to “H”. The photodiode can be reset by the injection / discharge operation of discharging the charge by discharging. In other words, in order to reset the reset transistor not in the strong inversion state but in the weak inversion state,
The noise can be reduced to 1/2 KTC.

Further, according to the present invention (claim 3), when the signal of the amplifying transistor is read out to the vertical signal line, no current is passed through the load transistor, and the charge injection line independently provided for each row is used. Charge is injected into the vertical signal line. Therefore, it is not necessary to supply a current to the load transistor, and the power consumption of the element can be reduced. Furthermore, since it is not necessary to provide a load transistor, the element area can be reduced and the element manufacturing process can be simplified. In addition, it is possible to prevent vertical nodal output nonuniformity on the playback screen caused by variations in the characteristics of the load transistors.

[0022]

Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 1 is a circuit configuration diagram showing a solid-state imaging device according to the first embodiment of the present invention.

The structure of the unit cell is basically the same as that of the conventional device shown in FIG. That is, the unit cell is composed of an amplification transistor 2 that amplifies a detection signal of the photodiode 1, a vertical selection transistor 3 that selects a line from which a signal is read, and a reset transistor 4 that resets a signal charge, and are arranged in a two-dimensional matrix. There is. Although 3 × 3 cells are arranged in the figure, actually more unit cells are arranged.

The horizontal address line 6 wired in the horizontal direction from the vertical shift register 5 is the vertical selection transistor 3
It is connected to the gate of and determines the line from which the signal is read. Similarly, the reset line 7 wired in the horizontal direction from the vertical shift register 5 is connected to the gate of the reset transistor 4. The source of the amplification transistor 2 is connected to the vertical signal line 8 arranged in the column direction, and the load transistor 9 is provided at one end thereof.

Although the basic structure up to this point is the same as that of the conventional apparatus, the present invention differs from the conventional apparatus in the following points. That is, the drain wiring (RD
Line 15 (15-1, 15-2, 15-3) is not connected to the power supply line Vdd connected to the drain of the amplification transistor 2 via the selection transistor 3 and is provided independently of the power supply line. ing. Furthermore, the RD line 15 is independent in each row.

The other end of the vertical signal line 8 is connected to the separation transistor 12 (12-1, 12-2, 12-3), and the separation transistor 12 and the horizontal selection transistor 19 are connected.
And an amplification capacitor 13 (13-1, 13-2, 13-
3) is connected. The separation transistor 12 and the amplification capacitor 13 may be omitted, and the vertical signal line 8 may be directly connected to the horizontal selection transistor 19 as shown in FIG.

In the present embodiment, the reset transistor 4
The drain wiring (RD line) 15 is provided independently of the power supply line Vdd, and the RD line 15 is arranged independently in each row. Therefore, the photodiodes 1 in each row can be reset independently in each row by an injection / discharge operation in which the RD line 15 is set to “L” to inject the charge and then set to “H” to discharge the charge. In this case, since the reset transistor 4 is reset in the weak inversion state, the noise generated in the photodiode 1 is reduced to 1/2 KTC.

FIG. 2 is a timing chart showing the operation in this embodiment. After the signal is read in the horizontal blanking period, the potential of the RD line 15 is set to "L",
Charge is injected by setting the reset gate to "H". After that, the potential of the RD line 15 is set to "H" and the reset gate is set to "H" again to discharge the charges.

As a result, the reset transistor 4 can be driven in a weak inversion state in which the drain is 5 V and the gate is 3 V, for example, and the injection operation can be performed. Therefore, the noise generated in the photodiode 1 can be reduced to 1/2 KTC. You can

Further, in this embodiment, the separation transistor 12 is provided between the vertical signal line 8 and the horizontal selection transistor 19.
By providing the amplifying capacitor 13 and the amplification capacitor 13, not only the signal storage time can be made closer to the time of one cycle, but also the difference in the storage time in one line can be eliminated, whereby the horizontal direction due to the difference in the signal storage time can be eliminated. It is also possible to eliminate the difference in sensitivity.

In the embodiment shown in FIG. 1, the RD line 15 is provided independently for each row.
Was provided. However, even if the RD line is common to all rows, the same effect as that of the embodiment of FIG. 1 can be obtained by using the operation timing of FIG. However, in this case, the RD lines of all rows are driven when the photodiodes 1 of one row are reset. Therefore, every time the photodiodes 1 in each row are reset, the capacitances of the RD lines in all the rows are driven, and the power consumption is significantly increased. Therefore, making the RD line of the embodiment of FIG. 1 independent in each row is advantageous in terms of power consumption. Alternatively, even if the RD lines of two adjacent rows are made common and the RD lines are made independent for every two rows, it is very advantageous in terms of power consumption as compared to common to all rows. (Second Embodiment) FIG. 3 is a circuit configuration diagram showing a solid-state imaging device according to the second embodiment of the present invention. The same parts as those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted.

The difference between this embodiment and the first embodiment described above is that the wiring connected to the drain of the amplification transistor 2 is independent for each row. Then, the RD wiring 15 of the adjacent row is shared with the wiring of the drain of the amplification transistor 2.

Even with such a configuration, since the RD line 15 of each row is independent, it is possible to reset by injecting / exhausting charges as in the first embodiment. (Third Embodiment) FIG. 4 is a circuit configuration diagram showing a solid-state imaging device according to the third embodiment of the present invention. The same parts as those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted.

This embodiment differs from the first and second embodiments in that the photodiode 1 is a read transistor 16
It is characterized in that it is connected to the amplification transistor 2 via (16-1, 16-2, 16-3). In addition, 1 in the figure
Reference numeral 7 (17-1, 17-2, 17-3) is a read line connected to the gates of the read transistors 16 in the same row.

With such a structure, the detection capacitance, which is the capacitance connected to the gate of the amplification transistor 2, can be reduced. Since the signal amplification factor of the cell portion is determined by the ratio of the wiring capacitance to the detection portion, it is desirable that the detection portion has a small capacitance in order to increase the amplification factor. The larger the photodiode area is, the better the light utilization rate is. However, when the photodiode 1 is directly connected to the gate of the amplification transistor 2, the larger the photodiode area, the larger the detection capacitance becomes. Since the photodiode 1 is independent of the detection unit, the structure of FIG. 3 has an advantage that the detection capacitance of the detection unit can be reduced while increasing the photodiode area and the light utilization rate.

Also in this embodiment, the RD line 15 is independent in each row, and the noise in the photodiode 1 can be reduced by resetting the photodiode 1 by injecting and discharging charges.

FIG. 5 is a block diagram of a unit cell including a sectional view of the detector and the photodiode when the photodiode has a structure of an embedded photodiode in the embodiment of the configuration of FIG. The potential distribution during charge reading is also shown. The embedded photodiode has a p-layer Si surface layer to prevent a dark current generated on the Si surface.

In the case of the embedded photodiode, the signal charge can be completely transferred by applying a sufficiently large voltage to the gate of the read transistor, and the photodiode can be completely depleted. In this case, K is for complete transfer.
TC noise does not occur. However, at a low gate voltage, complete transfer becomes difficult due to potential pockets as shown in FIG. Therefore, when the read transistor is operated in the strong inversion state and the photodiode 1 is reset, 2/3 KTC noise is generated. Although power consumption can be reduced by lowering the power supply voltage of the solid-state image sensor, it is necessary to transfer the signal charge from the photodiode with a low gate voltage for that purpose.

In the case of incomplete transfer, noise can be reduced by resetting by injecting and discharging charges as in this embodiment. Further, in the method of resetting the photodiode by simply reading out the charge by the incomplete transfer, transfer residual occurs and an afterimage occurs. On the other hand, as in the present embodiment, this afterimage can be eliminated by injecting / discharging charges and resetting.

FIG. 12 is a circuit configuration diagram in which a noise canceller is arranged in the horizontal signal reading section in the embodiment of FIG. In addition to the components shown in FIG.
1, a clamp transistor 22 is added. FIG.
Also in the second embodiment, the KTC noise generated in the photodiode 1 can be reduced and the afterimage can be suppressed as in the case of FIG.

FIG. 6 is a timing chart showing the operation in this embodiment. In FIG. 6A, in the horizontal blanking period, the potential of the address line 6 is set to “H” and RD is set.
The line 15 is set to "L" and the reset gate is set to "H" to inject charges. Then, the RD line 15 is set to "H" and the reset gate is set to "H" again to discharge the charges. Then, the read gate is turned on to read the signal.

In this operation, resetting of the signal detection unit 20 connected to the gate of the amplification transistor 2 is performed by injecting charge.
It is done by discharge. Therefore, in this operation, the KTC noise generated in the signal detection unit 20 is reduced to 1/2 KTC. In this case, it is desirable to completely transfer the signal charges accumulated in the photodiode 1 by turning on the read transistor 16.

In FIG. 6B, in the horizontal blanking period, the potential of the address line 6 is set to "H", the RD line 15 is set to "L", and the reset gate is set to "H" to inject charges. Next, the RD line 15 is set to “H” and the reset gate is set to “H” again to discharge the charge from the gate portion of the amplification transistor 2. Then, the read transistor is turned on to read the signal.

Then, the RD line 15 is set to "L", the reset gate is set to "H", and the read gate is set to "H" to inject charges in the photodiode portion. Next, the RD line 15 is set to "H", the reset gate is set to "H" again, and the read gate is set to "H" again to discharge charges.

In this operation, both the detector 20 and the photodiode 1 are reset by the charge injection / discharge operation, and the KTC noise is reduced to 1/2 KTC.
At the same time, it is possible to suppress an afterimage caused by incomplete transfer of signal charges from the photodiode.

In FIG. 6C, in the horizontal blanking period, the potential of the address line 6 is set to "H", the RD line 15 is set to "H", and the reset gate is set to "H" to discharge charges. Then, the read gate is turned on to read the signal. Then, the RD line 15 is set to "L", the reset gate is set to "H" again, and the read gate is turned on to inject charges. Next, the RD line 15 is set to "H", the reset gate is set to "H" again, and the read gate is turned on to discharge the charges.

Also in this operation, the photodiode 1
The charge has been injected and discharged to and reset.
TC noise is reduced to 1/2 KTC, and afterimage is also suppressed.

Here, the signal reading may be performed once or may be performed twice using a noise canceller. The case of reading twice using the noise canceller will be described in more detail with reference to FIG. In the first signal reading, the signal detection unit 20 is reset, and the vertical signal line 8 is at the potential corresponding to the reset potential of the signal detection unit 20. In this state, the clamp transistor 22 is turned on, and the potential of the signal storage unit 23 is the source potential of the clamp transistor. After this, the signal charge of the photodiode 1 is read out to the signal detection unit 20, and the potential of the signal detection unit 20 changes accordingly.
The potential change of the signal detection unit 20 at this time causes a potential change in the signal storage unit 23 through the vertical signal line 8. After that, the separation transistor 12 is turned off. Therefore, the potential change of the signal detection unit 20 due to this signal reading is caused by the signal storage unit 23.
Is accumulated in

As described above, in the case where the noise canceller is used to detect the potential change at the time when the signal charge of the signal detection unit 20 is not reset and after the signal charge is read out, the KTC noise at the signal detection unit 20 is completely eliminated. Since it can be suppressed, the reset means of the signal charge detection unit may operate the reset transistor 4 in the strong inversion state in which the KTC noise becomes 2/3 KTC. Of course, the same effect as that of the embodiment of FIG. 4 can be obtained by injecting / exhausting charges into / from the photodiode. (Fourth Embodiment) FIG. 7 is a circuit configuration diagram showing a solid-state imaging device according to the fourth embodiment of the present invention. In the figure, the same parts as those in FIG. 10 are designated by the same reference numerals, and detailed description thereof will be omitted.

The present embodiment is different from the conventional device shown in FIG. 10 in that the load transistor is omitted and the drain of the amplification transistor 2 is common to each row to the charge injection lines 201, 202 and 203 installed in each row. Is connected to.

FIG. 8 is a potential diagram of the amplification transistor, the vertical selection transistor, and the charge injection line for explaining the operation of the device of FIG. First, after turning on the vertical selection transistor in the row from which a signal is read (a), the charge injection line corresponding to the selected row is set to the “L” level, and charges are injected into the vertical signal line through the gate of the amplification transistor. (B). Then, the charge injection line potential is returned to the "H" level again (c). Since the vertical signal line potential becomes substantially equal to the channel potential of the amplification transistor, the signal charge on the gate potential of the amplification transistor is called out to the vertical signal line.

FIG. 9 shows the operation timing of the device. Although the operation is basically the same as that shown in FIG. 11, the present embodiment is characterized in that a pulse is applied to the charge injection lines 201, 202, 203 subsequent to the address pulse 101, 102, 103. .

As described above, according to this embodiment, it is not necessary to use the load transistor when reading the signal of the amplification transistor 2 to the vertical signal line 8. Therefore, the power consumed by the load transistor can be eliminated, and the power consumption can be reduced. The present invention is not limited to the above-described embodiments, and can be implemented with various modifications without departing from the scope of the invention.

[0054]

As described in detail above, the present invention (Claim 1,
According to 2), by resetting the photodiode by the charge injection / discharge operation, it is possible to reduce the noise generated in the photodiode section, and it is possible to realize a solid-state imaging device with high S / N. Become.

Further, according to the present invention (claim 3), it is not necessary to use the load transistor when reading the signal of the amplification transistor to the vertical signal line. Therefore, the element area can be reduced. Moreover, the element manufacturing process can be shortened. Also, because there is no load transistor,
The power consumed by the load transistor can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing a solid-state imaging device according to a first embodiment.

FIG. 2 is a timing chart showing an operation in the first embodiment.

FIG. 3 is a circuit configuration diagram showing a solid-state imaging device according to a second embodiment.

FIG. 4 is a circuit configuration diagram showing a solid-state imaging device according to a third embodiment.

FIG. 5 is a diagram showing a configuration of a unit cell according to a third embodiment.

FIG. 6 is a timing chart showing an operation in the third embodiment.

FIG. 7 is a circuit configuration diagram showing a solid-state imaging device according to a fourth embodiment.

FIG. 8 is a potential diagram of a unit cell for explaining the operation of the fourth embodiment.

FIG. 9 is a timing chart showing the operation of the fourth embodiment.

FIG. 10 is an example of a circuit diagram of a conventional MOS solid-state image sensor.

11 is an operation timing chart of the sensor of FIG.

FIG. 12 is a circuit configuration diagram in which a noise canceller is arranged in a horizontal signal reading unit in the embodiment of FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Photodiode 2 ... Amplification transistor 3 ... Vertical selection transistor 4 ... Reset transistor 5 ... Vertical shift register 6 ... Horizontal address line 7 ... Reset line 8 ... Vertical signal line 9 ... Load transistor 10 ... Horizontal shift register 11 ... Horizontal signal line 12 ... Separation transistor 13 ... Amplification capacitance 15 ... Reset drain wiring (RD line) 16 ... Read transistor 19 ... Horizontal selection transistor 20 ... Signal detection unit 21 ... Separation capacitor 22 ... Clamp transistor 23 ... Signal storage unit

Claims (3)

[Claims] 1. A unit cell 2 including a photodiode and a means for resetting the diode on a semiconductor substrate.
In a solid-state imaging device including an imaging region arranged in a dimension and a vertical selection unit that selects a readout row of the imaging region, the photodiode reset unit is configured to inject and discharge charges to and from the photodiode. A solid-state imaging device characterized by the above. 2. A unit cell including a photodiode for photoelectric conversion, an amplification transistor for inputting an output of the photodiode to a gate, and a reset transistor for resetting the photodiode is arranged in a matrix on a semiconductor substrate.
An imaging region arranged in a dimension, a vertical selection unit that selects a readout row of this imaging region, and a column direction in which a detection signal of a photodiode corresponding to the selected row is read out and the source of the amplification transistor is arranged. A solid-state imaging device comprising: connected vertical signal lines; and a horizontal selection transistor that sequentially reads out detection signals from these vertical signal lines to horizontal signal lines arranged in a row direction, wherein the solid-state imaging device is connected to the photodiode of the reset transistor. A solid-state imaging device, wherein the wiring of the terminal on the side opposite to the terminal extends in the row direction, and the wiring of each row is electrically independent. 3. An imaging region in which unit cells each having a photodiode for photoelectric conversion and an amplification transistor for inputting an output of the photodiode to a gate are arranged in a matrix two-dimensionally on a semiconductor substrate, and the imaging region. Vertical selection means for selecting a read row of the region, a plurality of vertical signal lines arranged in the column direction for reading the detection signal of the cell corresponding to the selected row and connected to the source of the amplification transistor, and these vertical signal lines In a solid-state imaging device including a horizontal selection transistor that sequentially reads detection signals from a signal line to a horizontal signal line arranged in a row direction, the drain of the amplification transistor is connected to a charge injection line, and the charge injection line potential is an amplification transistor. By setting the potential lower than the channel potential of the gate of, the charge is injected from the charge injection line to the vertical signal line, and then The solid-state imaging device is characterized in that a signal is read by setting the potential higher than the vertical signal line potential.