JP4391843B2 - Solid-state imaging device - Google Patents

Description

  The present invention relates to a solid-state imaging device capable of using a collective shutter operation mode.

  As a general readout method of pixel signals in the MOS type solid-state imaging device, there is an XY address readout method. An XY address reading method of the MOS type solid-state image pickup device will be described with reference to FIGS. FIG. 11 shows a general pixel configuration used for a MOS type solid-state imaging device. 1100 indicates a single pixel, 1106 is a photodiode that performs photoelectric conversion, 1102 is a transfer transistor that transfers signal charges generated by the photodiode 1106 to the memory 1105, and 1101 is for resetting the memory 1105 and the photodiode 1106 The reset transistor 1104 is an amplifier for amplifying and reading out the voltage level of the memory 1105, and 1103 is a selection transistor for selecting a pixel and transmitting the output of the amplifier 1104 to the vertical signal line 1114. Here, the portions other than the photodiode 1106 are shielded from light.

  Reference numeral 1110 denotes a pixel power supply line, which is electrically connected to the drain side of the amplifier 1104 and the drain side of the reset transistor 1101. Reference numeral 1111 denotes a reset line for resetting pixels for one row, which is electrically connected to the gates of the reset transistors 1101 of the pixels for one row. Reference numeral 1112 denotes a transfer line for transferring the signal charge of the pixels for one row to the memory 1105 of each pixel, which is electrically connected to the gate of the transfer transistor 1102 for one row. Reference numeral 1113 denotes a selection line for selecting pixels for one row, which is electrically connected to the gates of the selection transistors 1103 for one row. As described above, a pixel configuration using four transistors (hereinafter referred to as a 4Tr pixel) realizes a photoelectric conversion function, a reset function, an amplification read function, a temporary memory function, and a selection function.

  FIG. 12 shows a general basic configuration of an XY address reading type solid-state imaging device. The light receiving unit is configured by a pixel array 1200 in which pixels 1100 are arranged in m rows × n columns. The vertical scanning circuit 1204 performs scanning while outputting a row selection signal φSELi (i = 1, 2, 3,... M), a row reset signal φRSi, and a row transfer signal φTxi to the pixel array 1200. At this time, the row selection signal φSELi is transmitted to the gate of the selection transistor 1103 of the pixel in the i-th row via the selection line 1113, and the row reset signal φRSi is transmitted to the reset transistor 1101 of the pixel in the i-th row via the reset line 1111. The row transfer signal φTxi is transmitted to the gate, and is transmitted to the gate of the transfer transistor 1102 of the pixel in the i-th row via the transfer line 1112. When reading the signal of the pixel in the i-th row, the row selection signal φSELi of the i-th row is input from the vertical scanning circuit 1204 to the pixel array 1200, and when the photodiode 1106 of the pixel in the i-th row is reset. The row reset signal φRSi and the row transfer signal φTxi of the i-th row are input from the vertical scanning circuit 1204 to the pixel array 1200. When resetting the memory 1105 of the pixel in the i-th row, the row reset signal φRSi in the i-th row is input from the vertical scanning circuit 1204 to the pixel array 1200. When the signal charge of the pixel in the i-th row is transferred to the memory 1105, the row transfer signal φTxi in the i-th row is input from the vertical scanning circuit 1204 to the pixel array 1200.

  The signal of the pixel in the selected i-th row is subjected to processing such as FPN (fixed pattern noise) cancellation in the row parallel processing circuit 1201, and the processing result is stored in the line memory 1202. Thereafter, the horizontal scanning circuit 1203 outputs a horizontal selection signal φHj (j = 1, 2, 3,... N), thereby scanning while sequentially selecting pixel signals for one row stored in the line memory 1202. And read. By sequentially performing this process from the first row to the m-th row, the signals of all the pixels in the pixel array 1200 can be scanned and read out.

  FIG. 13 shows the driving timing of such a solid-state imaging device of the XY address reading method. Next, the operation will be described by paying attention to the reading period T1. The row selection signal φSEL1 is output from the vertical scanning circuit 1204, and then the row reset signal φRS1 is output, whereby the pixel in the first row is selected and the reset level of the pixel is read out. Further, the row transfer signal φTx1 is output from the vertical scanning circuit 1204, whereby the signal charge generated in the photodiode 1106 in the first row is transferred to the memory 1105, and the signal level of the pixel is read out. Thereafter, the row reset signal φRS1 and the row transfer signal φTx1 are output, and the photodiode 1106 and the memory 1105 are reset. Here, the accumulation period of the signal to be read is a period indicated by Ta in the figure from immediately after the photodiode 1106 is reset in the previous frame to when it is transferred. Further, a difference process between the signal level and the reset level is performed during the period T1, and the signal is stored in the line memory 1202. Thereafter, the horizontal scanning circuit 1203 is operated to output the horizontal selection signal φHj (j = 1, 2, 3,... N), thereby outputting the first row signal. Thereafter, the same operation is performed up to m rows.

  In such a normal XY address reading method, the signal accumulation time differs for each row. More specifically, the first row to be read first and the m-th row to be read last are equivalent to one frame at maximum. Since the times are different, there is a problem that the image is distorted when a high-speed moving object is photographed.

  As a method for solving this, there is a batch shutter reading method. This reading method will be briefly described. FIG. 14 shows the drive timing at the time of the collective shutter operation of the solid-state imaging device having the same basic configuration as FIG. 11 and FIG. First, the row reset signals φRS1 to φRSm of all rows and the row transfer signals φTx1 to φTxm of all rows are simultaneously output from the vertical scanning circuit 1204, thereby resetting the photodiodes 1106 of the pixels for all rows. Thereafter, with a certain signal accumulation period, the row transfer signals φTx1 to φTxm of all rows are simultaneously output from the vertical scanning circuit 1204, so that the signals accumulated in the photodiodes 1106 of the pixels for all rows within a certain period. The charges are transferred to the memory 1105 at the same time for all rows. A batch shutter operation is performed by such an operation.

  Next, reading of the signals stored in the memory 1105 is started line by line. First, the row selection signal φSEL1 is output from the vertical scanning circuit 1204, whereby the pixels in the first row are selected and the signal level of the pixels is read out. Further, the row reset signal φRS1 is output from the vertical scanning circuit 1204, whereby the memory 1105 in the first row is reset and the reset level of the pixel is read out. When the signal readout of the pixels in the first row is completed, the pixels in the second row are selected, and the signal level and the reset level are read out. By performing this scanning up to the m-th row, signal reading for one frame is performed.

Here, in order to simplify the explanation, the horizontal scanning pulse φHj of the horizontal scanning circuit 1203 is not shown, but φHj (j = 1, 2, 3,... N) is not changed from the signal reading of the i-th row. It is output until the signal reading of i + 1 row.
JP 2002-64751 A JP 2003-17677 A

  In general, when a high-luminance subject is imaged by the XY address readout method, excess charges generated by the photodiode are discharged to the pixel power supply via the substrate or the reset transistor of the pixel. In the 4Tr pixel shown in FIG. 11, a part of the excess charge is discharged to the pixel power supply line 1110 via the transfer transistor 1102, the memory 1105, and the reset transistor 1101. When the collective reset operation is performed with the basic configuration of the 4Tr pixels, the image information at the same time can be acquired in the pixels of all rows, but the period from the signal accumulation start to the signal readout and the readout start time are different. When a high-brightness object is reflected before the signal is read, there is a problem that an excessive image is mixed into the signal charges transferred to the memory in a lump and an appropriate image cannot be obtained. This problem becomes more conspicuous as the line is read later, that is, closer to the last read line (m-th line).

  As a countermeasure against this problem, an overflow drain structure generally used in a CCD (charge coupled device) type imaging device, for example, a horizontal overflow drain (hereinafter referred to as LOD) or a vertical overflow drain (hereinafter referred to as VOD) is used. Although it can be used, it is possible to prevent excessive charge from being mixed into the memory, but it causes a reduction in the capacitance (saturation charge) of the photodiode, and it is difficult to achieve high image quality due to a decrease in S / N during the daytime. There is.

  The present invention has been made paying attention to this point, and an appropriate image can be obtained even when a high-brightness object is reflected during the readout period during the collective shutter operation, and the S / N at the time of light is reduced. An object of the present invention is to provide a solid-state imaging device that does not.

In order to solve the above problems, the invention according to claim 1 is directed to a photoelectric conversion unit that performs photoelectric conversion, a memory that temporarily stores signal charges accumulated in the photoelectric conversion unit, and the signal A transfer unit for transferring charges to the memory; a reset unit for resetting the photoelectric conversion unit and the memory; an amplification unit for amplifying and reading a signal stored in the memory; and a potential barrier level And a pixel unit in which a plurality of pixels including a charge discharging unit for discharging signal charges generated in the photoelectric conversion unit are arranged two-dimensionally, and the pixels are sequentially scanned and read. A scanning circuit; and a charge discharging control unit configured to control a potential barrier level of the charge discharging unit to be lower than a potential barrier level of the transfer unit during a sequential reading period by the scanning circuit . Conductive The memory, the transfer unit, the reset unit, the amplification unit, and the charge discharge unit are formed in a first semiconductor region formed of a semiconductor having a conductivity type opposite to the first conductivity type. Is formed in a second semiconductor region formed of a semiconductor having the same conductivity type and high impurity concentration as the semiconductor of the first semiconductor region on the semiconductor substrate to constitute a solid-state imaging device. Examples of the solid-state imaging device according to claim 1 correspond to Example 1 and Example 2.

According to a second aspect of the present invention, there is provided a photoelectric conversion unit that performs photoelectric conversion, a memory for temporarily storing signal charges accumulated in the photoelectric conversion unit, and for transferring the signal charges to the memory A transfer unit, a reset unit for resetting the photoelectric conversion unit and the memory, an amplification unit for amplifying and reading a signal stored in the memory, and a potential barrier level being changeable, A plurality of pixels including two or more pixels including a charge discharging unit for discharging signal charges generated in the photoelectric conversion unit, a scanning circuit that sequentially scans and reads the pixels, and the scanning circuit during sequential readout period, and a charge discharging control unit for controlling the potential barrier level of the charge discharging portion lower than the potential barrier level of the transfer unit, the transfer unit and the charge discharging part from the MOS transistor Ri, wherein a gate terminal of the transfer unit, and the gate terminal according to the charge discharging section, and constitutes the solid-state imaging device are arranged symmetrically a position to each other with respect to substantially the center of the photoelectric conversion portion . Then, in the embodiment of the solid-state imaging device according to the second aspect, the third embodiment corresponds.

According to the solid-state imaging device of the first aspect, the potential barrier level in the charge discharging unit is set lower than the potential barrier level in the transfer unit only at the time of signal readout, thereby reducing the capacity of the photoelectric conversion unit during signal charge accumulation. It requires not, and at the time of signal readout with an excess charge due to incidence of high-intensity light as possible out control so as not mixed into memory, does not change the characteristics of the transistors of the peripheral circuit and the pixel, even when changing the potential barrier level Can be. In the solid-state imaging device according to the second aspect , the potential barrier level in the charge discharging unit is set lower than the potential barrier level in the transfer unit only at the time of signal readout , thereby reducing the capacity of the photoelectric conversion unit during signal charge accumulation. It is possible to control so that excessive charge due to the incidence of high-intensity light is not mixed into the memory at the time of signal readout, and the charge discharging unit and the transfer unit are configured similarly and symmetrical with respect to the center of the photoelectric conversion unit The optical symmetry of the photoelectric conversion unit can be improved by arranging in the above.

  Next, the best mode for carrying out the invention will be described.

First, a first embodiment of a solid-state imaging device according to the present invention will be described with reference to FIGS. The first embodiment corresponds to the first and second embodiments of the present invention. FIG. 1 shows a cross section of a pixel in this embodiment in which a VOD structure is added to the 4Tr pixel shown in FIG. 11, and the other basic configuration is the same as that shown in FIG. In FIG. 1, a P ⁻ type semiconductor region 122 and a P type semiconductor region 121 formed at a higher concentration and shallower than the P ⁻ type semiconductor region 122 are formed on an N type semiconductor substrate 120. On the surface of the P ⁻ type semiconductor region 122, there is a high concentration N ⁺ type impurity region 107, and an N ⁺ −P ⁻ photodiode 106 is formed. In the P-type semiconductor region 121, a transfer transistor 102 for transferring electrons generated by the photodiode 106 to the memory 105, a reset transistor 101 for resetting the photodiode 106 and the memory 105, and a voltage of the memory 105 A read amplifier 104 for amplifying and reading the level, and a selection transistor 103 for connecting the output of the read amplifier 104 to a vertical signal line (not shown) are formed. In FIG. 1, the read amplifier 104 and the selection transistor 103 are schematically shown.

The N-type semiconductor substrate 120 is applied with a substrate voltage V-sub set to a high voltage (for example, 5 V) in order to discharge excess electrons, thereby forming a VOD structure. The substrate voltage V-sub is controlled by the charge discharge control unit 130. A ground voltage GND is applied to the P-type semiconductor region 121 and the P ⁻ -type semiconductor region 122 via a contact 108. The drain side of the reset transistor 101 is connected to the pixel power supply VDD. Since the impurity concentration of the P ⁻ -type semiconductor region 122 is low (for example, about 1 × 10 ¹⁵ ), the depletion layer extends in the depth direction in the photodiode 106, resulting in high sensitivity. Further, by increasing the substrate voltage V-sub, it becomes easy to lower the potential barrier against electrons in the VOD structure. At this time, since the P-type semiconductor region 121 is formed shallow and is set to a high concentration (for example, about 1 × 10 ¹⁷ ), the change in the substrate voltage V-sub compared to the P ⁻ -type semiconductor region 122 is achieved. Can be reduced (for example, about 1/10).

  FIG. 2 shows the drive timing when the collective shutter operation is performed in the solid-state imaging device using the pixels shown in FIG. Since the pulse timing other than the substrate voltage V-sub is the same as that described in FIG. 14, the description thereof is omitted. The substrate voltage V-sub is controlled by the charge discharge control unit 130 so that the potential barrier level with respect to electrons in the VOD structure is the same as or higher than the potential barrier level in the transfer transistor 102 during the signal accumulation period. During the signal readout period according to, the potential barrier level in the VOD structure is controlled to be lower than the potential barrier level in the transfer transistor 102. At this time, the substrate voltage V-sub only needs to change the potential barrier level by about several hundred mV, and a particularly large voltage that completely resets the photodiode 106 is not required.

  3 to 6 show the potential distribution (A-A 'in FIG. 1) in the depth direction of the photodiode 106 and the photodiode 106 in the pixel structure shown in FIG. FIG. 3 is a diagram illustrating a potential distribution (BB ′ in FIG. 1) on the surface from the reset transistor 101 to the pixel power supply VDD in correspondence with the drive timing shown in FIG.

  FIG. 3 shows the potential distribution at the time of batch reset. By setting the gates of the transfer transistor 102 and the reset transistor 101 to the H level, electrons generated and accumulated by the photodiode 106 are discharged through the pixel power supply VDD. At this time, the potential barrier level of the VOD structure is controlled to a high level. FIG. 4 shows the potential distribution during the signal accumulation period. By setting the gates of the transfer transistor 102 and the reset transistor 101 to L level, the photogenerated electrons can be stored in the photodiode 106. FIG. 5 shows the potential distribution during batch transfer. The electrons stored in the photodiode 106 are transferred to the memory 105 by setting the gate of the transfer transistor 102 to the H level. FIG. 6 shows the potential distribution in the sequential readout period. The electrons generated during the sequential reading period are discharged to the substrate without being mixed into the memory 105 by lowering the potential barrier level of the VOD structure.

  When a VOD structure generally used in a CCD (charge coupled device) type image pickup device is applied to a MOS type image pickup device as it is, the potential barrier level of the excess charge discharging path from the photodiode to the substrate is changed by changing the substrate voltage. When trying to control, there is a problem that the transistor characteristics in the peripheral circuit and the pixel change, but even if the substrate voltage V-sub is changed by the pixel configuration in FIG. 1 and the drive timing in FIG. The potential barrier level can be controlled without changing the circuit characteristics, and an appropriate image can be obtained even when a high-luminance subject is reflected during the readout period during the collective shutter operation, and at the time of S A solid-state imaging device in which / N does not decrease is obtained.

  Various modifications can be made in this embodiment. For example, the photodiode 106 may be a buried photodiode and is not particularly limited. In this embodiment, the cancellation of kTC noise (thermal noise accompanying switching of the reset transistor) is not particularly described, but charge-voltage conversion is performed as disclosed in JP-A-2002-64751. And a second transfer transistor for controlling charge transfer to the capacitor, or a configuration capable of complete depletion reset of the memory 105 as disclosed in Japanese Patent Laid-Open No. 2003-17677. By using it, the kTC noise and the fixed pattern noise accompanied by the offset can be canceled by performing signal processing with the CDS circuit (correlated double sampling circuit). In this embodiment, electrons are used as the signal charges. Of course, it is possible to treat the holes as signal charges by changing the power source and the voltage levels of the pulses to H and L by changing the pixel structure to the opposite conductivity type.

Next, a second embodiment of the present invention will be described with reference to FIGS. FIG. 7 shows a cross section of a pixel in this embodiment in which an LOD structure is added to the 4Tr pixel shown in FIG. In FIG. 7, a P ⁻ type semiconductor region 722 and a P type semiconductor region 721 formed at a higher concentration and shallower than the P ⁻ type semiconductor region 722 are formed on a P type semiconductor substrate 720. A high-concentration N ⁺ -type impurity region 707 is formed on the surface of the P ⁻ -type semiconductor region 722, and an N ⁺ -P ⁻ photodiode 706 is formed. In the P-type semiconductor region 721, a transfer transistor 702 for transferring electrons generated by the photodiode 706 to the memory 705, a reset transistor 701 for resetting the photodiode 706 and the memory 705, and a voltage of the memory 705 A read amplifier 704 for amplifying and reading the level, a selection transistor 703 for connecting the output of the read amplifier 704 to the vertical signal line, and a drain 730 and an overflow gate 731 form an LOD structure. In FIG. 7, the amplifier 704 and the selection transistor 703 are schematically shown. The voltage applied to the overflow gate 731 is controlled by the charge discharge control unit 710.

A ground voltage GND is applied to the P-type semiconductor region 721 and the P ⁻ -type semiconductor region 722 through a contact 708. The drain side of the reset transistor 701 and the drain 730 having the LOD structure are connected to the pixel power supply VDD. Since the impurity concentration of the P ⁻ -type semiconductor region 722 is low (for example, about 1 × 10 ¹⁵ ), the depletion layer extends in the depth direction in the photodiode 706, resulting in high sensitivity.

  In the solid-state imaging device using this pixel, the driving timing when performing the collective shutter operation is the same as the driving timing of the first embodiment shown in FIG. 2 except that the overflow gate 731 is replaced with the timing for controlling the substrate voltage V-sub. Since only the control timing is different, detailed description is omitted. The overflow gate 731 is controlled by the charge discharge control unit 710 so that the potential barrier level for electrons in the LOD structure is the same as or higher than the potential barrier level in the transfer transistor 702 during the signal accumulation period. During the period, the potential barrier level in the LOD structure is controlled to be lower than the potential barrier level in the transfer transistor 702.

  FIG. 8A is a layout diagram in the vicinity of the photodiode 706 of the pixel when the LOD structure shown in FIG. 7 is used, and the same reference numerals as those in FIG. 7 are used. As described above, the overflow gate 731 and the gate of the transfer transistor 702 are made of the same material (for example, polysilicon), and are arranged symmetrically with respect to the center of the photodiode 706. 8B shows a cross section of the pixel portion shown in FIG. 8A. The potential distribution (signal accumulation) of XX ′ in FIG. 7A and FIG. 8B is shown. (Period) is shown in FIG.

  In order to improve the characteristics of the solid-state imaging device, it is necessary to consider optical characteristics. For example, if the oblique incidence dependency is asymmetric, there is a problem that an unnatural image appears as an asymmetry of a light amount drop (brightness shading) in the peripheral part of the captured image. As described above, by arranging the overflow gate 731 and the gate of the transfer transistor 702, the optical symmetry with respect to the light incident on the photodiode 706 of the pixel is improved, and the potential distribution is substantially the same as that of the photodiode 706. Because it is symmetric with respect to the center, the incident angle dependency of the light incident on the photodiode 706 is improved, and as a result, the luminance shading asymmetry of the photographed image is improved and a more natural image can be obtained. Is possible.

  Various modifications can be made in this embodiment. For example, the P-type semiconductor substrate can be changed to an N-type semiconductor substrate as in the first embodiment shown in FIG. The overflow gate 731 and the transfer transistor 702 need only be arranged symmetrically with respect to the approximate center of the photodiode 706, and the arrangement method is not particularly limited.

Next, Embodiment 3 of the present invention will be described with reference to FIGS. 9 has the same basic configuration as that of the pixel in the second embodiment shown in FIG. 7, but differs in that the overflow gate 931 and the contact 908 are electrically connected to a GND wiring (not shown). FIG. In FIG. 9, a P ⁻ type semiconductor region 922 and a P type semiconductor region 921 formed at a higher concentration and shallower than the P ⁻ type semiconductor region 922 are formed on a P type semiconductor substrate 920. A high concentration N ⁺ -type impurity region 907 is formed on the surface of the P ⁻ -type semiconductor region 922, and an N ⁺ -P ⁻ photodiode 906 is formed. The P-type semiconductor region 921 includes a transfer transistor 902 for transferring electrons generated by the photodiode 906 to the memory 905, a reset transistor 901 for resetting the photodiode 906 and the memory 905, and a voltage of the memory 905. A read amplifier 904 for amplifying and reading the level, a selection transistor 903 for connecting the output of the read amplifier 904 to the vertical signal line, and a drain 930 and an overflow gate 931 form an LOD structure. In FIG. 9, the read amplifier 904 and the selection transistor 903 are schematically shown.

A ground voltage GND is applied to the P-type semiconductor region 921 and the P ⁻ -type semiconductor region 922 via a contact 908. The drain side of the reset transistor 901 and the drain 930 of the LOD structure are connected to the pixel power supply VDD.

  In the solid-state imaging device using this pixel, the drive timing when performing the collective shutter operation is the same as that described with reference to FIG. FIG. 10 shows the potential distribution between Y and Y ′ in FIG. 9 when the collective shutter operation is performed in the solid-state imaging device using the pixel having the configuration of FIG. The potential barrier level of the overflow gate 931 is lower than the potential barrier level under the gate of the transfer transistor 902, for example, when N-type impurities are implanted under the overflow gate. Therefore, a potential distribution is obtained such that signal charges generated in the photodiode 906 during the sequential reading period do not enter the memory 905.

  In a solid-state imaging device having a large optical size such as that used in a single-lens reflex camera, when the noise mixed during pixel readout operation, for example, the voltage of a reset line, transfer line, or vertical signal line changes, the capacitance between wiring boards When noise due to coupling occurs, it may take time for the pixel signal voltage level to stabilize. Therefore, there is a problem that the signal readout time becomes long and high-speed readout is difficult. Can be stabilized, and it is possible to function as an LOD structure without requiring wiring for overflow control.

It is sectional drawing which shows the pixel structure of Example 1 of the solid-state imaging device concerning this invention. FIG. 2 is a diagram illustrating drive timing when a collective shutter operation is performed in the solid-state imaging device according to the first embodiment illustrated in FIG. 1. FIG. 6 is a diagram illustrating a potential distribution at the time of batch reset in the first embodiment illustrated in FIG. 1. FIG. 3 is a diagram illustrating a potential distribution during a signal accumulation period in the first embodiment illustrated in FIG. 1. FIG. 6 is a diagram illustrating a potential distribution during batch transfer in the first embodiment illustrated in FIG. 1. FIG. 6 is a diagram illustrating a potential distribution in a sequential read period in the first embodiment illustrated in FIG. 1. It is sectional drawing which shows the pixel structure in the solid-state imaging device which concerns on Example 2 of this invention. FIG. 8 is a plan view and a cross-sectional view showing a layout in the vicinity of a photodiode of a pixel in Example 2 shown in FIG. 7 and a diagram showing a potential distribution. It is sectional drawing which shows the pixel structure in the solid-state imaging device which concerns on Example 3 of this invention. It is a figure which shows the potential distribution at the time of the sequential read-out operation | movement after the collective shutter operation | movement between YY 'of the pixel in Example 3 shown in FIG. It is a circuit block diagram which shows the general pixel structure used for a MOS type solid-state image sensor. 2 is a block diagram illustrating a basic configuration of an XY address readout type solid-state imaging device. FIG. 13 is a diagram showing general drive timing of the solid-state imaging device shown in FIG. FIG. 13 is a diagram showing drive timings during a collective shutter operation of the solid-state imaging device shown in FIG.

101 Reset transistor
102 Transfer transistor
103 selection transistor
104 Read amplifier
105 memory
106 photodiode
107 N ⁺ type impurity region
108 contacts
120 N-type semiconductor substrate
121 P-type semiconductor region
122 P ^- type semiconductor region
130 Charge discharge control unit
701 Reset transistor
702 Transfer transistor
703 Select transistor
704 Read amplifier
705 memory
706 photodiode
707 N ⁺ type impurity region
708 contacts
710 Charge discharge controller
720 P type semiconductor substrate
721 P-type semiconductor region
722 P ^- type semiconductor region
730 drain
731 Overflow gate
901 Reset transistor
902 Transfer transistor
903 selection transistor
904 readout amplifier
905 memory
906 Photodiode
907 N ⁺ type impurity region
908 contacts
920 P-type semiconductor substrate
921 P-type semiconductor region
922 P ^- type semiconductor region
930 drain
931 overflow gate

Claims (2)

A photoelectric conversion unit that performs photoelectric conversion, a memory for temporarily storing signal charges accumulated in the photoelectric conversion unit, a transfer unit for transferring the signal charges to the memory, and the photoelectric conversion And a reset unit for resetting the memory, an amplifying unit for amplifying and reading a signal stored in the memory, and a signal charge generated in the photoelectric conversion unit, the potential barrier level being changeable A plurality of pixels including two or more pixels including a charge discharging unit for discharging
A scanning circuit that sequentially scans and reads the pixels;
During sequentially read period by the scanning circuit, the potential barrier level of the charge discharging unit have a charge discharge control unit for controlling lower than the potential barrier level of the transfer unit,
The photoelectric conversion unit is formed in a first semiconductor region formed of a semiconductor of a conductivity type opposite to the first conductivity type on a first conductivity type semiconductor substrate, and the memory, the transfer unit, and the reset The amplifying unit and the charge discharging unit are formed on the semiconductor substrate in a second semiconductor region formed of a semiconductor having the same conductivity type and high impurity concentration as the semiconductor of the first semiconductor region. a solid-state imaging apparatus characterized by there. A photoelectric conversion unit that performs photoelectric conversion, a memory for temporarily storing signal charges accumulated in the photoelectric conversion unit, a transfer unit for transferring the signal charges to the memory, and the photoelectric conversion And a reset unit for resetting the memory, an amplifying unit for amplifying and reading a signal stored in the memory, and a signal charge generated in the photoelectric conversion unit, the potential barrier level being changeable A plurality of pixels including two or more pixels including a charge discharging unit for discharging
A scanning circuit that sequentially scans and reads the pixels;
A charge discharge control unit that controls a potential barrier level of the charge discharge unit to be lower than a potential barrier level of the transfer unit during a sequential readout period by the scanning circuit;
The transfer unit and the charge discharge unit are formed of MOS transistors, and the gate terminal related to the transfer unit and the gate terminal related to the charge discharge unit are symmetrical to each other with respect to the approximate center of the photoelectric conversion unit. solid-state image sensor characterized in that it is arranged.

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