JPH09252145A - Semiconductor light emitting device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the number of parts and the number of processes at the time of mounting a light emitting element on a board, and reduce the manufacturing cost more. SOLUTION: This light emitting device has a light emitting element array 41 where at least one stack structure 51 including a light emitting layer is made on a semiconductor substrate, and a mounting board 42, and the light emitting array chip 41 is made on the mounting board 42. In this case, the main face including the stack structure 51 of the light emitting array chip 41 is a semiconductor in high carrier concentration to serve as a current injection part, and also at the mounting board 42, a junction pad 53 is made in the specified position, and the junction pad of the mounting board 42 and the semiconductor to serve as the current injection part of the light emitting element array chip 41 are connected by a bump metal 52 disposed therebetween.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor light emitting device used for optical communication, optical writing and the like.

[0002]

2. Description of the Related Art An array chip in which a plurality of light emitting elements or light receiving elements are arranged side by side on the same semiconductor substrate in an array form is a parallel optical transmission module in which a plurality of light emitting elements or light receiving elements and a plurality of optical fibers are integrated. It is used for optical writing printer heads.

By the way, in order to electrically connect such an array chip and a driver IC for driving the array chip (driving a light emitting element or the like), a wire bonding method is used with the main surface of the array chip facing upward. The method of connecting by wire is adopted. In this case, since the wire bonding method connects the wires by mechanically applying a force, it is not preferable in terms of manufacturing yield to directly connect the wires to the light emitting element or the like made of a mechanically weak semiconductor material, in terms of reliability, Therefore, the bonding pad is usually provided separately.

However, when the bonding pad is separately provided on the chip, it is necessary to increase the size of the chip accordingly, which reduces the number of chips taken from the wafer, which is not preferable in terms of manufacturing cost. Also, like an optical writing printer head, 400 DPI, 60
In a high-density light-emitting element array chip such as 0DPI, an extremely large number of wires must be connected in high density, and since the wire interval is narrow, problems such as shorts and opens are likely to occur, resulting in poor manufacturing yield. was there.

In order to solve such a problem, a face-down mounting method (for example, a light-emitting element array chip is a surface mounting method (face) is disclosed in, for example, JP-A-5-229174 and JP-A-5-18839. The method of mounting by down bonding) is proposed. FIG. 9, FIG. 10 and FIG. 11 are views showing an example of an LED print head in which LED elements are mounted by a face-down mounting method (Japanese Patent Laid-Open No. 5-229174). 9 is a sectional view of the LED print head, and FIG. 10 is the LED of FIG.
FIG. 11 is a sectional view of the LED element (light emitting element array chip) of the print head, and FIG. 11 is a plan view seen from the electrode surface of the LED element (light emitting element array chip) of FIG.

Referring to FIG. 9, in the example of this LED print head, a driver IC 22 is mounted on a substrate 21, and an LED element 23 is mounted thereon. Here, the driver IC 22 and the substrate 21 are connected to the wire 24.
The driver IC 22 is connected to the substrate 21
Signals and power are supplied from the side through the wire 24. In addition, the LED element 23 and the driver IC
22 are connected by the LED element 23 or the bump 34 provided on the driver IC 22.
3 is driven by a signal or power supplied from the driver IC 22 via the bump 34. Thus, in this LED printhead example,
Without connecting the LED element 23 and the driver IC 22 with a wire, the LED element 23 is connected to the driver IC.
It is mounted directly on 22 and these are directly connected by bump metal 34 and 36.

More specifically, in the example of FIG.
Referring to FIGS. 10 and 11, No. 3 is an LED in which a p-type impurity is diffused into an n-type wafer to form a pn junction and an LED is formed. That is, Zn, which is a p-type impurity, is selectively diffused into the n layer 31 to form the p layer 32.
A pn junction between the layer 31 and the p layer 32 is formed. In this case, since the light is emitted in the same direction at the pn junction, the light emitted in the arrow direction is used here as the output of the LED print head. That is, light is extracted laterally from the LED element 23.

In the LED element 23, the p-side individual electrode 33 is provided on the p-layer 32 in which p-type impurities are diffused, the p-side bump 34 is formed thereon, and the n-type portion also has the n-side. An electrode 35 is provided, and an n-side bump 36 is formed on it. Here, as the bumps 34 and 36, PbSn or A
uSn is used. As shown in FIG. 11, one p-side bump 34 is formed in one light emitting portion, and each n-side bump 36 is formed to the extent that the current value flowing through each pn junction does not vary.

As described above, in this example of the LED print head, the LED element 23 is directly mounted on the driver IC 22 without connecting the LED element 23 and the driver IC 22 with a wire, and these are mounted on the bump metal 3
Since they are directly connected by 4, 36, it is not necessary to form a pad for wire bonding, and therefore the chip can be made smaller, the number of chips taken from the wafer can be increased, and the manufacturing cost can be reduced. Furthermore, shorts and opens of wires are eliminated, and the manufacturing yield can be improved.

[0010]

However, in the above-described conventional semiconductor light emitting device, it is necessary to separately form the p-side individual electrode 33 and the n-side electrode 35 on the light emitting element array chip, and the mounting substrate is mounted. A bonding pad made of a metal is formed on each of the bumps 34, 36.
Are formed between the p-side individual electrode or the n-side electrode and the bonding pad, respectively, so that the number of components does not change from the case of mounting by wire bonding, and the number of steps for forming a light emitting element array chip does not change. Although the number of chips taken from the wafer can be improved by making the chips smaller, the reduction in manufacturing cost was still insufficient.

It is an object of the present invention to provide a semiconductor light emitting device capable of reducing the number of parts and the number of steps when mounting a light emitting element on a substrate and further reducing the manufacturing cost.

[0012]

In order to solve the above problems, according to the invention of claim 1, a light emitting element array chip having at least one laminated structure including a light emitting layer formed on a semiconductor substrate, and a mounting substrate. In the semiconductor light emitting device in which the light emitting element array chip is mounted on a mounting substrate, the main surface including the laminated structure of the light emitting element array chip is a semiconductor with a high carrier concentration that serves as a current injection portion. In addition, a bonding pad is formed at a predetermined position on the mounting substrate, and the bonding pad of the mounting substrate and the semiconductor part serving as the current injection part of the light emitting element array chip are between the two. Connected by placed bump metal,
The semiconductor part which will be the current injection part of the light emitting element array chip and the bump metal are directly connected to each other, and the ohmic electrode is formed in the wafer process (chip separation step) in the current injection part on the main surface of the light emitting element array chip. Is not formed separately (i.e., it is not necessary to form at least one of the p-side ohmic electrode and the n-side ohmic electrode). This can reduce the number of parts and the number of steps when mounting the light emitting element on the mounting substrate, and further reduce the manufacturing cost.

Further, according to the invention described in claim 2, according to claim 1,
In the semiconductor light emitting device described above, the current injection unit is p
Side and n-side current injection portions, both the p-side and n-side current injection portions are on the main surface of the light-emitting element array chip, and the bump metal made of the same material for both the p-side and the n-side is an ohmic electrode. Doubles as As a result, the p-side ohmic electrode, n, and n are formed on the light emitting device array chip during the wafer process.
It is not necessary to form each of the side ohmic electrodes individually, and further, the formation and mounting of the ohmic contacts on the p side and the n side can be performed in one step, further reducing the number of parts and the number of steps, and reducing the manufacturing cost. It can be further reduced.

According to the invention described in claim 3, claim 1
Alternatively, in the semiconductor light emitting device according to claim 2, an insulating dielectric film is formed on the main surface of the light emitting element array chip except for the current injection portion. Thereby, the bump metal can be prevented from spreading and a short circuit between adjacent elements can be prevented. Further, with such a structure, the self-alignment effect due to the surface tension can be provided even without the electrode metal, so that the light emitting element array chip and the mounting substrate can be aligned with high accuracy.

According to the invention of claim 4, the invention according to claim 1
In the semiconductor light emitting device according to any one of claims 3 to 3, the bump metal is formed of a material whose main component is In. As a result, even if the p-side ohmic electrode and the n-side ohmic electrode are not individually formed during the wafer process,
An ohmic contact can be easily formed with the semiconductor portion.

According to a fifth aspect of the present invention, in the semiconductor light emitting device according to the first to third aspects, the carrier concentration of the semiconductor portion serving as the current injection portion of the light emitting element array chip is 1 × 10 ¹⁸ cm ^−3. That is all. As a result, an ohmic contact with a low contact resistance can be easily formed.

According to the invention described in claim 6,
In the semiconductor light emitting device described above, the laminated structure includes a first laminated structure that functions as a light emitting element and a second laminated structure that functions as a dummy element, and the second laminated structure is It has the same structure as the first laminated structure and is formed at a symmetrical position on the substrate with respect to the first laminated structure. As a result, the chip may be turned upside down and the second laminated structure that functions as a dummy element may be used as a light emitting element, which facilitates mounting.
In addition, even if there is a defect in the first stacked structure that functions as a light-emitting element, if there is no defect in the second stacked structure that functions as a dummy element, the second stacked structure is used instead of the first stacked structure.
Can be used as a light emitting element, and the yield as a light emitting element array chip can be improved.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. 1 and 2 are diagrams showing a first configuration example of a semiconductor light emitting device according to the present invention. 1 is a cross-sectional view of the semiconductor light emitting device, and FIG. 2 is a plan view seen from the electrode surface of the light emitting element array chip.

Referring to FIGS. 1 and 2, this semiconductor light emitting device is constructed by mounting a light emitting element array chip 41 face down on a mounting substrate 42. Here, the light emitting element array chip 41 is formed on the n-type GaAs substrate (semiconductor substrate) 43 at equal intervals in the array direction R.
(For example, the light emitting diodes) 51 are arranged in a line (in an array), and similarly, the dummy elements 60 are arranged in a line (in an array) at symmetrical positions on the chip in the array direction R. Has become.

As shown in FIG. 1, each light-emitting element 51 has an n-type GaAs buffer layer 44 and an n-type Al layer formed by MOCVD on an n-type GaAs substrate 43 having a carrier concentration of 1 × 10 ¹⁸ cm ^-3. _0.4 Ga _0.6 As clad layer 45, n-type GaAs active layer 46 which is a light emitting layer, p-type Al _0.4 Ga _0.6
As clad layer 47, and carrier concentration is 1 × 10
^The p-type GaAs cap layer 48 having a thickness of ¹⁹ cm ⁻³ is formed as a laminated structure in which a plurality of layers are sequentially laminated, and the light is extracted in the lateral direction as an edge emitting light emitting diode.

Each dummy element 60 is also a light emitting element 51.
Exactly the same laminated structure (carrier concentration is 1 × 10 ¹⁸ cm
^-3 , the n-type GaAs substrate 43, and the n-type GaAs buffer layer 44 and the n-type Al _0.4 Ga _0.6 by the MOCVD method.
As clad layer 45, n-type GaAs active layer 46 as a light emitting layer, p-type Al _0.4 Ga _0.6 As clad layer 47, and p-type GaA having a carrier concentration of 1 × 10 ¹⁹ cm ^−3.
A plurality of layers of the s cap layer 48 are sequentially laminated to have a laminated structure).

In this light emitting element array chip 41,
Separation grooves 50, 61 are provided between the light emitting elements 51, between the dummy elements 60, and between the light emitting elements 51 and the dummy elements 60.
71 are separated from each other. The separation groove 5
0, 61 and 71 are formed by partially etching the laminated structure from the surface of the laminated structure, that is, the upper surface of the cap layer 48 to the GaAs substrate 43, by a dry etching method using a chlorine-based gas. This separation groove 50, 61
Thus, the light emitting elements 51 and the dummy elements 60 are electrically and spatially separated on the light emitting element array chip 41.

The light emitting facet 51a of each light emitting element (edge emitting type light emitting diode) 51 has the same depth as the separation grooves 50, 61 and is perpendicular to the face 43a of the n-type GaAs substrate 43 and in the array direction R. Is formed in parallel with. Then, on the back surface of the n-type GaAs substrate 43, an n-side ohmic electrode 57 that functions as an n-side current injection portion is formed.

On the other hand, the mounting substrate 42 is made of, for example, Al ₂ O ₃ , and corresponds to each laminated structure of the light emitting element array chip 41 (each light emitting element 51, each dummy element 60) on the mounting substrate 42. P-side bonding pads 53 are formed at the respective positions, and the n-side ohmic electrode 57 and the wire 58 of the light emitting element array chip are mounted on the mounting substrate 42.
An n-side bonding pad 59 connected by wire bonding is formed.

Then, the p-type GaAs of each laminated structure (each light emitting element 51, each dummy element 60) of the light emitting element array chip is formed.
The p-side bonding pad 53 on the cap layer 48 and the mounting substrate 42
Are directly connected by, for example, a bump metal 52 containing In as a main component. That is, the semiconductor portion (p-type GaAs cap layer 48) that serves as a current injection portion of the light emitting element array chip 41 and the bump metal 52 are directly joined at the time of mounting.

The semiconductor light emitting device having such a structure can be manufactured as follows. That is, first, the light emitting element array chip 41 is manufactured. In manufacturing the light emitting element array chip 41, the carrier concentration is 1 × 10 ^18.
The n-type GaAs buffer layer 44 and the n-type Al _0.4 G are formed on the n-type GaAs substrate 43 of cm ⁻³ by the MOCVD method.
a _0.6 As clad layer 45, n-type GaAs which is a light emitting layer
Active layer 46, p-type Al _0.4 Ga _0.6 As clad layer 47,
Then, p-type G having a carrier concentration of 1 × 10 ¹⁹ cm ⁻³
A plurality of layers of the aAs cap layer 48 are sequentially laminated to form a laminated structure. Then, from the top surface of the cap layer 48, G
The laminated structure is partially etched up to the aAs substrate 43 by a dry etching method using a chlorine-based gas to form isolation grooves 50, 61, 71, and each light emitting element 51 and dummy element 60 are formed. In addition, the light emitting end face 51a of each light emitting element (end face light emitting type light emitting diode) 51 is connected to the separation groove 5
Surface 43a of n-type GaAs substrate 43 at the same depth as 0, 61
To be perpendicular to and parallel to the array direction R. Then, an n-side ohmic electrode 57 is formed on the back surface of the n-type GaAs substrate 43.

Here, it should be noted that each current injection portion (in the above example, on the electrode surface (main surface) 62 of the light emitting element array chip (in the above example,
Each laminated structure 51, 60) has a p-type during the wafer process.
It is not necessary to separately form the side ohmic electrode (for example, a metal thin film for the p-side ohmic electrode). The wafer on which the light emitting element array chips 41 are formed is separated into the respective light emitting element array chips 41 by scribing or dicing.

Next, the light emitting element array chip 41 is mounted on the mounting substrate 42. In this mounting process, the current injection portion 55 on the p-type GaAs cap layer 48 of each laminated structure 51, 60 of the light emitting element array chip 41 and the p on the mounting substrate 42.
The side bonding pad 53 is directly bonded by the bump metal 52. That is, each laminated structure 51, 60 of the light emitting element array chip 41 and each p-side bonding pad 53 of the mounting substrate 42.
Are positioned at corresponding positions, bump metal (for example, metal containing In as a main component) 52 is inserted between them, and then heat treatment at about 400 ° C. is performed.
These are joined by the bump metal 52.

In addition, In is generally used as an electrode of a Hall measurement sample of a semiconductor thin film, and is a material capable of obtaining ohmic contact regardless of p-type or n-type.
Therefore, by using a metal whose main component is In for the bump metal 52, the ohmic contact is formed between the current injection portion 55 of each of the laminated structures 51 and 60 and the p-side bonding pad 53 on the mounting substrate 42. You can In other words,
In the semiconductor light emitting device of the first configuration example, the bump metal 52 also serves as the p-side ohmic electrode without separately forming the p-side ohmic electrode during the wafer process.

Further, the n-side ohmic electrode 57 and the n-side bonding pad 59 are connected by a wire 58 by wire bonding. In this way, the light emitting element array chip 41 is mounted on the mounting substrate 42, and the semiconductor light emitting device of FIGS. 1 and 2 can be manufactured.

As described above, in the semiconductor light emitting device of the first configuration example, on the light emitting element array chip 41 (that is, on the p-type GaAs cap layer 48 of each laminated structure 51, 60).
In addition, it is not necessary to previously form a p-side ohmic electrode (for example, a metal thin film for the p-side ohmic electrode) for making the p-side ohmic contact, and even if the p-side ohmic electrode is not formed in advance, mounting is possible. Sometimes, on the individual side (p side in this example) due to the bump metal 52 that also serves as the ohmic electrode.
Therefore, the number of parts and the number of manufacturing steps can be reduced, and the manufacturing cost can be reduced, as compared with the conventional semiconductor light emitting device shown in FIG. In this case, in order to obtain a low contact resistance,
The carrier concentration of the p-type GaAs cap layer 48 is 1 × 10.
It is desirable that the concentration is as high as ¹⁸ cm ^-3 or more.

Further, in this first configuration example, the light emitting element 5
Since the dummy element 60 having the same structure as that of 1 is formed at a symmetrical position on the chip 41, the chip 41 may be turned upside down (on the plane of the drawing) to use the dummy element 60 as a light emitting element. Therefore, the mounting can be made easier.
In addition, even if there is a defective bit on the light emitting element 51 side,
If there is no defective bit on the dummy element 60 side, the dummy element 60 can be used instead of the light emitting element 51, and in this case, the yield of the light emitting element array chip can be improved. Further, in the above configuration example,
Although the dummy element 60 has the same laminated structure as the light emitting element 51, the dummy element 60 may have a structure as a light receiving element. In this case, since the light output of the light emitting element can be individually monitored by the light receiving element corresponding thereto, it is possible to reduce the variation in the light output between the light emitting elements and the change over time.

In other words, in this first configuration example,
In a broader sense, the laminated structure 51 can be regarded as the first laminated structure, and the laminated structure 60 can be regarded as the second laminated structure.

FIGS. 3 and 4 are views showing a second configuration example of the semiconductor light emitting device according to the present invention. 3 is a sectional view of the semiconductor light emitting device, and FIG. 4 is a plan view seen from the electrode surface of the light emitting element array chip.

In the second configuration example, similarly to the first configuration example, each current injection portion (each laminated structure 51, 60) of the light emitting element array chip 41 is provided with a p-side ohmic electrode during the wafer process. No metal thin film is formed, but second
In the configuration example described above, the insulating dielectric film (eg, SiO ₂ ) 54 is formed on the semiconductor substrate 43 including the laminated structures 51 and 60 that are electrically and spatially separated into an array, and the current injection portion is formed. The (upper surface of each laminated structure 51, 60) is different from the first configuration example in that a part of the insulating dielectric film 54 is selectively removed.

That is, in this second configuration example, in the step of joining the light emitting element array chip 41 and the joining pad 53 of the mounting substrate 42, a part of the insulating dielectric film 54 on the light emitting element array chip 41 is partially removed. In the removed portion, the current injection portion 55 on the p-type GaAs cap layer 48 of the light emitting element array chip 41 has the bump metal 5 containing In as a main component.
2 on which the bonding pad 53 is formed, for example, Al ₂ O ₃
It is directly bonded to the mounting board 42 made of aluminum.

Also in this second configuration example, the semiconductor portion which is the current injection portion of the light emitting element array chip 41 and the bump metal 52 are directly connected at the time of mounting. Specifically,
Similar to the first configuration example, each bonding pad 53 is formed at a position corresponding to each p-side current injection portion 55 of the light emitting element array chip 41, and each laminated structure 51, 60 of the light emitting element array chip 41. And each p-side bonding pad 5 of the mounting substrate 42
3 and 3 are positioned at corresponding positions, a bump metal (for example, a metal containing In as a main component) 52 is inserted between them, and then heat treatment is performed at about 400 ° C. Join by. That is, the heat treatment causes ohmic contact with the p-side current injection portion 55, and therefore, it is not necessary to separately form a metal thin film for making the p-side ohmic contact on the p-type GaAs cap layer 48 in advance. Also, at the time of mounting, a p-type ohmic contact can be obtained by one type of mounting bump metal 52, and the manufacturing cost can be significantly reduced. In this case, similarly to the first configuration example, in order to obtain a low contact resistance, the p-type GaAs cap layer 48 is also used.
The carrier concentration is preferably 1 × 10 ¹⁸ cm ⁻³ or higher.

Further, in the second configuration example, since the insulating dielectric film 54 is formed on the light emitting element array chip 41 except for the above-mentioned joining portion, the insulating dielectric film 54 is used. It is possible to prevent the bump metal 52 from spreading and prevent a short circuit between adjacent elements. Further, when the insulating dielectric film 54 has a structure in which a part is selectively removed and has a cut portion, the bump metal 52 also has a self-alignment effect due to the surface tension. Accordingly, the bonding pad 53 of the mounting substrate 42 and the current injection portion 55 of the light emitting element array chip 41 are formed.
Since the light emitting element array chip 41 is moved so that the centers of the light emitting element array and the light emitting element array chip are aligned with each other, the alignment can be performed with high accuracy. FIG.
The same effect can be obtained in the conventional light emitting element array chip shown in FIG. 0, but this is the same as the p side individual electrode 33 and the n side electrode 35.
Exists in a size slightly larger than the bump metal, and exists individually. That is, in the second configuration example, the insulating dielectric film 54 has a structure in which a part is selectively removed and has a cut portion, so that the self-alignment effect can be provided without the electrode metal. it can.

FIGS. 5 and 6 are views showing a third configuration example of the semiconductor light emitting device according to the present invention. 5 is a sectional view of the semiconductor light emitting device, and FIG. 6 is a plan view seen from the electrode surface of the light emitting element array chip.

Referring to FIGS. 5 and 6, this semiconductor light emitting device is constructed by mounting a light emitting element array chip 41 face down on a mounting substrate 42. Here, the light emitting element array chip 41 is formed on the n-type GaAs substrate (semiconductor substrate) 43 at equal intervals in the array direction R.
(For example, light emitting diodes) 51 are arranged in a line (in an array). 5 and 6, each light emitting element 51 is configured as an end face light emitting type light emitting diode whose light extraction direction is the lateral direction.

Each light emitting element 51 has a carrier concentration of 1 ×, as shown in FIG. 3 (similar to the light emitting element 51 in FIG. 1).
On the n-type GaAs substrate 43 of 10 ¹⁸ cm ^-3 , MOC
N-type GaAs buffer layer 44, n-type Al by VD method
_0.4 Ga _0.6 As clad layer 45, n-type Ga that is a light emitting layer
As active layer 46, p-type Al _0.4 Ga _0.6 As clad layer 4
7 and p with carrier concentration of 1 × 10 ¹⁹ cm ⁻³
The GaAs cap layer 48 has a laminated structure in which a plurality of layers are sequentially laminated.

In this light emitting element array chip 41,
The light emitting elements 51 are separated from each other by a separation groove 50. The separation groove 50 is formed from the surface of the above-mentioned laminated structure, that is, the upper surface of the cap layer 48 to the GaAs substrate 43.
Up to this point, the laminated structure is partially etched by a dry etching method using a chlorine-based gas. Each light emitting element 51 is electrically and spatially separated on the light emitting element array chip 41 by the separation groove 50.

The light emitting end face 51a of each light emitting element (edge emitting light emitting diode) 51 has the same depth as the separation groove 50 and is perpendicular to the face 43a of the n-type GaAs substrate 43 and parallel to the array direction R. Is formed in.

By the way, in the third configuration example, n-type G
No n-side ohmic electrode functioning as an n-side current injection portion is formed on the back surface of the aAs substrate 43, and the n-side current injection portion 56 is provided on the main surface 62 of the n-type GaAs substrate 43 (that is, the laminated structure 51). (on the surface of the substrate 43 on the same side where the p-side current injection portion 55) is formed).

On the other hand, the mounting substrate 42 is formed of, for example, Al ₂ O ₃ , and on the mounting substrate 42, each laminated structure 51 (each p-side current injection part) on the main surface 62 of the light emitting element array chip 41 is formed. 55) and the n-side current injection portions 56, p-side and n-side bonding pads 53 are formed respectively. The bonding pad 53 can be similarly formed of the same material on both the p-side and the n-side.

Then, the current injection portion 55 (p-type GaAs cap layer 48) of each laminated structure (each light emitting element 51) of the light emitting element array chip and the p-side bonding pad 53 on the mounting substrate 42.
Are directly connected by, for example, a bump metal 52 containing In as a main component. Furthermore, in the third configuration example, each n-side current injection section 56 of the light emitting element array chip is also
For example, the bump metal 52 containing In as a main component is directly connected to the n-side bonding pad 53 on the mounting substrate 42. That is, in the third configuration example, the semiconductor portion (the p-type GaAs cap layer 58 of the integrated structure 51) which will be the p-side current injection portion 55 of the light emitting element array chip 41 and the bump metal 52 are directly bonded at the time of mounting. In addition to the above, the semiconductor portion (the main surface 62 of the n-type GaAs substrate 43) which becomes the n-side current injection portion 56 of the light emitting element array chip 41 is also directly joined to the bump metal 52 at the time of mounting.

The semiconductor light emitting device having such a structure can be manufactured as follows. That is, first, the light emitting element array chip 41 is manufactured. In manufacturing the light emitting element array chip 41, the carrier concentration is 1 × 10 ^18.
The n-type GaAs buffer layer 44 and the n-type Al _0.4 G are formed on the n-type GaAs substrate 43 of cm ⁻³ by the MOCVD method.
a _0.6 As clad layer 45, n-type GaAs which is a light emitting layer
Active layer 46, p-type Al _0.4 Ga _0.6 As clad layer 47,
Then, p-type G having a carrier concentration of 1 × 10 ¹⁹ cm ⁻³
A plurality of layers of the aAs cap layer 48 are sequentially laminated to form a laminated structure. Then, from the top surface of the cap layer 48, G
The laminated structure is partially etched up to the aAs substrate 43 by a dry etching method using a chlorine-based gas to form a separation groove 50, and each light emitting element 51 is formed. Further, the light emitting end face 5 of each light emitting element (end face light emitting type light emitting diode) 51
1a is an n-type GaAs substrate 43 having the same depth as the separation groove 50.
Is formed perpendicular to the surface 43a of the above and parallel to the array direction R.

Here, it should be noted that a p-side ohmic electrode (a metal thin film for the p-side ohmic electrode) is formed in each current injection portion of the electrode surface (main surface) 62 of the light emitting element array chip during the wafer process. Not done. In addition, n-type GaAs
On the back surface of the substrate 43, the n-side ohmic electrode (metal thin film for the n-side ohmic electrode) is not formed during the wafer process. The wafer on which the light emitting element array chips 41 are formed is separated into the respective light emitting element array chips 41 by scribing or dicing.

Next, the light emitting element array chip 41 is mounted on the mounting substrate 42. In this mounting step, the p-type GaAs cap layer 4 of each laminated structure of the light emitting element array chip 41 is formed.
8 and the p-side bonding pad 53 on the mounting substrate 42 are directly bonded by the bump metal 52, and the n-type GaAs substrate 4 of the light emitting element array chip 41 is connected.
3 and the n-side bonding pad 53 on the mounting substrate 42 are directly bonded by the bump metal 52. That is, each p-side current injection part 5 of the light emitting element array chip 41.
5, each n-side current injection portion 56 and each bonding pad 53 of the mounting substrate 42 are positioned at corresponding positions, and bump metal (for example, a metal containing In as a main component) 5 is interposed between them.
2 is inserted, and then heat treatment at about 400 ° C. is performed to bond them by the bump metal 52.

As described above, In is the Ha of the semiconductor thin film.
It is generally used as an electrode of the sample for measuring
It is a material that can obtain ohmic contact regardless of type or n-type. Therefore, by using a metal containing In as a main component for the bump metal 52, it is possible to form an ohmic contact between each p-side current injection portion 55 and the p-side bonding pad 53 on the mounting substrate 42. The bonding between each n-side current injection portion 56 and the n-side bonding pad 53 on the mounting substrate 42 can also be ohmic contact.

In other words, in the semiconductor light emitting device of the third configuration example, the p side and the n side of the light emitting element array chip 41 are
The semiconductor portion to be the current injection portions 55 and 56 on the side and the bump metal 52 are directly bonded at the time of mounting, and the bump metal 5
2 also serves as both p-side and n-side ohmic electrodes.

As described above, in the semiconductor light emitting device of the third configuration example, on the light emitting element array chip 41 (that is, on the p-type GaAs cap layer 48 of each laminated structure 51, and
on the n-type GaAs substrate 43), p-side ohmic electrode, n
Even if the side ohmic electrode is not separately formed in advance,
Since one kind of bump metal 52 can simultaneously provide ohmic contacts on both the p-side and the n-side during mounting, the number of components and the number of manufacturing steps can be further reduced, and the manufacturing cost can be significantly reduced. In this case, in order to obtain a low contact resistance, it is desirable that the carrier concentration of the p-type GaAs cap layer 48 and the carrier concentration of the n-type GaAs substrate 43 are high concentrations of 1 × 10 ¹⁸ cm ⁻³ or more. .

FIG. 7 and FIG. 8 are views showing a fourth structural example of the semiconductor light emitting device according to the present invention. 7 is a sectional view of the semiconductor light emitting device, and FIG. 8 is a plan view seen from the electrode surface of the light emitting element array chip.

The fourth configuration example corresponds to the third configuration example, and like the third configuration example,
In the light emitting element array chip, the metal thin film for the ohmic electrode is not formed on either the p-side or the n-side current injection portion. However, in the fourth configuration example, it is electrically and spatially separated into an array. Semiconductor substrate 43 including integrated structure 51 formed by
An insulating dielectric film (for example, SiO ₂ ) 54 is formed on the upper portion of the current injection portion (p side 55, n side 56), and a portion of the insulating dielectric film 54 is selectively removed. Is different from the third configuration example.

That is, in the fourth configuration example, in the step of joining the light emitting element array chip 41 and the joining pad 53 of the mounting substrate 42, a part of the insulating dielectric film 54 on the light emitting element array chip 41 is partially removed. In the removed portion, on the p side of the light emitting element array chip 41, the current injection portion 55 on the p-type GaAs cap layer 48 is formed by the bump metal 52 containing In as a main component and the bonding pad 53 is formed, for example, Al. It is directly bonded onto the mounting substrate 42 made of ₂ O ₃ . The n side is the current injection part 56 on the n-type GaAs substrate 43.
However, the mounting substrate 42 made of, for example, Al ₂ O ₃ on which the bonding pad 53 is formed by the bump metal 52 containing In as a main component.
It is directly bonded on top.

Also in this fourth configuration example, the semiconductor portion which is the current injection portion of the light emitting element array chip 41 and the bump metal 52 are directly connected at the time of mounting. Specifically,
Similar to the third configuration example, each bonding pad 53 is connected to each of the p-side and n-side current injection portions 55 of the light emitting element array chip 41.
The current injection portions 55, 56 of the light emitting element array chip 41 and the bonding pads 53 of the mounting substrate 42 are formed at the positions corresponding to 56, respectively, and are positioned at the corresponding positions, respectively, and bump metal is provided between them. (For example, a metal containing In as a main component) 52 is inserted, and then heat treatment at about 400 ° C. is performed to bond them by the bump metal 52. That is, by performing heat treatment,
Ohmic contact to both sides, thus
Even if a metal thin film for making a p-side ohmic contact and a metal thin film for making an n-side ohmic contact are not separately formed in advance on the light emitting element array chip 41, one kind of mounting bump metal is used at the time of mounting. By 52, ohmic contacts can be obtained on both sides of the n-side and the p-side, and the manufacturing cost can be significantly reduced. In this case, as in the third configuration example, in order to obtain a low contact resistance, the p-type GaAs cap layer 48 and the n-type GaAs substrate 4 are used.
It is desirable that the carrier concentration of 3 is a high concentration of 1 × 10 ¹⁸ cm ⁻³ or more.

Further, in the fourth configuration example, since the insulating dielectric film 54 is formed on the light emitting element array chip 41 except for the above-mentioned joining portion, the insulating dielectric film 54 is used. It is possible to prevent the bump metal 52 from spreading and prevent a short circuit between adjacent elements. Further, when the insulating dielectric film 54 has a structure in which a part is selectively removed and has a cut portion, the bump metal 52 also has a self-alignment effect due to the surface tension. Accordingly, the bonding pad 53 of the mounting substrate 42 and the current injection portion 5 of the light emitting element array chip 41 are
Since the light emitting element array chip 41 is moved so that the centers of 5, 56 coincide with each other, alignment can be performed with high accuracy. The conventional light emitting element array chip shown in FIG. 10 also has the same effect, but this is because the p-side individual electrode 33 and the n-side electrode 35 are individually slightly larger than the bump metal. That is, in the fourth configuration example, since the insulating dielectric film 54 has a structure in which a part is selectively removed and has a disconnection portion, a self-alignment effect can be provided without the electrode metal. it can.

In each of the above configuration examples, a material containing In as a main component is used as the bump metal, but the p-side, n
It is also possible to use another low melting point metal capable of simultaneously making ohmic contact. Also, ohmic contacts may be separately formed by using low melting point metals capable of forming ohmic contacts separately on the p-side and the n-side. of course,
The present invention can be applied to semiconductor materials other than GaAs, and p and n may have opposite conductivity types. Further, in each of the above configuration examples, only the LED array using the double heterojunction is described, but in addition to the double heterojunction, a homojunction or a single heterojunction may be used,
Further, the semiconductor light emitting device is not limited to the LED, but may be an LD or a PD.
Other optical elements such as the above may be used, and the same effect can be obtained with other optical elements.

[0059]

As described above, according to the first aspect of the present invention, there is provided a mounting substrate and a light emitting element array chip in which at least one laminated structure including a light emitting layer is formed on a semiconductor substrate. In the semiconductor light emitting device in which the light emitting element array chip is mounted on a mounting substrate, the main surface including the laminated structure of the light emitting element array chip is a semiconductor portion having a high carrier concentration that serves as a current injection portion. ,Also,
A bonding pad is formed at a predetermined position on the mounting substrate, and the bonding pad of the mounting substrate and the semiconductor portion serving as a current injection portion of the light emitting element array chip are formed by a bump metal placed between them. The semiconductor part which is connected and serves as a current injection part of the light emitting element array chip is directly connected to the bump metal, and an ohmic electrode is formed in the wafer process in the current injection part on the main surface of the light emitting element array chip.
When the light emitting element is mounted on the mounting substrate, since it is not formed individually (before the chip separation step) (that is, it is not necessary to form at least one of the p-side ohmic electrode and the n-side ohmic electrode). The number of parts and the number of steps can be reduced, and the manufacturing cost can be further reduced.

According to a second aspect of the present invention, in the semiconductor light emitting device according to the first aspect, the current injection section has p-side and n-side current injection sections.
Both of the current injection parts on the side are on the main surface of the light emitting element array chip, and since the bump metal of the same material also serves as the ohmic electrode on the p side and the n side, the p side on the light emitting element array chip is formed during the wafer process. It is not necessary to separately form both the side ohmic electrode and the n-side ohmic electrode, and the formation and mounting of the ohmic contacts on the p-side and the n-side can be performed in one step, further reducing the number of parts and the number of steps. However, the manufacturing cost can be further reduced.

According to the invention described in claim 3, in the semiconductor light emitting device according to claim 1 or 2,
Since an insulating dielectric film is formed on the main surface of the light emitting device array chip except for the current injection part, it is possible to prevent the bump metal from spreading and to prevent a short circuit between adjacent devices. Can be prevented. Further, with such a structure, the self-alignment effect due to the surface tension can be provided even without the electrode metal, so that the light emitting element array chip and the mounting substrate can be aligned with high accuracy.

According to a fourth aspect of the invention, in the semiconductor light emitting device according to any one of the first to third aspects, the bump metal is formed of a material whose main component is In. Therefore, it is possible to easily form an ohmic contact with the semiconductor portion without separately forming the p-side ohmic electrode and the n-side ohmic electrode during the wafer process.

According to the invention of claim 5, claim 1
Further, in the semiconductor light emitting device according to claim 3, since the carrier concentration of the semiconductor portion which becomes the current injection portion of the light emitting element array chip is 1 × 10 ¹⁸ cm ⁻³ or more, an ohmic contact having a small contact resistance can be easily formed. it can.

According to the invention of claim 6, in the semiconductor light emitting device of claim 1, the laminated structure is
It is composed of a first laminated structure that functions as a light emitting element and a second laminated structure that functions as a dummy element, and the second laminated structure has the same structure as the first laminated structure. However, since the chips are formed at symmetrical positions on the substrate with respect to the first laminated structure, the chip may be turned upside down and the second laminated structure functioning as a dummy element may be used as a light emitting element. , Easy to implement. Further, even if there is a defect in the first stacked structure that functions as a light emitting element, if there is no defect in the second stacked structure that functions as a dummy element, the second stacked structure is replaced by the second stacked structure instead of the first stacked structure. It can be used as a light emitting element, and the yield as a light emitting element array chip can be improved.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor light emitting device of a first configuration example according to the present invention.

FIG. 2 is a plan view of a semiconductor light emitting device having a first configuration example according to the present invention.

FIG. 3 is a sectional view of a semiconductor light emitting device of a second configuration example according to the present invention.

FIG. 4 is a plan view of a semiconductor light emitting device having a second configuration example according to the present invention.

FIG. 5 is a sectional view of a semiconductor light emitting device of a third configuration example according to the present invention.

FIG. 6 is a plan view of a semiconductor light emitting device having a third configuration example according to the present invention.

FIG. 7 is a sectional view of a semiconductor light emitting device of a fourth configuration example according to the present invention.

FIG. 8 is a plan view of a semiconductor light emitting device having a fourth configuration example according to the present invention.

FIG. 9 is a diagram showing a configuration example of a conventional print head to which face-down mounting is applied.

10 is a cross-sectional view of a light emitting element array chip of the print head of FIG.

FIG. 11 is a plan view of the light emitting device array chip of FIG. 10 viewed from the electrode surface.

[Explanation of symbols]

41 light emitting element array chip 42 mounting substrate 43 n-type GaAs substrate 44 n-type GaAs buffer layer 45 n-type Al _0.4 G
a _0.6 As clad layer 46 n-type GaAs active layer 47 p-type Al _0.4 G
a _0.6 As clad layer 48 p-type GaAs cap layer 51 light emitting element 60 dummy element 50, 61, 71 isolation groove 51a light emitting end face 52 bump metal 53 p-side bonding pad 54 insulating dielectric film 55, 56 current injection portion 57 n Side ohmic electrode 58 wire 59 n-side bonding pad 62 electrode surface (main surface) of light emitting element array chip

Claims (6)

[Claims] 1. A semiconductor light emitting device comprising: a light emitting element array chip having at least one laminated structure including a light emitting layer formed on a semiconductor substrate; and a mounting substrate, wherein the light emitting element array chip is mounted on the mounting substrate. In the device, the main surface of the light emitting element array chip including the laminated structure is a semiconductor portion having a high carrier concentration which serves as a current injection portion,
A bonding pad is formed at a predetermined position on the mounting substrate, and the bonding pad of the mounting substrate and the semiconductor portion serving as a current injection portion of the light emitting element array chip are formed by a bump metal placed between them. A semiconductor light emitting device, wherein a semiconductor portion which is connected and serves as a current injection portion of a light emitting element array chip and a bump metal are directly connected. 2. The semiconductor light emitting device according to claim 1, wherein the current injection section has p-side and n-side current injection sections, and both the p-side and n-side current injection sections are light emitting element arrays. A semiconductor light emitting device characterized in that a bump metal, which is on the main surface of a chip and is made of the same material on both the p side and the n side, also serves as an ohmic electrode. 3. The semiconductor light emitting device according to claim 1, wherein an insulating dielectric film is formed on the main surface of the light emitting element array chip except for a current injection portion. A semiconductor light emitting device characterized by the above. 4. The semiconductor light emitting device according to claim 1, wherein the bump metal is formed of a material whose main component is In. 5. The semiconductor light emitting device according to claim 1, wherein a carrier concentration of a semiconductor portion which is a current injection portion of the light emitting element array chip is 1 × 10 ¹⁸ cm ⁻³ or more. Semiconductor light emitting device. 6. The semiconductor light emitting device according to claim 1, wherein the laminated structure includes a first laminated structure that functions as a light emitting element and a second laminated structure that functions as a dummy element. Is the same structure as the first laminated structure, and is formed at a symmetrical position on the substrate with respect to the first laminated structure. .