JP3974676B2 - Manufacturing method of semiconductor light emitting device - Google Patents

Manufacturing method of semiconductor light emitting device Download PDF

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Publication number
JP3974676B2
JP3974676B2 JP1122697A JP1122697A JP3974676B2 JP 3974676 B2 JP3974676 B2 JP 3974676B2 JP 1122697 A JP1122697 A JP 1122697A JP 1122697 A JP1122697 A JP 1122697A JP 3974676 B2 JP3974676 B2 JP 3974676B2
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semiconductor
light emitting
electrodes
layer
wire bonding
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JPH10209497A (en
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毅 筒井
俊次 中田
幸男 尺田
雅之 園部
範和 伊藤
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Rohm Co Ltd
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Rohm Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched

Description

【０００１】
【発明の属する技術分野】
本発明は基板上に半導体層が積層され、積層された半導体層の表面側にｐ側およびｎ側の両電極が形成される半導体発光素子の製法に関する。さらに詳しくは、両電極（パッド）にワイヤボンディングをする場合に、自動機で行っても間違いなく容易に行うことができるように電極が設けられた半導体発光素子の製法に関する。
【０００２】
【従来の技術】
たとえば青色系の半導体発光素子は、図３にその発光素子チップ（以下、ＬＥＤチップという）の一例の概略図が示されるように、サファイアからなる絶縁性の基板２１上にチッ化ガリウム系化合物半導体層が積層されて、その表面側にｐ側電極２８およびｎ側電極２９の両方が設けられることにより形成されている。すなわち、ウェハ状のサファイア基板２１上にたとえばｎ形のＧａＮがエピタキシャル成長されたｎ形層（クラッド層）２３と、バンドギャップエネルギーがクラッド層のそれよりも小さくなる材料、たとえばＩｎＧａＮ系（ＩｎとＧａの比率が種々変わり得ることを意味する、以下同じ）化合物半導体からなる活性層２４と、ｐ形のＧａＮからなるｐ形層（クラッド層）２５とが積層され、その表面のｐ形層２５に電気的に接続してｐ側電極２８が、積層された半導体層の一部がエッチングされて露出するｎ形層２３と電気的に接続してｎ側電極２９が設けられることにより、ＬＥＤチップが形成されている。この構造で、両電極間に電圧が印加されるとｐ側電極２８からｎ側電極２９に向かって電流が流れ、その電流が活性層２４を流れるときに発光する。そのため、できるだけ広い範囲に亘って電流が流れるように、両電極（パッド）２８、２９は図３に示されるように、４角形状のＬＥＤチップの一番離れた位置、すなわち４角形状の対角線方向の両端に設けられている。
【０００３】
このＬＥＤチップ３０がガラスエポキシなどからなる回路基板３１上にダイボンディングされて、図４に示されるように、ｐ側電極２８およびｎ側電極２９が回路基板３１の配線３２にそれぞれ金線３３などによりワイヤボンディングされることにより回路中に組み込まれる。このワイヤボンディングは、ＬＥＤチップ３０の両電極２８、２９の位置のｘ座標を自動機に入力し、そのときの回路基板３１の配線３２のｙ座標を同時に入力して自動的にボンディングが行われる。
【０００４】
【発明が解決しようとする課題】
前述のように、ＬＥＤチップに設けられる２つの電極が、対角線方向に沿って設けられていると、そのＬＥＤチップが回路基板などにボンディングされるとき、回路基板の配線とＬＥＤチップの１辺が平行（または直角）になるようにダイボンディングされるため、２つの電極はそのｘ座標およびｙ座標の両方共異なる。そのため、ワイヤボンディングをするときの座標入力が、ｘ座標２つに対してそれぞれにｙ座標を入力しなければならない。そのため、ｐ側電極とｎ側電極とで入力を間違えてボンディングミスをするという問題がある。さらに、１個のＬＥＤチップのワイヤボンディングをするのに、自動ワイヤボンディング機をｘ軸方向の２か所の場所に移動して停止し、その都度ｙ方向に移動してボンディングをしなければならない。その結果、自動機の能率が低下したり、歩留りが低下するという問題がある。
【０００５】
本発明は、このような問題を解決するためになされたもので、基板の同一面側に一対の電極（パッド）が設けられ、両電極（パッド）にワイヤボンディングを自動機により行う場合に、入力のデータが簡単で、かつ、自動機の動きの無駄をなくして効率よくボンディングをすることができる電極（パッド）の位置を有する半導体発光素子の製法を提供することを目的とする。
【０００６】
【課題を解決するための手段】
本発明による半導体発光素子の製法は、四角形状の基板と、該基板上に発光層を形成すべくチッ化ガリウム系化合物半導体が積層される半導体積層部と、該半導体積層部の表面に形成される電流拡散層と、該電流拡散層上に設けられ前記半導体積層部の表面側の第１導電形の半導体層に接続して設けられる第１の電極と、前記半導体積層部の一部がエッチングにより除去されて露出する第２導電形の半導体層に接続して設けられる第２の電極とから平面形状が四角形状の発光素子チップが形成され、前記第１および第２の電極がワイヤボンディング用電極としてワイヤボンディングをする幅を有し、平面形状で円形または四角形状に形成されると共に、前記発光素子チップの平面形状で、１つの１辺の端縁からほぼ同じ距離の位置で、かつ、前記１つの１辺の両端部である四角形状の２隅に前記第１および第２の電極がそれぞれ形成され、前記発光素子チップが、平行に２つの配線が形成された回路基板の該配線間に、前記発光素子チップの前記１つの１辺が前記配線と直交するようにマウントされ、前記第１および第２の電極が、それぞれ前記２つの配線の一方および他方とワイヤボンディングにより接続され、かつ、前記２つの配線の延びる方向をｘ軸として前記第１および第２の電極ならびに前記２つの配線にそれぞれワイヤボンディングされる位置が同じｘ座標になるようにボンディングされてなる半導体発光素子の製法であって、前記第１および第２の電極の前記ワイヤボンディングのために、ボンディング機をｘ軸方向に移動させることなくワイヤボンディングをすることを特徴としている。
【０００７】
ここにチッ化ガリウム系化合物半導体とは、III 族元素のＧａとＶ族元素のＮとの化合物またはIII 族元素のＧａの一部がＡｌ、Ｉｎなどの他のIII 族元素と置換したものおよび／またはＶ族元素のＮの一部がＰ、Ａｓなどの他のＶ族元素と置換した化合物からなる半導体をいう。また、第１導電形および第２導電形とは、半導体の極性のｎ形およびｐ形のいずれか一方を第１導電形としたとき、他方のｐ形またはｎ形が第２導電形であることを意味する。また、電極とは、ワイヤボンディングをし得るように厚く形成された電極部（電極パッド）を意味し、一方の電極が幅広く形成される場合は、その一部が他方の電極と共に前記一辺に沿って設けられているものを含む。
【０００８】
本発明により、ＬＥＤチップの両電極が設けられる側の１辺を回路基板の配線と直角になるようにＬＥＤチップをボンディングすることにより、両電極は配線方向をｘ軸とするとｘ座標が等しくなる。そのため、ｘ座標の入力は常に一定で、ｙ座標のみを入力すればよく、間違えることがなく、また自動機がｘ方向に２度動く必要がない。
【０００９】
前記エッチングにより除去されずに残存する半導体積層部の第１導電形の半導体層と前記第２の電極との平面形状で対向する部分がほぼ等距離になるように前記半導体積層部のエッチングおよび第２の電極形成がなされていることが、第１導電形層のエッチング端部の真下の第２導電形半導体層から第２の電極に至る距離はどこでも等しく、第１導電形の半導体層に広がった電流が第２導電形の半導体層に進む場合に、第２導電形の半導体層の一部に電流が集中しないで全体に広がって流れるため好ましい。
【００１０】
【発明の実施の形態】
つぎに、図面を参照しながら本発明の半導体発光素子の製法について説明をする。図１には、たとえば青色系の発光に適したチッ化ガリウム系化合物半導体が積層された本発明の製法により得られる半導体発光素子のチップの断面および平面説明図が示されている。
【００１１】
本発明の製法により得られる半導体発光素子は、たとえば図１に示されるように、サファイア（Ａｌ2 Ｏ3 単結晶）などからなる絶縁性の基板１の表面に発光層を形成する半導体積層部１０が形成されて、その表面側の第１導電形の半導体層（ｐ形層５）に、電流拡散層７を介してｐ側電極（第１の電極）８が電気的に接続されている。また、半導体積層部１０の一部が除去されて露出する第２導電形の半導体層（ｎ形層３）に電気的に接続されるようにｎ側電極（第２の電極）９が形成されている。本発明では、図１（ｂ）に平面図が示されるように、ＬＥＤチップ１１の平面形状の四角形の一辺Ｂに沿ってｐ側電極８およびｎ側電極９の両電極が設けられていることに特徴がある。その結果、ｐ側電極８とｎ側電極９とを結ぶ方向はＬＥＤチップ１１の一辺Ｂと平行となり、その辺を基準として一定の距離のところに両電極が存在する。なお、図１（ａ）は、（ｂ）のＡ-Ａ線断面図を示す。
【００１２】
このような形状のＬＥＤチップを形成するには、サファイア基板１のウェハ上に半導体層を積層して半導体積層部１０および電流拡散層７を形成した後に、ｎ側電極を形成するために４角形状のチップの１隅の半導体積層部１０の一部をエッチングしてｎ形層３を露出させる。そして露出するｎ形層３にｎ側電極９を形成すると共に、そのｎ側電極９が設けられた角部と隣接する角部にｐ側電極８を設けることにより得られる。
【００１３】
図１に示される例では、（ｂ）に平面図が示されるように、ｎ側電極９を形成するために積層された半導体層の一部がエッチングされて残存する半導体積層部１０のエッチングされたエッチング端部１０ａとｎ側電極９の前記端部１０ａとの対向部分が、平面形状でほぼ等距離になるように半導体積層部のエッチング端部１０ａおよびｎ側電極９の形状が形成されている。その結果、ｐ形層５のｎ側電極９に最も近いエッチング端部１０ａとｎ側電極９との距離はその対向部分のどこにおいても等しくなっている。このエッチング端部１０ａとｎ側電極９の形状の対向部を等距離にするには、半導体積層部１０のエッチングの際のレジスト膜などのマスクのパターニング、およびｎ側電極９を形成するためのマスクのパターニングをエッチング端部１０ａとｎ側電極９の対向部分が相互に平行になるように行うことにより簡単に形成される。
【００１４】
半導体積層部１０は、たとえばＧａＮからなる低温バッファ層、クラッド層となるｎ形のＧａＮおよび／またはＡｌＧａＮ系（ＡｌとＧａの比率が種々変わり得ることを意味する、以下同じ）化合物半導体の積層構造からなるｎ形層３、バンドギャップエネルギーがクラッド層のそれよりも小さくなる材料、たとえばＩｎＧａＮ系化合物半導体からなる活性層４、およびｐ形のＡｌＧａＮ系化合物半導体層および／またはＧａＮ層からなるｐ形層（クラッド層）５が、基板１上にそれぞれ順次積層されることにより構成されている。
【００１５】
この半導体発光素子を製造するには、たとえば有機金属化学気相成長法（ＭＯＣＶＤ法）により、反応ガスおよび必要なドーパントガスを導入してｎ形層３を１〜５μｍ程度、活性層４を０.０５〜０.３μｍ程度、およびｐ形層５を０.２〜１μｍ程度、それぞれエピタキシャル成長する。その後、たとえばＮｉおよびＡｕをそれぞれ真空蒸着などにより積層してシンターし、合金化することにより、２〜１００ｎｍ程度の厚さに電流拡散層７を形成する。この電流拡散層７は、活性層４で発光する光を透過させる必要があるため、あまり厚く形成することはできないが、電流を充分に拡散させるためにはできるだけ厚い方がよく、両特性を満たすように設けられる。
【００１６】
ついで、表面にレジスト膜を設け、パターニングをして塩素ガスなどによる反応性イオンエッチングにより、積層された半導体層の一部を図１に示されるように除去する。この際、図１（ｂ）に示されるように、エッチング端部１０ａとｎ側電極９との平面形状における距離が、その対向部において等しくなるように形成するに場合には、このエッチングの際のマスクの形状がｎ側電極９の対向部分と相互に平行になるようにレジスト膜のパターニングをすることにより得られる。その後、たとえばリフトオフ法により、ＴｉとＡｕとを積層して両金属の積層構造からなるｐ側電極８を形成する。また同様に、たとえばリフトオフ法により、ＴｉとＡｌをそれぞれ積層してシンターすることにより両金属の合金層からなるｎ側電極９を形成し、ウェハから各チップにブレークする。このｎ側電極９を形成する際に、半導体積層部１０のエッチング端部１０ａの対向部とほぼ等距離になるようにマスクのパターニングを行うことにより、前述のようにｎ側電極９とエッチング端部１０ａとの距離が等しい、図１に示される構造のＬＥＤチップ１１が得られる。
【００１７】
本発明によれば、ｎ側電極９およびｐ側電極８がＬＥＤチップ１１の一辺Ｂに沿ってほぼ平行に設けられているため、両側に両電極用の配線３２が設けられている回路基板３１の配線３２間にＬＥＤチップ１１をマウントする場合に、前述の一辺Ｂがその配線３２と直角になるようにマウントすることにより、図２に示されるように、配線３２が設けられている方向をｘ方向とすると、両電極８、９のｘ座標が等しくなる。そのため、ワイヤボンディングのためのボンディングの位置の座標を入力する場合に、ｙ座標のみを入力すればよく、入力ミスが生じることがない。しかも、ワイヤボンディング時には、ｐ側およびｎ側の両電極のボンディングのためにボンディング機をｘ方向に移動させる必要がなく、ｙ方向の移動だけで金線３３による両電極のワイヤボンディングをすることができ、無駄な動きがなく短時間でワイヤボンディングをすることができる。
【００１８】
一方、ｐ側電極８からｎ側電極９に向かって電流が流れるため、両電極が沿って設けられる一辺と対向する辺側には電流が流れ難くなる。しかし、前述のように、ｐ形層５の表面に電流拡散層７が設けられることにより、電気抵抗が小さくなり、電流拡散層７で充分に電流が拡散する。そのため、ｐ形層５の全体に電流が広がり、ｐ形層５に広がった電流はその下側のｎ形層３に流れ、ｎ形層３に達した電流はｎ側電極９に向かって流れる。この場合、チップの平面図で、ｐ形層５のエッチング端部１０ａとｎ側電極９の平面形状における対向部がほぼ等距離になっておれば、エッチング端部１０ａの真下のｎ形層３とｎ側電極９との距離は対向部のどの位置でも等しく、直列抵抗が同じで、ｐ形層５からｎ形層３への電流経路が抵抗の小さい所に集中して偏るということがない。そのため、均一な発光が得られる。
【００１９】
本発明は、以上のように、ＬＥＤチップの一対の両電極が一辺に沿って平行になるように設けられているため、回路基板などにダイボンディングをしてワイヤボンディングをする場合に、自動機の座標設定が一方向のみでよく簡単に行える。したがって、両電極がＬＥＤチップの一辺に沿って平行に設けられておればよく、ＬＥＤチップの形状は４角形でなくても、３角形などの他の形状でもよい。また、電極（パッド）の形状も図１に示される例に限定されず、共に円形もしくは４角形状などの他の形状でもよい。さらに、少なくとも一方の電極が幅広く設けられる場合には、ワイヤボンディングをする幅を有する一部が他方の電極と共にＬＥＤチップの一辺に沿って設けられておれば、前述のようにｘ軸方向は一定で、ｙ軸方向の座標のみを設定することにより、両方の電極のワイヤボンディングをすることができる。
【００２０】
また、図１に示される例では、ｎ形層３とｐ形層５とで活性層４が挟持されるダブルヘテロ接合構造であるが、ｎ形層とｐ形層とが直接接合するｐｎ接合構造の半導体発光素子でも同様である。また、積層される半導体層の材料も一例であって、その材料には限定されないが、チッ化ガリウム系化合物半導体の場合にその電気抵抗が大きいため、前述のエッチング端部とｎ側電極との平面形状における対向部を平行にする効果が大きい。
【００２１】
【発明の効果】
本発明によれば、一対の両電極がＬＥＤチップの一辺に沿って平行に設けられているため、回路基板などにボンディングをして自動機によりワイヤボンディングをする場合に、ボンディング位置の設定が一方向だけでよいため、入力ミスが少なくなり、またボンディング時の自動機の移動が一方向のみでよいため、無駄な動きがなく、高作業能率で、かつ、高歩留りで組立てをすることができる。
【００２２】
さらに、ｐ形層のエッチング端部とｎ側電極の対向部が等距離になるように形成されることにより、電流が部分的に集中しないため、部分的に半導体層が劣化して寿命を短くしたり、不良に至らしめることがない。
【図面の簡単な説明】
【図１】 本発明の製法により得られる半導体発光素子のチップの断面および平面説明図である。
【図２】本発明のＬＥＤチップが回路基板などにボンディングされてワイヤボンディングされるときの説明図である。
【図３】従来の半導体発光素子の一例の斜視説明図である。
【図４】従来のＬＥＤチップのワイヤボンディングの説明図である。
【符号の説明】
１ 基板
３ ｎ形層
５ ｐ形層
８ ｐ側電極
９ ｎ側電極
１０ 半導体積層部[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor light emitting device in which a semiconductor layer is laminated on a substrate, and both p-side and n-side electrodes are formed on the surface side of the laminated semiconductor layer. More specifically, the present invention relates to a method for manufacturing a semiconductor light emitting device provided with electrodes so that it can be easily performed without fail when wire bonding is performed to both electrodes (pads).
[0002]
[Prior art]
For example, a blue semiconductor light-emitting element is formed of a gallium nitride compound semiconductor on an insulating substrate 21 made of sapphire as shown in a schematic diagram of an example of the light-emitting element chip (hereinafter referred to as an LED chip) in FIG. The layers are stacked and both the p-side electrode 28 and the n-side electrode 29 are provided on the surface side. That is, an n-type layer (cladding layer) 23 in which, for example, n-type GaN is epitaxially grown on a wafer-like sapphire substrate 21, and a material whose band gap energy is smaller than that of the cladding layer, such as InGaN-based (In and Ga The active layer 24 made of a compound semiconductor and a p-type layer (cladding layer) 25 made of p-type GaN are laminated, and the p-type layer 25 on the surface thereof is laminated. The p-side electrode 28 is electrically connected, and the n-side electrode 29 is provided by being electrically connected to the n-type layer 23 exposed by etching a part of the laminated semiconductor layer. Is formed. With this structure, when a voltage is applied between both electrodes, a current flows from the p-side electrode 28 to the n-side electrode 29, and light is emitted when the current flows through the active layer 24. Therefore, both electrodes (pads) 28 and 29 are arranged at the farthest positions of the quadrangular LED chip, that is, the diagonal of the quadrangular shape, as shown in FIG. It is provided at both ends of the direction.
[0003]
The LED chip 30 is die-bonded on a circuit board 31 made of glass epoxy or the like, and as shown in FIG. 4, the p-side electrode 28 and the n-side electrode 29 are respectively connected to the wiring 32 of the circuit board 31 with a gold wire 33 or the like. Is incorporated into the circuit by wire bonding. In this wire bonding, the x-coordinates of the positions of the electrodes 28 and 29 of the LED chip 30 are input to an automatic machine, and the y-coordinates of the wiring 32 of the circuit board 31 at that time are simultaneously input to perform bonding automatically. .
[0004]
[Problems to be solved by the invention]
As described above, when the two electrodes provided on the LED chip are provided along the diagonal direction, when the LED chip is bonded to the circuit board or the like, the wiring on the circuit board and one side of the LED chip are Because they are die-bonded to be parallel (or perpendicular), the two electrodes differ in both their x and y coordinates. Therefore, the coordinate input when wire bonding is performed must input the y coordinate for each of the two x coordinates. For this reason, there is a problem in that an input error is made between the p-side electrode and the n-side electrode, resulting in a bonding mistake. Furthermore, in order to wire bond one LED chip, the automatic wire bonding machine must be stopped by moving it to two places in the x-axis direction, and moving in the y direction each time for bonding. . As a result, there are problems that the efficiency of the automatic machine is lowered and the yield is lowered.
[0005]
The present invention was made in order to solve such a problem. When a pair of electrodes (pads) are provided on the same side of the substrate and wire bonding is performed on both electrodes (pads) by an automatic machine, It is an object of the present invention to provide a method of manufacturing a semiconductor light emitting device having a position of an electrode (pad) that can be bonded efficiently with simple input data and without waste of movement of an automatic machine.
[0006]
[Means for Solving the Problems]
A method of manufacturing a semiconductor light emitting device according to the present invention includes a rectangular substrate, a semiconductor stacked portion on which a gallium nitride compound semiconductor is stacked to form a light emitting layer on the substrate, and a surface of the semiconductor stacked portion. A current diffusion layer, a first electrode provided on the current diffusion layer and connected to a first conductivity type semiconductor layer on a surface side of the semiconductor multilayer portion, and a part of the semiconductor multilayer portion is etched. A light emitting element chip having a square planar shape is formed from the second electrode connected to the second conductive type semiconductor layer removed and exposed by the step, and the first and second electrodes are used for wire bonding. The electrode has a width for wire bonding, is formed in a planar or circular or square shape, and in the planar shape of the light-emitting element chip, at a position approximately the same distance from an edge of one side, and The first and second electrodes are respectively formed at two corners of a square shape, which are both ends of one side, and the light emitting element chip has two wirings formed in parallel between the wirings of the circuit board. The one side of the light emitting element chip is mounted so as to be orthogonal to the wiring, and the first and second electrodes are respectively connected to one and the other of the two wirings by wire bonding, and A method of manufacturing a semiconductor light emitting device in which the extending direction of the two wirings is set to the x-axis, and the first and second electrodes and the two wirings are bonded so that the positions where wire bonding is performed have the same x coordinate. Then, for the wire bonding of the first and second electrodes, wire bonding is performed without moving the bonding machine in the x-axis direction. It is characterized by a door.
[0007]
Here, the gallium nitride compound semiconductor is a compound in which a group III element Ga and a group V element N or a part of the group III element Ga is substituted with another group III element such as Al or In, and A semiconductor composed of a compound in which a part of N of the group V element is substituted with another group V element such as P or As. In addition, the first conductivity type and the second conductivity type mean that when one of the n-type and p-type semiconductor polarities is the first conductivity type, the other p-type or n-type is the second conductivity type. Means that. In addition, the electrode means an electrode part (electrode pad) formed so as to be capable of wire bonding. When one electrode is formed widely, a part of the electrode is along the one side together with the other electrode. Included.
[0008]
According to the present invention, by bonding the LED chip so that one side of the LED chip on which both electrodes are provided is perpendicular to the wiring of the circuit board, both electrodes have the same x coordinate when the wiring direction is the x axis. . Therefore, the input of the x coordinate is always constant, it is only necessary to input the y coordinate, there is no mistake, and the automatic machine does not need to move twice in the x direction.
[0009]
Etching of the semiconductor stacked portion and the first portion of the semiconductor stacked portion remaining without being removed by the etching so that the facing portions of the first conductivity type semiconductor layer and the second electrode in the planar shape are substantially equidistant . 2 is formed, the distance from the second conductivity type semiconductor layer directly below the etching end of the first conductivity type layer to the second electrode is the same everywhere, and spreads to the semiconductor layer of the first conductivity type. When the current flows to the second conductivity type semiconductor layer, the current does not concentrate on a part of the second conductivity type semiconductor layer and flows in a wide range, which is preferable.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Next, a method for manufacturing the semiconductor light emitting device of the present invention will be described with reference to the drawings. FIG. 1 shows a cross-sectional and plan view of a chip of a semiconductor light emitting device obtained by the manufacturing method of the present invention in which, for example, a gallium nitride compound semiconductor suitable for blue light emission is laminated.
[0011]
As shown in FIG. 1, for example, the semiconductor light emitting device obtained by the manufacturing method of the present invention has a semiconductor laminated portion 10 that forms a light emitting layer on the surface of an insulating substrate 1 made of sapphire (Al 2 O 3 single crystal). The p-side electrode (first electrode) 8 is electrically connected to the first conductivity type semiconductor layer (p-type layer 5) on the surface side through the current diffusion layer 7. In addition, an n-side electrode (second electrode) 9 is formed so as to be electrically connected to the semiconductor layer (n-type layer 3) of the second conductivity type exposed by removing a part of the semiconductor stacked portion 10. ing. In the present invention, both the p-side electrode 8 and the n-side electrode 9 are provided along one side B of the square shape of the planar shape of the LED chip 11 as shown in the plan view of FIG. There is a feature. As a result, the direction connecting the p-side electrode 8 and the n-side electrode 9 is parallel to one side B of the LED chip 11, and both electrodes exist at a certain distance with respect to the side. FIG. 1A shows a cross-sectional view taken along line AA in FIG.
[0012]
In order to form the LED chip having such a shape, a semiconductor layer is stacked on the wafer of the sapphire substrate 1 to form the semiconductor stacked portion 10 and the current diffusion layer 7, and then a square is formed to form an n-side electrode. The n-type layer 3 is exposed by etching a part of the semiconductor laminated portion 10 at one corner of the shaped chip. Then, the n-side electrode 9 is formed on the exposed n-type layer 3 and the p-side electrode 8 is provided at a corner adjacent to the corner where the n-side electrode 9 is provided.
[0013]
In the example shown in FIG. 1, as shown in the plan view of FIG. 1B, a part of the semiconductor layer laminated to form the n-side electrode 9 is etched and the remaining semiconductor laminated portion 10 is etched. The shape of the etching end portion 10a and the n-side electrode 9 of the semiconductor stacked portion is formed so that the facing portions of the etching end portion 10a and the end portion 10a of the n-side electrode 9 are substantially equidistant in a planar shape. Yes. As a result, the distance between the etching end portion 10a closest to the n-side electrode 9 of the p-type layer 5 and the n-side electrode 9 is equal everywhere in the opposite portion. In order to make the opposite ends of the shape of the etching end portion 10a and the n-side electrode 9 equidistant, patterning of a mask such as a resist film during the etching of the semiconductor stacked portion 10 and the formation of the n-side electrode 9 are performed. The mask patterning is easily performed by performing the patterning so that the facing portions of the etching end 10a and the n-side electrode 9 are parallel to each other.
[0014]
The semiconductor laminated portion 10 is a laminated structure of a low-temperature buffer layer made of, for example, GaN, n-type GaN and / or AlGaN-based (which means that the ratio of Al and Ga can be variously changed, the same applies hereinafter) compound semiconductor that becomes a cladding layer An n-type layer 3 composed of a material having a band gap energy smaller than that of the cladding layer, for example, an active layer 4 composed of an InGaN-based compound semiconductor, and a p-type composed of a p-type AlGaN-based compound semiconductor layer and / or a GaN layer. A layer (cladding layer) 5 is formed by sequentially laminating on the substrate 1.
[0015]
In order to manufacture this semiconductor light emitting device, the reaction gas and the necessary dopant gas are introduced by, for example, metal organic chemical vapor deposition (MOCVD method), the n-type layer 3 is about 1 to 5 μm, and the active layer 4 is 0 Epitaxial growth of about 0.05 to 0.3 μm and the p-type layer 5 of about 0.2 to 1 μm are performed. Thereafter, for example, Ni and Au are laminated by vacuum deposition or the like, sintered, and alloyed to form the current diffusion layer 7 to a thickness of about 2 to 100 nm. The current diffusion layer 7 needs to transmit light emitted from the active layer 4 and cannot be formed so thick. However, the current diffusion layer 7 should be as thick as possible in order to sufficiently diffuse the current and satisfy both characteristics. It is provided as follows.
[0016]
Next, a resist film is provided on the surface, patterning is performed, and a part of the stacked semiconductor layers is removed by reactive ion etching using chlorine gas or the like as shown in FIG. At this time, as shown in FIG. 1B, in the case of forming the etching end portion 10a and the n-side electrode 9 so that the distance in the planar shape is equal at the opposite portion, the etching is performed. The resist film is patterned so that the shape of the mask is parallel to the opposing portion of the n-side electrode 9. Thereafter, Ti and Au are laminated by, for example, a lift-off method to form the p-side electrode 8 having a laminated structure of both metals. Similarly, Ti and Al are laminated and sintered by, for example, a lift-off method to form the n-side electrode 9 made of an alloy layer of both metals, and break from the wafer to each chip. When the n-side electrode 9 is formed, the n-type electrode 9 and the etching end are etched as described above by patterning the mask so as to be substantially equidistant from the facing portion of the etching end portion 10a of the semiconductor stacked portion 10. The LED chip 11 having the structure shown in FIG. 1 having the same distance from the portion 10a is obtained.
[0017]
According to the onset bright, since the n-side electrode 9 and the p-side electrode 8 is provided substantially in parallel along one side B of the LED chip 11, circuit wirings 32 for the electrodes on either side are provided a substrate When the LED chip 11 is mounted between the wirings 32 of the 31, the direction in which the wiring 32 is provided as shown in FIG. 2 by mounting so that the one side B is perpendicular to the wiring 32. Is the x direction, the x coordinates of both electrodes 8 and 9 are equal. For this reason, when inputting the coordinates of the bonding position for wire bonding, only the y coordinate needs to be input, and no input error occurs. Moreover, at the time of wire bonding, it is not necessary to move the bonding machine in the x direction for bonding both the p-side and n-side electrodes, and wire bonding of both electrodes by the gold wire 33 can be performed only by movement in the y direction. It is possible to perform wire bonding in a short time without wasteful movement.
[0018]
On the other hand, since the current flows from the p-side electrode 8 toward the n-side electrode 9, it is difficult for the current to flow on the side opposite to one side along which both electrodes are provided. However, as described above, by providing the current diffusion layer 7 on the surface of the p-type layer 5, the electric resistance is reduced, and the current is sufficiently diffused in the current diffusion layer 7. Therefore, the current spreads over the entire p-type layer 5, the current spread in the p-type layer 5 flows to the n-type layer 3 below, and the current reaching the n-type layer 3 flows toward the n-side electrode 9. . In this case, in the plan view of the chip, the n-type layer 3 just below the etching end 10a is provided if the etching end 10a of the p-type layer 5 and the facing portion in the planar shape of the n-side electrode 9 are substantially equidistant. The distance between the n-side electrode 9 and the n-side electrode 9 is the same at any position in the facing portion, the series resistance is the same, and the current path from the p-type layer 5 to the n-type layer 3 is not concentrated and biased in a small resistance area. . Therefore, uniform light emission can be obtained.
[0019]
In the present invention, as described above, since the pair of both electrodes of the LED chip are provided so as to be parallel along one side, an automatic machine is used when wire bonding is performed by die bonding to a circuit board or the like. The coordinate setting can be done in only one direction. Therefore, it is sufficient that both electrodes are provided in parallel along one side of the LED chip, and the shape of the LED chip may not be a quadrangle, but may be another shape such as a triangle. Further, the shape of the electrode (pad) is not limited to the example shown in FIG. 1 and may be other shapes such as a circular shape or a quadrangular shape. Furthermore, when at least one of the electrodes is provided widely, the x-axis direction is constant as described above if a part having a width for wire bonding is provided along one side of the LED chip together with the other electrode. Thus, by setting only the coordinate in the y-axis direction, wire bonding of both electrodes can be performed.
[0020]
Further, in the example shown in FIG. 1, a double heterojunction structure in which the active layer 4 is sandwiched between the n-type layer 3 and the p-type layer 5 is a pn junction in which the n-type layer and the p-type layer are directly joined. The same applies to the semiconductor light emitting device having the structure. In addition, the material of the semiconductor layer to be stacked is also an example, and is not limited to the material. However, in the case of a gallium nitride compound semiconductor, the electrical resistance is large, so that the above-described etching end portion and the n-side electrode The effect of making the opposing portions in the planar shape parallel is great.
[0021]
【The invention's effect】
According to the present invention, since a pair of both electrodes are provided in parallel along one side of the LED chip, the bonding position is set when bonding to a circuit board or the like and wire bonding is performed by an automatic machine. Since only the direction is required, input errors are reduced, and since the automatic machine only needs to move in one direction during bonding, there is no wasteful movement, high work efficiency, and high yield. .
[0022]
Furthermore, since the etching end portion of the p-type layer and the facing portion of the n-side electrode are formed at the same distance, the current is not partially concentrated, so that the semiconductor layer is partially deteriorated and the life is shortened. And will not lead to defects.
[Brief description of the drawings]
BRIEF DESCRIPTION OF DRAWINGS FIG. 1 is a cross-sectional and plan view of a chip of a semiconductor light emitting device obtained by the production method of the present invention.
FIG. 2 is an explanatory diagram when the LED chip of the present invention is bonded to a circuit board or the like and wire-bonded.
FIG. 3 is an explanatory perspective view of an example of a conventional semiconductor light emitting element.
FIG. 4 is an explanatory diagram of wire bonding of a conventional LED chip.
[Explanation of symbols]
1 Substrate 3 n-type layer 5 p-type layer 8 p-side electrode 9 n-side electrode 10 Semiconductor laminated portion

Claims (2)

四角形状の基板と、該基板上に発光層を形成すべくチッ化ガリウム系化合物半導体が積層される半導体積層部と、該半導体積層部の表面に形成される電流拡散層と、該電流拡散層上に設けられ前記半導体積層部の表面側の第１導電形の半導体層に接続して設けられる第１の電極と、前記半導体積層部の一部がエッチングにより除去されて露出する第２導電形の半導体層に接続して設けられる第２の電極とから平面形状が四角形状の発光素子チップが形成され、前記第１および第２の電極がワイヤボンディング用電極としてワイヤボンディングをする幅を有し、平面形状で円形または四角形状に形成されると共に、前記発光素子チップの平面形状で、１つの１辺の端縁からほぼ同じ距離の位置で、かつ、前記１つの１辺の両端部である四角形状の２隅に前記第１および第２の電極がそれぞれ形成され、前記発光素子チップが、平行に２つの配線が形成された回路基板の該配線間に、前記発光素子チップの前記１つの１辺が前記配線と直交するようにマウントされ、前記第１および第２の電極が、それぞれ前記２つの配線の一方および他方とワイヤボンディングにより接続され、かつ、前記２つの配線の延びる方向をｘ軸として前記第１および第２の電極ならびに前記２つの配線にそれぞれワイヤボンディングされる位置が同じｘ座標になるようにボンディングされてなる半導体発光素子の製法であって、前記第１および第２の電極の前記ワイヤボンディングのために、ボンディング機をｘ軸方向に移動させることなくワイヤボンディングをすることを特徴とする半導体発光素子の製法。A rectangular substrate, a semiconductor laminate on which a gallium nitride compound semiconductor is laminated to form a light emitting layer on the substrate, a current diffusion layer formed on the surface of the semiconductor laminate, and the current diffusion layer A first electrode provided on and connected to a semiconductor layer of the first conductivity type on the surface side of the semiconductor stacked portion; and a second conductivity type in which a part of the semiconductor stacked portion is removed by etching and exposed. A square light emitting element chip is formed from a second electrode connected to the semiconductor layer, and the first and second electrodes have a width for wire bonding as wire bonding electrodes. The planar shape of the light-emitting element chip is formed in a circular shape or a square shape, and is located at substantially the same distance from the edge of one side and at both ends of the one side. Square shape The first and second electrodes are respectively formed at two corners, and the one side of the light emitting element chip is between the wirings of the circuit board on which the light emitting element chip is formed with two wirings in parallel. Mounted so as to be orthogonal to the wiring, the first and second electrodes are respectively connected to one and the other of the two wirings by wire bonding, and the extending direction of the two wirings is the x-axis A method of manufacturing a semiconductor light emitting device , wherein the first and second electrodes and the two wirings are bonded so that the positions where wire bonding is performed have the same x coordinate. for wire bonding, method of the semiconductor light emitting device characterized by the wire bonding without moving the bonding machine in the x-axis direction 前記エッチングにより除去されずに残存する半導体積層部の第１導電形の半導体層と前記第２の電極との平面形状で対向する部分がほぼ等距離になるように前記半導体積層部のエッチングおよび第２の電極形成がなされてなる請求項１記載の半導体発光素子の製法。Etching of the semiconductor stacked portion and the first portion of the semiconductor stacked portion remaining without being removed by the etching so that the facing portions of the first conductivity type semiconductor layer and the second electrode in the planar shape are substantially equidistant. The method for producing a semiconductor light emitting device according to claim 1, wherein two electrodes are formed.
JP1122697A 1997-01-24 1997-01-24 Manufacturing method of semiconductor light emitting device Expired - Lifetime JP3974676B2 (en)

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