JPH09252134A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize structure in fine channel length by forming an insular first semiconductor layer in a partial region on an SOI substrate, a second semiconductor layer on the first semiconductor layer and a third semiconductor layer having the same conductivity type as the first semiconductor layer on the second semiconductor layer and forming a gate electrode section to a part of a side face through an insulating film. SOLUTION: A semiconductor layer as a drain layer 4 is formed onto a silicon substrate 1. A semiconductor layer as a channel layer 5 is formed. A semiconductor layer as a source layer 6 is shaped. A gate insulating film 7 is formed onto one surfaces of the side faces of each layer of the drain layer 4, the channel layer 5 and the source layer 6, and a gate electrode 8 is formed to the upper section of the gate insulating film 7. Accordingly, the channel length of a MOS transistor can be controlled by the film thickness of silicon epitaxial growth, the MOS transistor having gate length finer than a conventional MOS transistor can be realized, and a device having high driving force can be acquired.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device,
In particular, the present invention relates to a structure of a fine MOS transistor which provides a digital integrated circuit and an analog integrated circuit with high driving force and high reliability.

[0002]

2. Description of the Related Art Conventionally, a method of forming an element on an SOI substrate is widely known in order to realize a MOS transistor having a high driving force.

FIG. 4 is a cross-sectional view of such a conventional semiconductor device, in which a MOS type transistor including a source / drain region 9, a gate insulating film 7 and a gate electrode 8 is arranged on a silicon substrate 1 to form a silicon oxide film 2. It has the structure formed above.

[0004]

A conventional semiconductor device is:
Since it is configured as described above, it is important to miniaturize the gate length in order to increase the driving force of the MOSFET.
Gate butterflies have had lithographic limitations on gate patterning. Further, the reduction of the size of the source / drain region is also limited for the same reason, and it is difficult to reduce the parasitic capacitance.

The present invention solves the above-mentioned problems of the prior art, realizes a structure having a fine channel length as compared with the conventional SOI transistor, and has a small parasitic capacitance MOS.
An object of the present invention is to provide a semiconductor device that enables an FET type transistor.

[0006]

In order to achieve the above object, the present invention provides a first semiconductor layer of a first conductivity type laminated on a semiconductor substrate via an insulating film, and the first semiconductor layer. A second semiconductor layer laminated on the semiconductor layer, a third semiconductor layer of the first conductivity type laminated on the second semiconductor layer, and an exposed portion of the second semiconductor layer. The present invention provides a semiconductor device including an electrode arranged in a partial region via an insulating film.

In the semiconductor device of the present invention, an island-shaped first semiconductor layer is formed on a partial region of an SOI substrate, and an island-shaped first semiconductor layer is formed thereon.
A second semiconductor layer is formed, and a third semiconductor layer having the same conductivity type as the first semiconductor layer is formed on the second semiconductor layer, and each of these semiconductor layers is molded to expose the side surface, Forming a gate electrode portion on a part of the side surface of the semiconductor layer through an insulating film,
After that, a MOS type transistor is formed by drawing out wirings from the first and third semiconductor layers and the gate electrode portion. As a result, the channel length of the MOS type transistor is compared with the case where it is formed by a normal exposure method. Then, it can be formed finely, the driving force of the transistor is increased, and the parasitic capacitance of the source / drain portion is significantly reduced.

[0008]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a cross-sectional view for explaining a semiconductor device according to an embodiment of the present invention in the order of steps in the manufacturing method thereof.

First, as shown in FIG. 1A, in a structure in which a silicon oxide film 2 is arranged on a silicon substrate 1 and a silicon layer 3 is further laminated thereon, the silicon layer 3
Is patterned into a desired shape by RIE using a photoresist mask, and is left on the silicon oxide film 2.

Subsequently, as shown in FIG. 1B, silicon is epitaxially grown in the atmosphere containing impurities of the first conductivity type (for example, phosphorus) with the silicon layer 3 as a nucleus to form the drain layer 4 and the silicon. A semiconductor layer to be formed. As the conditions at this time, for example, disilane gas and phosphine gas are used at 750 ° C.

Next, under the condition that impurities are not introduced, silicon is epitaxially grown to a desired film thickness to form a semiconductor layer to be the channel layer 5.

Then, silicon is epitaxially grown to a desired film thickness in an atmosphere containing impurities of the first conductivity type to form a semiconductor layer to be the source layer 6.

The channel layer 5 may be formed in an atmosphere using a conductivity type impurity different from the conductivity type impurity used for growing the drain layer 4 and the source layer 6, for example, boron. In this case, it can be realized by using diborane gas and disilane gas.

When the conductivity type impurities are not used for forming the channel layer 5, the silicon layer becomes an intrinsic silicon layer.

After that, one side surface of each of the drain layer 4, the channel layer 5, and the source layer 6 is removed by RIE using a photoresist mask, and these are exposed at the side portions.

The train layer 4, the channel layer 5 and the source layer 6 may have various forms as shown in FIGS. 2 (A) to 2 (C).

Subsequently, as shown in FIG. 1C, the side surfaces of the drain layer 4, the channel layer 5 and the source layer 6 are oxidized in an oxygen atmosphere to form a gate insulating film 7. The conditions at this time are, for example, 800 ° C. and RTO of 20 seconds. In addition,
2 (B) and 2 (C), the channel region is exposed by an etch-back method, a gate oxide film is formed, and a gate electrode is formed thereon, as shown in FIG. May be.

Subsequently, a conductive type polycrystalline silicon layer is deposited in close contact with the gate insulating film 7, and the gate electrode 8 is formed into a desired shape by photoresist and RIE.

On the other hand, as a conductive layer for forming the gate electrode 8, a metal layer or metal silicide may be applied.

Next, as shown in FIG. 1D, a photoresist mask and RIE method are used on the side surface of the drain layer 4, the channel layer 5, and the source layer 6 different from the side where the gate electrode 8 is formed. Only the source layer 6 and the channel layer 5 are removed to expose the surface of the drain layer 4. This allows
The metal wiring for the drain layer 4 is facilitated.

As shown in FIG. 3, by removing the source layer 6 and the channel layer 5 in a stepwise manner, the respective surfaces of the drain layer 4, the channel layer 5 and the source layer 6 are partially exposed individually. You may do it. In this case, metal wiring can be individually connected to each of the drain layer 4, the channel layer 5, and the source layer 6.

After completing the basic structure as described above, an insulating film is deposited, openings are formed in the contact portions of the drain layer 4, the channel layer 5 and the source layer 6 and metal wirings are arranged to complete the semiconductor device. Complete.

By the steps as described above, the channel length of the MOS transistor can be controlled by the film thickness of the silicon epitaxial growth, and theoretically, for example, the atomic level or molecule of silicon of about 3 to 5 angstroms can be controlled. It is possible to control the channel length at the level. As a result, a MOS transistor having a fine gate length can be realized as compared with a conventional MOS transistor, and a device with high driving force can be obtained.

Further, since the source / drain regions can be controlled by the film thickness of epitaxial growth, the parasitic capacitance can be greatly reduced as compared with the conventional structure. As a result, high-speed digital operation and analog operation become possible.

The transistor of the above embodiment can be constructed as an NMOS or a PMOS.

[0027]

As described above, in the semiconductor device of the present invention, the channel of the MOS transistor is formed by controlling the film thickness of epitaxial growth.
Since it is possible to accurately form a minute channel length,
A device with a high driving force can be realized, while parasitic capacitance can be reduced also in the source and drain, so that there is an effect that a device suitable for high speed driving can be realized.

[Brief description of drawings]

FIG. 1 is a process sectional view of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing another example of the step shown in FIG.

FIG. 3 is a cross-sectional view showing another example of the step shown in FIG.

FIG. 4 is a cross-sectional view of a conventional semiconductor device.

[Explanation of symbols]

 1 silicon substrate 2 silicon oxide film 3 silicon layer 4 drain layer 5 channel layer 6 source layer 7 gate insulating film 8 gate electrode 9 source / drain region 10 channel region

Claims (5)

[Claims] 1. A first semiconductor layer of a first conductivity type laminated on a semiconductor substrate with an insulating film interposed therebetween, and a second semiconductor layer laminated on the first semiconductor layer. A third semiconductor layer of a first conductivity type stacked on the second semiconductor layer; and an electrode arranged in an exposed partial region of the second semiconductor layer with an insulating film interposed therebetween. A semiconductor device characterized by the above. 2. The semiconductor device according to claim 1, wherein the second semiconductor layer is composed of an intrinsic semiconductor. 3. The semiconductor device according to claim 1, wherein the second semiconductor layer is composed of a semiconductor layer of a second conductivity type. 4. The semiconductor device according to claim 1, wherein the electrode is formed of at least one of polycrystalline silicon layers. 5. The first semiconductor layer constitutes a drain layer, the second semiconductor layer constitutes a channel layer, the third semiconductor layer constitutes a source layer, and the electrode constitutes a gate. The semiconductor device according to claim 1.