JPH09252088A - Semiconductor device equipped with resistor array for electron potentiometer and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device equipped with a resistor array which is used for an electron potentiometer and minimized in area exclusively occupied by it, wherein the resistor array is composed of resistor chips which are different from each other in maximum resistance value and resistance resolution and made common in a layout design for resistor chip as a whole. SOLUTION: A polysilicon resistor or a diffusion resistor is used as a resistor element which forms a resistor array on a semiconductor substrate for an electron potentiometer, wherein the resistor element is controlled in sheet resistance without being changed in size so as to be set at a specified resistance value corresponding to the resistance resolution of the electron potentiometer. When a resistor array 1 is formed, the resistor element is controlled in sheet resistance without being changed in size by controlling impurities in concentration and implanted ions in does so as to be set at a specified resistance value corresponding to the resistance resolution of the electron potentiometer. The electron potentiometer is equipped with the resistor array 1, a decoder 2, and a transfer gate 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resistance element of a resistance network of a semiconductor integrated circuit, and more particularly, to a resistance array for an electronic potentiometer which variably controls a resistance value by digital control.

[0002]

2. Description of the Related Art A conventional electronic potentiometer is shown in a functional block diagram of FIG. The figure shows the electronic potentiometer "X9CMME" series manufactured by Xicor. The structure of one resistance element Rn (n = 1 to 99) used in the resistance array 1 shown in this figure will be described with reference to a schematic plan view of a semiconductor substrate. This electronic potentiometer has a VL terminal and a V terminal, which correspond to the fixed terminals of the mechanical potentiometer.
A resistor array 1 having 99 resistance elements R1 to R99 connected in series and having the same resistance value with the H terminal,
It comprises a decoder 2 and a transmission gate 3. In the electronic potentiometer, one end of 100 transmission gates SW0 to SW99 corresponding to each resistance element is connected to both ends of each resistance element, and the other end is commonly connected to a VW terminal corresponding to a movable terminal of a mechanical potentiometer. In addition, the transmission gates SW0 to SW99 have 7-bit input data DO0 to D, respectively.
It is controlled on and off by O9. For example, assuming that the maximum resistance of the electronic potentiometer is 10 kΩ, the resistance value resolution per resistance element R1 to R99 is 10
It becomes kΩ ÷ 99 to 101Ω.

In this case, the electronic potentiometer has two terminals, one of its VL or VH terminal and the other of its VW terminal.
When the terminal is used, the output signal DO0 to DO99 of the decoder is turned on / off in accordance with SW0 to SW99.
Based on the resistance value resolution of Ω, it operates as a variable resistor that linearly changes the resistance value range of 0Ω to 10 kΩ. Further, for example, when 0V is applied to the VL terminal and 10V is applied to the VH terminal and the Vw terminal is used as the output terminal, this electronic potentiometer is turned on / off by the transmission gates SW0 to SW99 corresponding to the output signals DO0 to DO99 of the decoder. 10
It can also operate as a variable voltage divider that linearly changes the range of 0 V to 10 V with a voltage value resolution of 1 mV. The maximum resistance value and resistance value resolution of the electronic potentiometer are various according to the needs of the market. For example, when the maximum resistance value is set to 10 kΩ, 50 kΩ, and 100 kΩ, the semiconductor substrate can be formed by using a conventional technique. 2 and FIG. 1 in the case of forming a semiconductor integrated circuit formed in
0 and FIG.

When the functional block of the electronic potentiometer shown in FIG. 1 has the same structure, the resistance elements R1 to R are used.
When the maximum value of these resistances is set to 10 kΩ, 50 kΩ, and 100 kΩ, the resistance resolution per 99 is about 101 Ω and about 505 Ω, respectively.
It becomes about 1.01 kΩ. The resistance value of the resistance array in the semiconductor integrated circuit formed on the semiconductor substrate is determined by the sheet resistance and the element size of the resistance element forming the resistance. For example, when a resistance element having a width of 10 μm and a sheet resistance of 101 Ω is used, the total resistance length when the maximum resistance is 10 kΩ is (10 kΩ ÷ 101 Ω) × 10 μm
Since it is 990 μm, 99 sheet resistance elements are required. Similarly, when the maximum resistance of the resistor array is 50 kΩ, the total resistance length is (50 kΩ ÷
101Ω) × 10 μm to 4950 μm, and 495 resistance elements for the sheet resistance are required. When the maximum resistance of the resistor array is 100 kΩ, the total resistance length is (100 kΩ ÷ 101 Ω) × 10 μm to 9900 μm.
Therefore, it is understood that 990 resistance elements for the sheet resistance are required.

The sheet resistance of the resistance element will be described with reference to FIG. The figure is a perspective view of a resistance element as a rectangular parallelepiped sample. A resistance value R of a diffusion resistance element having a length L, a width W, and a thickness T formed on a semiconductor substrate is given by the following equation. 1. When the n-type diffusion region of the semiconductor substrate is used as a resistance element, R = (L / W) (1 / q.μn.ND.T) = (L / W) Rs (Ω) .. When the p-type diffusion layer region of the semiconductor substrate is used as a resistance element, R = (L / W) (1 / q.μP.NA.T) = (L / W) Rs (Ω) .. Where q is the electronic charge (1.6 × 10 ^-13 coulomb),
μn is the electron mobility (cm ² / V se
c), μp are the mobility of holes (cm ² / V sec), ND
Is the impurity concentration of n-type impurities (cm ⁻³ ), and NA is the impurity concentration of p-type impurities (cm ⁻³ ). Rs is a sheet resistance of the diffusion region and has a unit of Ω / □. That is, the first
From equation and the second equation, sheet resistance represents the resistance of one square plate of material of thickness T.

Therefore, as described above, the resistance of the potentiometer, that is, the maximum value of the resistance of the resistance array is set to 10 k.
The area of the resistor array in the case of Ω, 50 kΩ, and 100 kΩ is 5 times as large as 50 kΩ with reference to 10 kΩ.
An area of 10 times is required for 00 kΩ. Conventionally, when a product with the same functional block configuration of the potentiometer and different specifications of the maximum resistance is integrated into a semiconductor integrated circuit,
For example, as shown in FIG. 10A, a resistance corresponding to one of the resistance elements R1 to R99 of the resistance array has a resistance value of, for example, 101Ω in advance (R1-1 to R1-). Ten,
R2-1 to R2-10, R3-1 to R3-10, ... Rn-1 to Rn-
10) will be arranged. Then, in the process of processing wiring such as aluminum when manufacturing a semiconductor integrated circuit on a semiconductor substrate, the maximum resistance value of the resistance array is 10 kΩ and the resistance value resolution per resistance element is 10 kΩ.
When making a product with a specification of 1Ω, the resistance of one resistor piece is 1
Since it is 01Ω, the wiring is processed by using a glass mask designed so that only the resistance R1-1 is connected to the wiring as shown in FIG. 10B as the resistance corresponding to one of the resistance elements R1 to R99. To do.

That is, one of the 10 resistance pieces is used as the resistance of the resistance element. Similarly, the maximum resistance of the resistor array is 5
With 0 kΩ, resistance value resolution per resistance element is 505
To make a product with Ω specifications, perform wiring processing using a glass mask designed so that the five resistors R1-1 to R1-5 are connected in series as shown in FIG. 11 (a). To do. When making a product with a maximum resistance value of the resistance array of 100 kΩ and a resistance value resolution of 1.01 kΩ per resistance element, as shown in FIG. 11 (b), the resistors R1-1 to R1-
Wiring is performed using a glass mask designed so that 10 resistors of 10 are connected in series. When integrating various products with different maximum resistance and resistance value resolution specifications of the potentiometer into a semiconductor integrated circuit on a semiconductor substrate,
If the ratio of resistance value resolution per electronic potentiometer is an integer multiple, the unit resistance of the greatest common divisor of resistance value resolution is equal to the number of the least common multiple without designing the layout of the entire chip for each specification. By arranging in advance, the electronic potentiometer can be formed only by designing and using only the glass mask used in the wiring processing step according to each specification. According to the above process, there are advantages that the development cost can be saved and the development period can be shortened as compared with the case of designing the layout of the entire chip one by one for each specification.

[0008]

Although the conventional electronic potentiometer and the method for forming the same have the above-mentioned advantages, only the resistance strip Rn-1 is required as the resistance value resolution as shown in FIG. 10B. In case of specifications, the remaining R1-2 to R1-
The area occupied by the nine resistance pieces of 10 on the semiconductor substrate (chip) was a useless area. If such a wasteful area is large, there is a problem that the chip size becomes large and the cost becomes high as compared with the case where the layout design of the entire chip is performed for each specification. As described above, the present invention relates to a case where a product in which the maximum value of resistance of an electronic potentiometer and the specification of resistance value resolution are different for each chip is made into a semiconductor integrated circuit on a semiconductor substrate by sharing a layout design of the entire chip in the related art. In order to prevent the chip size from increasing, a semiconductor device in which the area occupied by the resistor array is minimized and a method for manufacturing the semiconductor device in which the area occupied by the resistor array is minimized are provided.

[0009]

SUMMARY OF THE INVENTION The present invention uses a polysilicon resistor or a diffusion resistor as a resistance element for forming a resistance array for an electronic potentiometer on a semiconductor substrate, and does not change the dimensions of the resistance element, and the sheet of the resistance element is used. It is characterized by using a resistance element whose resistance is controlled so as to obtain a predetermined resistance value corresponding to the resistance value resolution of the potentiometer, and the occupied area of the resistance array can be minimized. Further, by controlling the impurity concentration of impurities and the ion implantation amount when forming the resistance array, the sheet resistance of the resistance element can be made to correspond to the resistance value resolution of the potentiometer without changing the dimensions of the resistance element. It is characterized by controlling so that a resistance value can be obtained. When the manufacturing method of the present invention is performed on a plurality of semiconductor substrates, a plurality of resistance elements having the same size and sheet resistance are formed on each semiconductor substrate. The resistance elements formed on any of the semiconductor substrates all have the same size, and the resistance value and sheet resistance of the resistance elements can be different for each semiconductor substrate.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a functional block diagram of a semiconductor substrate for explaining an electronic potentiometer of the present invention. One resistor element Rn used in the resistor array 1 shown in this figure
The structure of (n = 1 to 99) will be described with reference to a schematic plan view of a semiconductor substrate. This electronic potentiometer has the same resistance value between the VL terminal, which is the first or second terminal corresponding to the fixed terminal of the mechanical potentiometer, and the VH terminal, which is the second or first terminal. It comprises a resistor array 1 consisting of 99 resistor elements R1 to R99 connected to each other, a decoder 2 and a transmission gate 3. In the electronic potentiometer, one end of 100 transmission gates SW0 to SW99 corresponding to each resistance element is connected to both ends of each resistance element, and the other end is a third terminal corresponding to a movable terminal of a mechanical potentiometer VW. The transmission gates SW0 to SW99 are commonly connected to the terminals, and the input data D is 7 bits each.
On / off control is performed by O0 to DO9. For example,
When the maximum value of the resistance of the electronic potentiometer is 10 kΩ, the resistance value resolution per resistance element R1 to R99 is 10 kΩ ÷ 99 to 101 Ω.

In this case, the electronic potentiometer has one of its VL terminal and VH terminal (first terminal).
When two terminals of VW terminal and VW terminal (third terminal) are used, SW0 to SW99 are turned on / off corresponding to the output signals DO0 to DO99 of the decoder, and 0Ω to 10kΩ based on the resistance value resolution of 101Ω. It operates as a variable resistor that changes the resistance value range linearly. Also, for example, 0V for the VL terminal (second terminal) and 10V for the VH terminal (first terminal).
When V is applied and the Vw terminal (third terminal) is used as an output terminal, this electronic potentiometer is turned on / off in response to the decoder output signals DO0 to DO99.
0V with a voltage value resolution of 101mV by W0-SW99
It can also operate as a variable voltage divider that varies linearly in the 10V range.

3 (a), 4 (a), and 5 (a),
It is a schematic plan view of the resistance element formed in the semiconductor substrate of the Example of this invention, FIG.3 (b), FIG.4 (b), FIG.5 (b).
FIG. 7 is a schematic plan view of a conventional resistance element formed on a semiconductor substrate. In these figures, one resistance element Rn (n is included in the resistance array 1 having 99 resistances R1 to R99 connected in series and having the same resistance value between the VL terminal and the VH terminal. = 1 to 99) corresponding to the resistive element on the semiconductor substrate (see FIG. 1). FIG. 3A shows the first embodiment, and the resistance element Rn has a sheet resistance R
s is 101Ω / □, and the resistance value is 101Ω. A conventional resistance element R formed on a semiconductor substrate corresponding to this embodiment
n (sheet resistance Rs = 101Ω / □, resistance value = 101
Ω) is shown in FIG. FIG. 4A shows the second embodiment, and the resistance element Rn has a sheet resistance Rs of 5
The resistance value is 05Ω / □ and the resistance value is 505Ω. A conventional resistance element Rn (sheet resistance Rs = 505Ω / □, resistance value = 505Ω) formed on a semiconductor substrate corresponding to this embodiment is
It is shown in FIG. FIG. 5A shows the third embodiment, and the resistance element Rn thereof has a sheet resistance Rs of 1.01Ω.
/ □, the resistance value is 1.01Ω. The conventional resistance element Rn (sheet resistance Rs = 1.01Ω / □, resistance value = 1.01Ω) formed on the semiconductor substrate corresponding to this embodiment is
It shows in FIG.5 (b).

The resistor element Rn and its wiring are shown in FIGS. 3 (a), 4 (a) and 5 (a). The shape is, for example, a square planar shape. FIG. 3 (a)
In the first embodiment, the case where the resistance value of one resistor Rn in the resistor array is 101Ω will be described. The resistance value of the resistance element is obtained by multiplying the sheet resistance Rs by L / W, which is the dimension value of the length and width of the resistance element, as shown in the first equation or the second equation. Since the plane resistance of the resistance element is square, that is, the dimension ratio L / W = 1 of the length and the width, the sheet resistance Rs is 1 in order to set the resistance value of the resistance element in the figure to 101Ω.
If it is 01Ω / □, it will be good. Similarly, FIG.
To set the resistance value of one resistor Rn in the resistor array to 505Ω as in the second embodiment of FIG.
It is sufficient to set s to 505Ω / □. Furthermore, as in the third embodiment of FIG. 5A, one resistor Rn in the resistor array is used.
It can be seen that the sheet resistance Rs can be set to 1.01 kΩ / □ as described above in order to set the resistance value of 1 to 1.01 kΩ.

FIG. 6 is a schematic plan view of a semiconductor substrate on which the resistor array of the above-described embodiment is formed. The resistance element of the first embodiment shown in FIG. 3A is formed on the semiconductor substrate 10A of FIG. The resistor array 1 includes square resistive elements R1, R2, R3, ...
It is composed of R99, and these sheet resistance Rs is 101Ω.
/ □. In the semiconductor substrate 10 (B) of FIG. 6 (b),
The resistance element of the second embodiment shown in FIG. 4A is formed. The resistance array 1 is composed of square resistance elements R1, R2, R3, ..., R99 having a uniform area, and their sheet resistance Rs is 505 Ω / □. On the semiconductor substrate 10 (C) of FIG. 6 (c), the resistance element of the third embodiment shown in FIG. 5 (a) is formed. The resistor array 1 has a uniform area, for example, square resistor elements R1, R2, R.
3, ..., R99, and these sheet resistances R
s is 1.01 kΩ / □. The sheet resistance of the resistance element is set to a predetermined value without changing the dimensions of the resistance element by controlling the impurity concentration of impurities and the ion implantation amount when forming the resistance array 1 of the semiconductor substrate 10.

In these examples, the dimension ratio L / W = 1 of the length and width of the resistance element is set, but in the present invention, the dimension ratio L / W = 1 of the resistance element is not necessarily required. Because when L / W = 0.5, the value of the sheet resistance Rs is L / W
If the value of the sheet resistance Rs is doubled when L / W = 2, and the value of the sheet resistance Rs is increased 0.5 times when L / W = 1, the resistance value of the same value is obtained. This is because it can be obtained. That is, even if the resistance elements have the same size, the resistance value of the resistance element can be set to a predetermined value by controlling the value of the sheet resistance Rs. 3 (b), FIG. 4 (b), and FIG.
FIG. 10B shows the conventional resistance element Rn shown in FIGS. 10B to 11B (having resistance values of 101Ω, 505Ω, and
FIG. 10 is a schematic plan view of a conventional technique (1.01 kΩ). The planar shape of the resistance element was a square as in the above-mentioned embodiment so that it could be easily compared with that of the present invention.
In the prior art, when a product having different specifications for the maximum resistance value and resistance value resolution of an electronic potentiometer is formed into a semiconductor integrated circuit on a semiconductor substrate, the resistance value per resistance element in the resistance array according to each specification ( In the example, 101
Ω, 505Ω, 1.01kΩ) unit resistances (101Ω) with the greatest common divisor are arranged in advance for the number of least common multiples (10), and the resistance value of any specification is realized by wiring connection of aluminum etc. Is used.

Therefore, as shown in these figures, it is necessary to have ten resistance pieces which are the least common multiples. On the other hand, according to the present invention, the resistance value of the resistance element can be set to a predetermined value by controlling the sheet resistance Rs of the resistance element regardless of the specification of the resistance value. Since only one resistor array is required, the area of the resistor array occupying the semiconductor substrate is remarkably smaller than the conventional one. In order to control the sheet resistance of the resistance element described above, for example, when a diffusion resistance is formed as a resistance element on the semiconductor substrate, impurities are diffused and formed on the surface of the silicon semiconductor substrate by a method such as ion implantation. For example, phosphorus, arsenic, antimony, or the like is diffused to form an n-type diffusion region, and boron or the like is diffused to form a p-type diffusion region. The impurity concentration of impurities diffused at this time is adjusted. By doing so, the sheet resistance can be adjusted to a predetermined value. When polysilicon used for a gate, wiring, resistance, etc. in a recent silicon gate process is used as a resistance element, it can be realized by controlling the impurity concentration and adding the same.

Regarding the specific relationship between the impurity concentration and the sheet resistance, when a polysilicon film is used for the resistance element, for example, the impurity concentration is high (10 ²⁰ cm ^-3 to 10 ²¹ cm ^-3).
When the sheet resistance Rs is about 15 to 200Ω / □, a low resistance (10 ¹⁸ / cm ⁻³ or less) is obtained.
In the case of, the sheet resistance Rs is 1 MΩ / □ to 100 GΩ / □
The resistance element of is obtained. Further, as shown in FIG. 7, when a diffusion resistance formed on a semiconductor substrate is used as a resistance element, the sheet resistance depends on the ion implantation amount of impurities. In this characteristic diagram, the vertical axis represents the sheet resistance (Ω / □), and the horizontal axis represents the implantation amount (c) of impurities doped in the diffusion region.
m ^-2 ). Ion implantation amount is 10 ¹¹ cm ^-2 to 10 ¹⁶ c
When changed in the range of m ^-2 , the sheet resistance is 10Ω / □
To 100 kΩ / □ or more. A solid line in the figure is a sheet resistance-ion implantation amount characteristic diagram of a p-type diffusion resistance element in which boron is ion-implanted at an acceleration current of 100 keV, and a dotted line is a sheet of an n-type diffusion resistance element in which arsenic is ion-implanted at an acceleration current of 150 keV. It is a resistance-ion implantation amount characteristic view.

Next, the formation of the resistance element in the semiconductor substrate of the present invention will be described with reference to FIGS. 8 and 9 are cross-sectional views of a semiconductor substrate on which an electronic potentiometer is formed. FIG. 8 shows the CMO forming the resistance elements R1, R2 and R3 forming the resistance array and the transmission gate.
The S transistor is shown on the semiconductor substrate. Display of terminals is omitted. An n-type silicon semiconductor substrate 10, for example, is used as the semiconductor substrate on which the resistor array and the like are formed. n
A p-well 11 is formed on the type silicon semiconductor substrate 10. The field oxide film 4 is formed in the element isolation region of the semiconductor substrate 10. An n-channel gate electrode 6 made of, for example, polysilicon is formed on the p-well 11 via a gate oxide film 5 having a thickness of about 20 to 25 nm, and on the semiconductor substrate 10, made of, for example, polysilicon. P-channel gate electrode 7 is formed with gate oxide film 5 interposed. In the p well 11, n ⁺ source / drain regions 8 and 9 are formed below both side surfaces of the n channel gate electrode 6 to form an n channel transistor (NMOS). P on the semiconductor substrate 10
P ⁺ source / drain regions 12 and 13 are formed below both side surfaces of the channel gate electrode 7 to form a p-channel transistor (PMOS).

A high impurity concentration p ⁺ diffusion layer 14 is formed in the p well 11 for well bias, and the semiconductor substrate 1
A high impurity concentration n ⁺ diffusion layer 1 for substrate bias is provided on the 0 side.
5 are formed. In the embodiment of the present invention, the resistor array is formed on the field oxide film 4 on the surface of the semiconductor substrate. The resistance array is composed of polysilicon resistance elements. For example, the resistance elements R1, R2, and R3 have a sheet resistance of 101Ω / □ and a resistance value of 101Ω. The sheet resistance of this resistance element is adjusted by simultaneously doping all the resistance elements with impurities such as ion implantation. The surface of the semiconductor substrate 10 is covered with an interlayer insulating film 16 made of SiO ₂ or the like.
Also covers the resistance element 1 and the gate electrode. A metal wiring 17 such as Al is formed on the interlayer insulating film 16, and the metal wiring 17 is formed by removing the interlayer insulating film 16 and connecting the source / source of the resistor element, the semiconductor substrate, and the transistor through a contact hole provided. It is electrically connected to the drain region, the well and the like. An insulating protection film 18 such as SiO ₂ is provided on the semiconductor substrate 10 so as to cover the metal wiring 17.

As described above, the resistance element is formed of polysilicon, and two methods are used to form the resistance element on the semiconductor substrate. In the first method, first, a first polysilicon film is formed on a semiconductor substrate 10, impurities are ion-implanted into the first polysilicon film, and then patterned into a predetermined shape to form n-channel and p-channel gate electrodes 6 and 7. To do. Next, a second polysilicon film is formed on the semiconductor substrate 10 and patterned into a predetermined shape to form resistance elements R1, R2, R3. Then, for example, the resistance elements R1, R2, and R3 that are targets using photoresist or the like
Impurities are ion-implanted so that the region other than the above is masked and polysilicon of the resistance element obtains a predetermined sheet resistance. The second method is to form a polysilicon film on the semiconductor substrate 10 and pattern it into a predetermined shape to form n-channel and p-channel gate electrodes 6 and 7 and resistance elements R1 and R.
2 and R3 are formed at the same time. Then, as in the first method, for example, a region other than the target resistance element is masked with a photoresist or the like, and impurities are ion-implanted so that the polysilicon of the resistance element obtains a predetermined sheet resistance.
Thus, the sheet resistance can be easily set to a predetermined value by the ion implantation amount. Further, if the second method is used, part of the manufacturing process of the resistance element can be shared during the manufacturing process of the MOS transistor, so that the manufacturing process is simplified as compared with the first method.

In FIG. 9, regions other than the resistor array are
Although the configuration is the same as that of FIG. 8, the configuration of the resistance array region is different. That is, the diffusion region formed in the surface region of the semiconductor substrate 10 is used for the resistance elements R1, R2, R3 of the resistance array. The resistance elements R1, R2, and R3 have a sheet resistance of 101Ω / □ and a resistance value of 101Ω. The wiring structure and the like on the semiconductor substrate 10 are the same as those in the previous example of FIG. As described above, the resistance element uses the impurity diffusion region formed in the surface region of the semiconductor substrate. To form this resistance element on a semiconductor substrate, for example, impurities are first diffused into a predetermined surface region of the semiconductor substrate 10 using an ion implantation method or the like to form source / drain regions of n-channel and p-channel transistors. 8, 13, 9 and 12 are further formed, and a p ⁺ diffusion layer 14 for well bias is formed in the p well 11, and an n ⁺ diffusion layer 15 for substrate bias is formed on the substrate 10 side. Then, by utilizing this impurity diffusion, resistors R1, R2, and R3, which are diffusion resistors, are formed in the resistor array region of the semiconductor substrate 10. An impurity diffusion amount such as ion implantation when forming each resistance element is determined according to a desired sheet resistance value. Thus, the sheet resistance of the resistance element can be easily set to a predetermined value by the ion implantation amount.

[0022]

According to the present invention, when a plurality of products (chips) having different resistance value specifications of an electronic potentiometer are integrated into a semiconductor integrated circuit by making the layout design of the entire chip common, a resistance element forming a resistance array of the electronic potentiometer is provided. By controlling the impurity concentration and the ion implantation amount without changing the size of the resistance element when forming the semiconductor device on the semiconductor substrate, the sheet resistance of the resistance element can be controlled to a predetermined resistance value according to the resistance value resolution. As in the past, resistance elements with the highest common divisor that can satisfy the specifications of different resistance values are arranged in advance by the number of least common multiples, and the wiring connections between the arranged resistance pieces are adjusted according to the resistance value specifications. According to the present invention, a glass mask for changing the wiring connection is unnecessary compared with the case where wiring is performed by selectively using a glass mask designed as described above, and only a resistor equivalent to one conventionally used resistance piece is used. Not only can the resistance value resolution be realized, but the area occupied by the resistor array can be minimized, which is suitable for high integration.

[Brief description of drawings]

FIG. 1 is a functional block diagram of the present invention and a conventional electronic potentiometer.

FIG. 2 is a perspective view of a resistance element of the present invention and a conventional resistance element.

FIG. 3 is a schematic plan view of a semiconductor substrate on which a resistance element of the present invention and a conventional resistance element are arranged.

FIG. 4 is a schematic plan view of a semiconductor substrate on which a resistance element of the present invention and a conventional resistance element are arranged.

FIG. 5 is a schematic plan view of a semiconductor substrate on which a resistance element of the present invention and a conventional resistance element are arranged.

FIG. 6 is a schematic plan view of a semiconductor substrate on which a resistor array of the present invention is formed.

FIG. 7 is a characteristic diagram showing ion implantation dose dependency of sheet resistance in diffusion resistance.

FIG. 8 is a cross-sectional view of a semiconductor device in which a resistance array region of the present invention is formed.

FIG. 9 is a sectional view of a semiconductor device in which a resistance array region of the present invention is formed.

FIG. 10 is a circuit diagram corresponding to a resistance for one step of resistance value resolution of a conventional resistance array.

FIG. 11 is a circuit diagram corresponding to a resistance for one step of resistance value resolution of a conventional resistance array.

[Explanation of symbols]

1 ... Resistor array, 2 ... Decoder, 3.
..Transmission gates, 4 ... Field oxide films, 5.
..Gate oxide films, 6, 7 ... Gate electrodes, 8,
13 ... Source, 9, 12 ... Drain, 10
... n-type silicon semiconductor substrate, 11 ... p well,
14 ... P ⁺ diffusion layer for well bias, 15 ...
-N ⁺ diffusion layer for substrate bias, 16 ... Interlayer insulating film, 17 ... Metal wiring, 18 ... Protective insulating film.

Claims (3)

[Claims] 1. A resistance element having a semiconductor substrate and a first terminal, a second terminal and a third common terminal formed on the semiconductor substrate, the resistance element having the same resistance value between the first and second terminals. A plurality of resistor arrays connected in series are formed on the semiconductor substrate and each has one corresponding resistance element, one end of which is connected to the corresponding resistance element and the other end of which is connected to the third common terminal. A plurality of transmission gates commonly connected with the resistance element, and a decoder formed on the semiconductor substrate for decoding and generating a signal for controlling ON / OFF of each of the plurality of transmission gates in response to digital input data. , A resistance value between one of the first terminal or the second terminal and the third common terminal is set to a constant resistance value resolution by selecting an arbitrary transmission gate according to the digital input data. A variable electronic potentiometer is provided, wherein the resistance element is composed of a polysilicon resistance or a diffusion resistance formed on the semiconductor substrate, and the sheet resistance of the resistance element can be converted into a resistance value resolution of the potentiometer without changing the dimensions of the resistance element. A semiconductor device having a resistance array for an electronic potentiometer, which is controlled to a predetermined resistance value in accordance with the above. 2. A resistance array in which a semiconductor substrate is provided with a first terminal, a second terminal and a third common terminal, and a plurality of resistance elements having the same resistance value are connected in series between these first and second terminals. A plurality of resistance elements respectively corresponding to the semiconductor substrate, one end of which is connected to the corresponding resistance element, and the other end of which is commonly connected to the third common terminal together with the other resistance element. Transmission gate and a decoder for decoding and generating a signal for controlling ON / OFF of each of the plurality of transmission gates on the semiconductor substrate in correspondence with digital input data, and select an arbitrary transmission gate by the digital input data. Thereby forming an electronic potentiometer that varies the resistance value between one of the first terminal or the second terminal and the third common terminal with a constant resistance value resolution, The resistance element is composed of a polysilicon resistance or a diffusion resistance formed on the semiconductor substrate, and the sheet resistance of the resistance element is controlled by controlling the impurity concentration and the ion implantation amount without changing the dimensions of the resistance element. A method of manufacturing a semiconductor device having a resistance array for an electronic potentiometer, characterized in that the polysilicon resistance or the diffusion resistance is formed while controlling to a predetermined resistance value corresponding to a resistance value resolution. 3. A plurality of the semiconductor substrates are prepared, a plurality of resistance elements having the same size and sheet resistance are formed on each semiconductor substrate, and the resistor formed on which semiconductor substrate. 3. The semiconductor device having a resistance array for an electronic potentiometer according to claim 2, wherein all the elements have the same size, and the resistance value and the sheet resistance of the resistance element are different for each semiconductor substrate. Production method.