JPH09246274A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent short-circuiting even with lower pad pitches by forming wiring extending from pads to the surface of an insulator layer through openings formed in pad positions, and forming bumps on the surface of the insulator layer. SOLUTION: Semiconductor element are formed on an IC chip 2, and its active element surface is covered with an insulator layer 4. A SiO2 film or polyimide film is used for the insulator layer 4. Openings 6 are formed in the insulator layer 4 in the positions of pads, and wirings 8 are formed which extend from the openings 6 to the surface of the insulator layer 4, respectively. Bumps 10 are formed on the insulator layer 4 at the end of the wirings 8. The wiring 8 are formed from a conductive film obtained by laminating a Cu layer and an Au layer on a Cr layer, the lowermost layer, or a conductive film obtained by laminating a Ni layer and an Au layer on a Ti layer, the lowermost layer. This allows the bump pitch to be increased, prevents short-circuiting between bumps, and makes the semiconductor device easy to handle.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a semiconductor device,
In particular, the present invention relates to a semiconductor device in which bumps are formed on a semiconductor integrated circuit device chip for flip-chip connection.

[0002]

2. Description of the Related Art Semiconductor integrated circuit device chips (hereinafter referred to as IC
Chip), a connection pump is formed on the active element surface of the IC chip, the active elements of the IC chip are arranged toward the mounting substrate, and the bumps of the IC chip and the wiring of the mounting substrate are connected. Flip chip connection is used to connect the two. IC for flip chip connection
Solder bumps for connection are formed on the chip, and the IC chip is positioned according to the wiring of the mounting substrate, and the solder is melted for connection. The positions of the bumps are directly formed on the pads of the IC chip.

[0003]

The size of the bump is IC
The size is formed so as to cover the opening on the pad opened in the passivation film covering the surface of the chip. Since the bumps are directly formed on the pads, when the pitch of the pads becomes finer, there is a risk of short-circuiting between the bumps. Further, the finer the pitch, the more strict the positional accuracy of the bumps. Therefore, the handling is also required to be accurate when the bumps are connected to the wiring of the mounting board. The present invention suppresses the occurrence of a short circuit in an IC chip for flip-chip connection even when the pad pitch becomes finer.
The purpose is to prevent positional accuracy from being strictly required.

[0004]

In the semiconductor device of the present invention, the surface of the semiconductor integrated circuit device on which elements are formed is covered with an insulating layer, and the position of the pad of the semiconductor integrated circuit device is covered with the insulating layer. An opening is provided in the wiring, a wiring extending from the pad to the surface of the insulating layer through the opening is formed, and a bump is formed on the wiring on the surface of the insulating layer.

Since the bumps are not formed directly on the pads but on the wiring extending from the pads to the surface of the insulating layer, the entire surface of the IC chip covered with the insulating layer is arranged as bumps. It can be used as an area.
Therefore, even if the pitch of the pads becomes fine, it is possible to prevent a short circuit between the bumps.

[0006]

FIG. 1 shows an embodiment. (A) is a plan view showing a surface on which bumps are formed, and (B) is its XX ′.
It is sectional drawing in a line position. The example shows a state of being cut out for one chip. A semiconductor element is formed on the IC chip 2, and the active element surface thereof is an insulator layer 4
Covered by The insulator layer 4 may be a SiO ₂ film used as a passivation film, a polyimide film, or the like. As an example, a polyimide film having a thickness of about 10 μm is used. An opening 6 is formed in the insulating layer 4 at the position of the pad, and a wiring 8 extending from the opening 6 to the surface of the insulating layer 4 is formed. Wiring 8
A bump 10 is formed on the insulator layer 4 at the tip of the. The lowermost layer of the wiring 8 is a Cr layer, a Cu layer thereon, and a conductor layer (Cr / Cu / Au) on which an Au layer is further laminated.
Laminated film) or a conductor film (Ti / Ni / Au) in which the lowermost layer is a Ti layer, a Ni layer is formed thereon, and an Au layer is further formed thereon.
Laminated film). The bump 10 is, for example, a solder bump.

A method of manufacturing the IC chip of this embodiment will be described with reference to FIGS. FIG. 2A shows a silicon wafer 12 on which elements are formed. A large number of elements for IC chips 14 are formed on the wafer 12. An enlarged view of one IC chip 14 area is shown in FIG.
(B). A wiring 16 that serves as a pad is arranged along the periphery of one IC chip 14, for example.

FIG. 3 shows a manufacturing process of an IC chip, and shows a portion for one IC chip. The cross-sectional views of the respective steps of FIG. 3 represent the cross-sectional shape at the position of the line YY ′ in FIG. (A) On the surface of the wafer 12, the surface on which elements are formed (active element surface) is covered with the insulator layer 4. The insulator layer 4 is, for example, a polyimide film. (B) The insulator layer 14 is patterned by photolithography and etching to form holes 6 at the pad portions. (C) A conductor film is formed on the entire surface of the insulator layer 14 by a sputtering method or a vapor deposition method. The conductor film 18 is, for example, the above-mentioned Cr / Cu / Au laminated film.

(D) The conductor film 18 is patterned by photolithography and etching to form holes 6 in the pad portion.
To the surface of the insulating layer 4, and the wiring 8 having the tip as a terminal portion is formed. (E) For example, the solder bump 10 is attached to the terminal portion at the tip of the wiring 8.
To form Then, the wafer 12 is cut into individual IC chips to obtain the IC chips of the embodiment shown in FIG.

[0010]

According to the present invention, a wiring pattern extending from a pad is formed on an insulating layer covering the surface of a semiconductor integrated circuit device to provide a terminal on the insulating layer, and a bump is formed on the terminal. As a result, the entire surface of the IC chip can be used for bump placement. Therefore, the pitch of the bumps can be increased, a short circuit between the bumps can be suppressed, and the handling becomes easy.

[Brief description of drawings]

1A and 1B are views showing an embodiment, FIG. 1A is a plan view of a bump side, and FIG. 1B is a cross-sectional view taken along line XX ′.

2A and 2B are views showing a silicon wafer on which elements are formed, FIG. 2A is a schematic plan view, and FIG. 2B is a schematic plan view in which one IC chip region is enlarged.

FIG. 3 is a process cross-sectional view showing a manufacturing method of one embodiment.

[Explanation of symbols]

 2 IC chip 4 Insulator layer 6 Opening for pad 8 Wiring 10 Bump

Claims (1)

[Claims] 1. A surface of a semiconductor integrated circuit device on which elements are formed is covered with an insulating layer, and an opening is provided in the insulating layer at a position of a pad of the semiconductor integrated circuit device, and the pad is passed through the opening. A semiconductor device for flip-chip connection, in which a wiring extending from the insulating layer to the surface of the insulating layer is formed, and a bump is formed on the wiring on the surface of the insulating layer.