JPH09244596A - Display control device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal display control device which can prevent degradation and damage of LCD(liquid crystal display) without outputting abnormal display such as meaningless display and a non-display state by reset occurring in a host system side. SOLUTION: Picture data transferred from a host system 50 is stored in a data storing region 61a for normal display of a storage means 61. Data in accordance with display contents at the time of reset is previously stored in a reset time storing region 61b of the storage means 61. An address specifying means 62 specifies the leading address of the data storing region 61a for normal display at the time of non-reset as a read-out address of the picture data, at the time of reset, specifies the leading address of the reset time storing region 61b. A LCD control means 63 reads out picture data from the specified address of the storage means 61 and transfers it to a LCD 70.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control device for displaying image data sent from a host system on a display, and in particular, outputting a meaningless display to the display after a reset occurs in the host system. And a display control device capable of preventing continuous output of the same display.

[0002]

2. Description of the Related Art FIG. 11 is a block diagram showing a configuration of a general liquid crystal display system, in which image data sent from the host system 50 is placed between the host system 50 and a liquid crystal display (LCD) 70. Is connected to a liquid crystal display control device 60 for performing various controls for displaying on the LCD 70. Liquid crystal display controller 60
Includes a buffer memory 10, temporarily stores the image data sent from the host system 50 in the buffer memory 10, then reads the image data from the buffer memory 10 and transfers it to the LCD 70.

With such a configuration, when a reset occurs in the host system 50, a reset signal is sent to the host system 5.
It is also sent from 0 to the liquid crystal display control device 60, and the liquid crystal display control device 60 is also reset at the same time. At this time, the liquid crystal display control device 60 reads the image data from the buffer memory 10, and
Since the transfer to D70 can be restarted immediately after reset, L
The image data on the buffer memory 10 is immediately displayed on the CD 70.

On the other hand, in the host system 50, it may be necessary to execute initialization processing after reset. In such a case, output of image data cannot be resumed immediately, and after reset, The output of image data from the host system 50 to the liquid crystal display control device 60 may be temporarily interrupted. Therefore, the image data on the buffer memory 10 cannot be rewritten, and the LCD 7
The same image data is continuously output to 0, and as a result, there is a problem that the user feels distrust.

Further, when the liquid crystal display control device 60 is reset, the stored contents of the buffer memory 10 may be destroyed, and therefore an abnormal display due to the destroyed image data is output to the LCD 70 immediately after the reset. There was also the problem of making the user feel distrustful.

In order to solve such a problem that may occur immediately after resetting in the host system, for example, in Japanese Patent Laid-Open No. 5-341726, the buffer memory 10 is cleared immediately after resetting, or the buffer memory 1
A liquid crystal display control device has been proposed which temporarily prevents the reading of image data from 0 to prevent abnormal display immediately after resetting and continuous display of the same content.

[0007]

In the above-mentioned conventional technique, the contents stored in the buffer memory 10 are cleared immediately after resetting, or the reading of image data from the buffer memory 10 is prohibited.
For a while after the reset occurs, the LCD 70 remains in the non-display state in which nothing is displayed. For this reason,
As in the case of abnormal display, there is a problem that the user feels distrust.

A first object of the present invention is to solve the above-mentioned problems of the prior art and to prevent an abnormal display such as a meaningless display or a non-display state from being output due to a reset generated on the host system side. It is to provide a control device. A second object of the present invention is to provide a display control device capable of preventing deterioration or damage of the LCD in addition to the above first object.

[0009]

In order to solve the above-mentioned problems, the present invention is characterized in that the following means are taken. (1) A liquid crystal display for visually displaying image data, storage means for storing at least one screen of image data transferred from a host system, address designating means for designating a read address for the storage means, A display control device for reading out the image data stored in the specified address of the storage means and supplying the image data to the display;
The address designating means always designates the first address, and when detecting the reset signal output from the host system, designates the second address different from the first address. (2) Message data at the time of reset is stored in the storage area designated by the second address of the storage means. (3) Reset control means for detecting a second reset signal output from the host system at an arbitrary timing is further provided, and the reset control means resets the display control device when detecting the second reset signal. , The display drive voltage was turned off.

According to the above configuration (1), when the reset signal is output from the host system, the display shows
Image data in another storage area (second address) different from the storage area (first address) in which the image data transferred from the host system is stored is read and displayed. Therefore, for example, if the non-display image data is stored in the other storage area, meaningless display output when the reset occurs on the host system side can be prevented.

According to the above configuration (2), when a reset occurs on the host system side, a message to that effect is displayed on the display, so that the user can recognize the situation.

According to the above configuration (3), when the display control device is reset from the host system at an arbitrary timing, the drive voltage of the display is turned off and the application of the DC voltage to the display is prevented. , The display is prevented from deterioration and damage.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings. FIG. 1 is a functional block diagram of a liquid crystal display control device 60a that is an embodiment of the present invention.
The storage unit 61 stores a normal display data storage area 61 in which image data for at least one screen of the LCD 70 is stored.
A reset display data storage area 61b for storing a and display contents at reset is secured. The address designating means 62 designates different read addresses to the storage means 61 depending on the presence / absence of a reset signal sent from the host system 50. LCD control means 6
3 reads out the image data stored in the designated address of the storage means 61 and supplies it to the LCD 70.

In such a configuration, the host system 5
The image data transferred from 0 is stored in the normal display data storage area 61a of the storage means 61. Storage means 6
Data corresponding to the display contents at the time of reset is stored in advance in the reset memory area 61b of No. 1. When the address designating unit 62 detects the image data reading request from the LCD control unit 63, it designates the leading address of the normal display data storage area 61a as a reading address of the image data when the reset signal is not input and in the non-reset state. At the time of reset when the reset signal is input, the start address of the storage area at reset 61b is designated.
The LCD control means 63 reads the image data from the designated address of the storage means 61 and transfers it to the LCD 70.

As described above, according to the present invention, the host system 50
The read address of the image data to be output to the LCD 70 is changed depending on whether or not the reset has occurred, and when the reset occurs, the image data according to the display content at the time of reset is selectively read from the storage means 61. There is a feature in doing so.

Next, embodiments of the present invention will be described in detail. FIG. 2 is a block diagram of the liquid crystal display control device according to the first embodiment of the present invention. The buffer memory 10 has the function of the storage means 61, and in the storage area thereof, as shown in FIG. 5, the normal display area 10a (addresses 0000H to 077F) starting from "normal start address" is displayed.
H) and "reset start address", reset screen storage area 10b (address 0800H-0
FFFH) is secured. The normal display area 10a corresponds to the normal display data storage area 61a, and the reset screen storage area 10b corresponds to the reset display data storage area 61b.

The storage capacity of the buffer memory 10 is L
Since it is ensured to be slightly larger than the data amount for one screen of the CD 70, in the present embodiment, the empty area of the buffer memory 10 is used as the screen storage area at reset 10b,
The display message at the time of reset is stored in advance in this empty area. In addition, the buffer memory 10
Since the storage capacity of the empty area is less than the amount of data for one screen of the LCD 70, the empty area is, for example, the LCD 7
Only the upper half image data of 0 can be stored.
However, if a message for resetting only half a screen is stored in this empty area, the buffer 10 is idled for the remaining half screen, so the LCD
On the screen 70, as shown in FIG. 6, a message is displayed in the upper half and the image data for non-display is read in the lower half, so that the user does not feel uncomfortable.

The buffer memory arbitration circuit 20 designates either the system 50 or the LCD control circuit 40 as a target for permitting access to the buffer memory 10, and normally permits access to the system 50. When a negative logic access request (DTMG) signal is output from the LCD control circuit 40, the access right is transferred from the system 50 to the LCD control circuit 40. The LCD control circuit 40 sends out a DTMG signal and outputs the DTMG signal to the buffer memory 10.
The access signal to the buffer memory 10 and the address signal (A0 to A11) of the buffer memory 10 and the read signal (hereinafter, the control signals such as the read signal and the write signal are collectively referred to as a buffer control signal) to be sent to the buffer. Image data is received from the memory 10. Of the address signals (A0 to A11) of the buffer memory 10, only the most significant bit data A11 is sent to the address control circuit 30, and the remaining bit data A0 to A10 is sent to the buffer memory arbitration circuit 20.

When the address control circuit 30 receives the most significant bit data A11 of the address signal from the LCD control circuit 40, the address control circuit 30 reads the image data from the buffer memory 10 according to whether the reset signal is being output or not. Start address 0000H (normal start address) of normal display area 10a or screen storage area 10b at reset
Of the top address 0800H (start address at reset) is selectively designated, the most significant bit data A11 (for example, "0") is unchanged (when not reset) or converted to "1" ( At the time of reset), this is output as the most significant bit data A11 '.

FIG. 3 is a diagram showing an example of a specific configuration of the address control circuit 30, which is a D-flip-flop (FF) 31, an SR latch 32, and a NAND gate 3.
3 and an inverter 34. FIG. 4 is a diagram showing signal waveforms of its main part.

The host system 5 is connected to the D terminal of the D-FF 31.
A system reset signal is input from 0, and a sampling clock is input to the clock terminal. D-FF31
Q output of is input to the set terminal S of the SR latch 32,
A reset display cancellation signal is input to the reset terminal R. The inverted Q output of the SR latch 32 is the NAND gate 3
The most significant bit data signal A11 of the address signal is inputted from the LCD control circuit 40 to the other input terminal of the NAND gate 33 via the inverter 34. Since the output of the NAND gate 33 is input to the buffer memory arbitration circuit 20 as the most significant bit data A11 ', the address signals A0 to A11 output from the LCD control circuit 40 are the address signals A0 to A10,
It is input to the buffer memory arbitration circuit 20 as A11 '.

In such a configuration, since the most significant bit data A11 is "0" and the inverted Q output of the SR latch 32 is "1" when not reset, the most significant bit data A11 'output from the NAND gate 33 is "1". It becomes 0 ". Therefore, the image data is read out from the buffer memory
It will start from address 0000. On the other hand, when the system is reset at time t1, the SR latch 32 is set at the next rising timing t2 of the sampling clock, and the inverted Q output thereof transits to "L" level. As a result, the most significant bit data A11 'output from the NAND gate 33 becomes "1", and the reading of the image data starts from the address 0800 of the buffer memory 10 this time. That is, when the image data is read out, 0000 of the buffer memory 10 when not reset.
It will be started from the address, and at reset, it will be started from the address 0800.

FIG. 7 is a block diagram of a second embodiment of the present invention, in which the same symbols as those used above represent the same or equivalent portions. In the present embodiment, the address control circuit 30a is connected between the buffer memory arbitration circuit 20 and the buffer memory 10, and the image data transmitted from the host system 50 is displayed in the normal display area 10 even when reset.
LCD control circuit 4 in order to be written to a.
The address control circuit 30a is made to function only while the DTMG signal is transmitted from 0.

FIG. 8 is a diagram showing an example of a specific configuration of the address control circuit 30a, and the same reference numerals as those used above represent the same or equivalent portions. Comparing the configuration of FIG. 8 with the configuration of the address control circuit 30 described with reference to FIG. 3, the inverted Q output of the SR latch 32 has an OR gate circuit 35 whose opening and closing is controlled by a DTMG signal output from the LCD control circuit 40. It is different in that it is inputted to one of the input terminals of the NAND gate 33 via the NAND gate 33.

In such a configuration, the LCD control circuit 40
Is output the negative logic DTMG signal, the OR gate circuit 35 is enabled and the SR latch 32 is turned on.
The inverted Q output of is input to the NAND gate 33. Therefore, if the DTMG signal is output ("L" level) while the reset signal is output ("L" level), the most significant bit A11 ("0") is converted to "1" and output. Therefore, it functions similarly to the first embodiment. If the DTMG signal is not output from the LCD control circuit 40, the most significant bit A11 'is A11 ("0").
Therefore, the image data sent from the host system 50 is written in the normal display area 10a.

In the first and second embodiments, the host system 50 may try to reset the LCD control circuit 40 directly. When such a reset is performed on the LCD control circuit 40, the LCD drive power supply outputs L
A DC voltage is applied to the CD 70, and the LCD 7
0 may be deteriorated or damaged. The third embodiment attempts to solve this, and will be described with reference to the block diagram of FIG. The same reference numerals as those used in the drawings represent the same or equivalent parts.

In this embodiment, in order that the host system 50 can reset the LCD control circuit 40 at an arbitrary timing, the LCD control circuit 40 is reset by detecting an arbitrary reset signal output from the host system 50. The feature is that the reset control circuit 100 is provided. Then, in this embodiment, when the LCD control circuit 40 is reset, the LCD drive power supply is also turned off at the same time in order to prevent the application of the DC voltage to the LCD 70.

FIG. 10 is a diagram showing an example of a specific configuration of the reset control circuit 100, and the AND gate 3
6 and the SR latch 37. AN
The host system 50 is connected to one input terminal of the D gate 36.
The power-on reset signal output from is input, and the arbitrary reset signal is input to the other input terminal. AN
The output signal of the D gate 36 is input to the reset terminal of the LCD control circuit 40 and the set terminal S of the SR latch 37. The LCD power-on signal is input to the reset terminal R of the SR latch 37, and its inverted Q output is L.
It is an ON / OFF switching signal for the CD drive power supply 110. Therefore, when the host system 50 resets the LCD control circuit 40, the LCD drive power supply 110 is turned off and the application of the DC voltage to the LCD 70 is prevented.

According to the present embodiment, the host system can reset the LCD control circuit 40 at an arbitrary timing, and at that time, the output voltage of the LCD drive power supply 110 is turned off and the DC voltage to the LCD 70 is reduced. Since the application is prevented, the LCD 70 is prevented from being deteriorated or damaged.

[0030]

According to the present invention, the following effects are achieved. (1) According to the invention of claim 1, when the reset signal is output from the host system, the liquid crystal display is stored in another storage area different from the storage area in which the original image data is stored. The image data is read and displayed. Therefore, for example, if non-display image data is stored in the other storage area, meaningless output to the liquid crystal display when a reset occurs on the host system side can be prevented. (2) According to the invention of claim 2, when a reset occurs on the host system side, a message to that effect is displayed on the liquid crystal display, so that the user can recognize the situation. (3) According to the invention of claim 3, in addition to the effect of the invention of claim 1, when the display control device is reset from the host system at an arbitrary timing, the drive voltage of the liquid crystal display is turned off and the liquid crystal is displayed. Since the direct current voltage is prevented from being applied to the display, deterioration or damage of the liquid crystal display is prevented.

[Brief description of drawings]

FIG. 1 is a functional block diagram of the present invention.

FIG. 2 is a block diagram of the first embodiment of the present invention.

FIG. 3 is a detailed block diagram of the address control circuit of FIG.

FIG. 4 is a signal waveform diagram of a main part of FIG.

FIG. 5 is a diagram schematically showing stored contents of a buffer 10.

FIG. 6 is a diagram showing a display example on the LCD at the time of reset.

FIG. 7 is a block diagram of a second embodiment of the present invention.

FIG. 8 is a detailed block diagram of the address control circuit of FIG.

FIG. 9 is a block diagram of a third embodiment of the present invention.

FIG. 10 is a detailed block diagram of the reset control circuit of FIG.

FIG. 11 is a block diagram of the related art.

[Explanation of symbols]

10 ... Buffer memory, 20 ... Buffer memory arbitration circuit, 30 ... Address control circuit, 40 ... LCD control circuit,
50 ... Host system, 60a ... Liquid crystal display control device, 61 ... Storage means, 61a ... Normal display data storage area, 61b ... Reset display data storage area, 62 ...
Addressing means, 63 ... LCD control means, 70 ... LC
D

Claims (3)

[Claims] 1. A display for visually displaying image data, and at least one of image data transferred from a host system.
Storage means for storing screen portions; address designating means for designating a read address for the storage means; and a display control device for reading out image data stored at the designated address of the storage means and supplying the display data to a display. The address specifying means always specifies the first address, and specifies a second address different from the first address when a reset signal output from the host system is detected. Display controller. 2. The display control according to claim 1, wherein the storage area designated by the second address of the storage means stores message data displayed on the display at reset. apparatus. 3. A reset control means for detecting a second reset signal output from the host system at an arbitrary timing is further provided, and the reset control means causes the display control device to operate when the second reset signal is detected. The display driving voltage is turned off at the same time as resetting.
Alternatively, the display control device according to item 2.