JPH11344962A - Display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable preventing erroneous rewriting of data in a memory circuit which can be rewritten from a personal computer(PC) side. SOLUTION: In a display device 2, video reproduction is performed by a video signal PS supplied from a PC1 in a display device 8, also a memory 10 in which data such as specification of the display device 2 is stored is directly connected with the PC1 through a communication interface 3, writing and reading data can be performed directly from the PC1. When writing request is performed from the PC1 through the communication interface, a CPU 5 controls an erroneous writing preventing circuit 9 and makes the memory 10 a into enabling state of writing data, when writing finish request is performed from the PC1, the CPU 5 controls the erroneous writing preventing circuit 9 and makes the memory 10 an into prohibited state of writing data. These request are generated by means and technique which cannot be used by a user.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processing device in general, and more particularly to a display device used for a computer terminal or the like and having a communication function with a personal computer (hereinafter, referred to as a PC) or a workstation. .

[0002]

2. Description of the Related Art Japanese Unexamined Patent Publication No. 7-302068 discloses a display device in a display system having a communication function with a computer.

A memory as a non-volatile storage device is mounted on the display device, and a control code relating to “height, width and luminance of visual output” in the display device is stored in the memory in advance. . In addition, an identification code for enabling the computer to identify the specifications of the display device is stored in the memory device in advance, and the information is read out by the display system as needed, and transmitted to the computer by communication via an interface. Can be The computer recognizes this information, and based on this information, can control the display device and recognize what peripheral device is connected.

By providing such a function, in this display system, it is possible to omit troublesome screen adjustments performed by the user when using the display device, such as horizontal and vertical display positions and display sizes. I have.

[0005]

By the way, in the above-mentioned prior art, a device external to the display device, that is, a device which can be directly rewritten from a PC, is used as a memory for storing data such as the control code and the identification code as described above. For example, it is possible to store the above data immediately before shipment of a product, or to add or change the above data for addition or change of the function of the display device after shipment. It is possible to make it possible. However, in such a case, since the memory is directly connected to the PC, the user may erroneously perform the writing operation of the memory on the PC. The data in the memory may be easily rewritten.

When the power of the display device is turned off while the power source of the PC is turned on, a signal current is drawn to the display device via a communication interface with the PC, and the peripheral device connected to the same interface is connected to the display device. There is also a possibility that communication may be disabled or a failure may occur in the drive circuit of the interface on the PC side.

An object of the present invention is to provide a display device which can solve such a problem and can prevent inadvertent rewriting of data in a memory device.

Another object of the present invention is to enable communication between peripheral devices connected to the same interface even when the power supply is cut off, thereby preventing the interface on the PC side from affecting the drive circuit. It is an object of the present invention to provide a display device as described above.

[0009]

In order to achieve the above object, the present invention provides a video processing circuit to which R, G, B video signals are inputted, and a display based on an output signal of the video processing circuit. Display device, a drive circuit for driving the display device based on a synchronization signal input together with the video signal, a CPU for controlling the video processing circuit and the drive circuit, and a memory circuit directly accessible from an external computer Which is provided with rewrite prevention means for controlling write inhibition / permission of the memory circuit.

According to another aspect of the present invention, there is provided a video processing circuit to which R, G, and B video signals are input, and a display device that performs display based on an output signal of the video processing circuit. A drive circuit for driving the display device based on a synchronization signal input together with the video signal, controlling the video processing circuit and the drive circuit, and further controlling communication of a video signal and a synchronization signal with an external PC. Is provided with a CPU having a different interface, and further provided with a switch circuit that opens and closes in accordance with the power on / off of the CPU on a path of the interface between the CPU and an external PC. .

[0011]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a first embodiment of a display device according to the present invention, wherein 1 denotes P
C, 2 a display device of this embodiment, 3 a communication interface, 4 a synchronous processing circuit, 5 a CPU, 6 a drive circuit, 7 a video processing circuit, 8 a display device, 9 an erroneous rewrite prevention circuit, 10 Is a memory, and 11 is a control data memory.

In FIG. 1, in the display device 2,
R, G, B video signal PS and composite synchronization signal C from PC1
S is supplied to the video signal PS by the synchronization processing circuit 4.
And a horizontal synchronizing signal HS and a vertical synchronizing signal VS. The video signal PS is supplied to the video processing circuit 7, and the horizontal synchronizing signal HS and the vertical synchronizing signal VS are supplied to the CPU 5 and the drive circuit 6.

When the PC 1 outputs the horizontal synchronizing signal HS and the vertical synchronizing signal VS in a form separated from the video signal PS in advance, the synchronizing processing circuit 4
The polarity information of S and VS may be detected and supplied to the CPU 5.

The CPU 5 specifies an input signal from the frequencies of the horizontal synchronization signal HS and the vertical synchronization signal VS supplied from the synchronization processing circuit 4 and the above-mentioned polarity information, and determines the brightness, color, and display size of the display screen based on the video signal PS. , Display position, distortion and other control data from the control data memory 11,
The video processing circuit 7 and the drive circuit 6 are controlled.

Here, the control data memory 11 is shown as being separate from the CPU 5, but the present invention is not limited to this.
As 1, a built-in ROM of the CPU 5 may be used. Also,
The capacity of the memory 10 may be expanded, and a part thereof may be used as the control data memory 11.

R, G, B output from the synchronization processing circuit 4
The video signal PS of the video processing circuit 7
Signal processing such as amplification and level shift is performed on the basis of the control information from 5 and supplied to the display device 8. The display device 8 is driven by a drive circuit 6 to which the synchronization signals HS and VS are supplied from the synchronization processing circuit 4 and control information from the CPU 5, respectively, and the display size and distortion are controlled. .

By operating the respective parts as described above, an image (video, text, etc.) based on the input video signal PS is displayed on the display device 8. The display device 8 may be a CRT system, a liquid crystal system, or a plasma system, and may be any device that can display images, characters, and the like.

A rewritable device is used as the memory 10, which stores display specification information such as a name of a maker and a model of the display device 2 and a corresponding signal frequency. A part or all of the recorded information is transferred to the communication interface 3
Can be transmitted to the PC 1 via the. Here, even if the communication interface 3 is a serial transmission system,
Although it may be a parallel transmission system, a clock synchronous transmission system, or a differential transmission system, here,
The description will be made assuming that the interface is a clock synchronous serial communication interface.

By operating each part as described above,
The PC 1 outputs the video signal PS at the highest resolution that can be displayed by the display device 2, and can automatically perform image display under optimum conditions without bothering the user. Further, the display device 2 is provided with an erroneous rewrite prevention circuit 9 so that the PC 1 does not erroneously rewrite data in the memory 10.

FIG. 2 is a block diagram showing a specific example of such an erroneous rewrite prevention circuit 9. In FIG.
Reference numerals 9b to 9d denote resistors, reference numerals 12 and 13 denote power supplies, and portions corresponding to those in FIG.

In FIG. 1, as the memory 10, a device having a control terminal WP for prohibiting / permitting writing to a memory array therein is used. Although the control specification of the control terminal WP of the memory 10 differs depending on the device, it is assumed here that writing is prohibited at “L” (low level).

Here, the control terminal WE of the CPU 5
Output a signal for controlling write inhibition / permission of memory 10 (write inhibition / permission (WE) signal). When the power supply voltages of the memory 10 and the CPU 5 are equal, the control terminal WP of the memory 10 may be directly controlled by the WE signal of the CPU 5, but here, the power supply voltages of the memory 10 and the CPU 5 are different from each other. I do. Therefore, memory 1
0 is supplied with the power supply voltage E ₁ from the power supply 12, and the CPU 5 is supplied with the power supply voltage E ₂ from the power supply 13.
These power supply voltages E ₁ and E ₂ are different, and here, E ₁ <E ₂
And

The erroneous rewrite prevention circuit 9 is composed of a transistor 9a and resistors 9b to 9d.
These form a level shift circuit. That is, the erroneous rewrite prevention circuit 9 is constituted by a level shift circuit.

The operation of this embodiment will be described below.

In this specific example, writing to the memory 10 is permitted by a data write request command from the PC 1 (FIG. 1), and data writing to the memory 10 is prohibited by a command from the PC 1 indicating completion of data writing. Things. Here, the data write request or the data write end command is performed, for example, by performing a special operation on the PC 1 that the user does not perform, or
It is output from the PC 1 by connecting a special device to C1 and operating this device, etc., and shall not be generated by the operation of the user.

When such a write request command to the memory 10 is supplied from the PC 1 to the memory 10 via the communication interface 3, the CPU 5 receives this command and outputs "H" (high level) WE (write inhibit / write) from the control terminal WE. Output) signal. In the erroneous rewrite prevention circuit 9, the "H" W
The E signal is divided by the resistor 9c and the resistor 9d, and
Level down to a voltage level that can be supplied to
The buffered signal is supplied to the control terminal WP of the memory 10 by being buffered by an emitter follower circuit composed of the transistor b and the transistor 9a. The memory 10 is enabled to write when the signal “H” is applied to the control terminal WP, so that the data supplied through the interface 3 can be written.

When the data writing in the memory 10 is completed in this way, the CP
The above command indicating the end of data writing is transmitted to U5. As a result, the CPU 5 sends the “L” W signal from the control terminal WE in order to prohibit data writing to the memory 10.
Outputs the E signal. Therefore, the erroneous rewrite prevention circuit 9 processes the WE signal as described above and supplies the WE signal to the control terminal WP of the memory 10. Thereby, the control terminal W
An “L” signal is supplied to P, and the memory 10 is set in a write-protected state.

In this manner, data can be written in the memory 10 and inadvertent rewriting of internal data in the memory 10 can be prevented.

The memory 1 is always in the initial state of the CPU 5.
0 may be set to the write-protected state. In this case, the power of the display device 2 is temporarily turned off once the data writing is completed, and then the power-on reset for immediately turning on the power is automatically performed. C
PU5 is always in the initial state and is set to the write-inhibited state.

Here, when the input impedance of the control terminal WP of the memory 10 is sufficiently larger than the resistance resistors 9c and 9d, the emitter follower composed of the resistance 9b and the transistor 9a may be omitted. At this time, it is necessary to adjust the voltage dividing ratio of the resistors 9c and 9d in consideration of the voltage drop due to the base-emitter voltage V _BE of the transistor 9a.

In the present embodiment, the CPU 5 receives a message from the PC 1 via the communication interface 3 as a trigger to permit writing to the memory 10.
Although the writing of the memory 10 is permitted by the write request command to the memory 10, the present invention is not limited to this. For example, the writing of the memory 10 is permitted at a location that cannot be easily controlled by the user, such as inside the circuit board. A switch may be provided to operate the switch at the time of initial adjustment at a factory, or a combination of operation keys of the display device 2 may be used (for example, a bright key and a contrast key may be used). It may be triggered by pressing a specific operation key within a certain period of time after the power is turned on. Alternatively, a communication interface different from the communication interface 3 of the display device 2 may be used. A write request command or data to be written to the memory 10 is transmitted through the It may be written through.

FIG. 3 is a block diagram showing a specific example of the erroneous rewrite prevention circuit 9 in the display apparatus according to the second embodiment of the present invention. In FIG. 3, reference numeral 9e denotes an AND gate. Have the same reference numerals.

The erroneous rewrite prevention circuit 9 shown in FIG. 2 is used for a memory 10 having a dedicated control terminal WP for prohibiting / permitting writing to an internal memory array. The erroneous rewrite prevention circuit 9 shown in FIG. 1 is a memory 1 in which the control terminal WP is also used for other signals.
This is the case where 0 is used. Here, it is assumed that the control terminal WP of the memory 10 is also used as, for example, the input terminal of the vertical synchronization signal VS.

In this case, the display device (ie, the second
Has a configuration similar to that of the display apparatus 2 shown in FIG. 1, but includes a first communication mode in which data transmission is performed in synchronization with the vertical synchronization signal VS, and a communication mode supplied from the communication interface 3. The memory 10 shown in FIG. 3 is used in the second embodiment, which corresponds to two communication modes including a second communication mode in which data transmission is performed in synchronization with a clock. In the second embodiment, the memory 10 is set in a data write permission or data write inhibition state depending on whether the communication mode is the first communication mode or the second communication mode.

The memory 10 uses the control terminal WP as an input terminal of the vertical synchronizing signal VS in the first communication mode, and operates in the same manner as the memory 10 shown in FIG. 2 in the second communication mode. Used as a control terminal WP of a control signal WE for prohibiting / permitting data writing to the inside. Therefore, in order to support the first and second communication modes, P
According to the communication mode of C1, when PC1 is in the first communication mode, the vertical synchronization signal VS is inputted to the control terminal WP of the memory 10, and when in the second communication mode, the control terminal WP is set to "L". "

Therefore, the CPU 5 may monitor the communication mode of the PC 1 and directly control the control terminal WP of the memory 10 by the WE signal from the control terminal WE as described above. In order to make the display device in this case compatible with the above two communication modes, P
An erroneous rewrite prevention circuit that controls the control terminal WP of the memory 10 according to the communication mode of C1 is used.

In FIG. 3, an erroneous rewrite prevention circuit 9 is such an erroneous rewrite prevention circuit, and is a two-input one-output AN.
The input is a vertical synchronizing signal VS, the other input is a control signal WE from the CPU 5, and the output is connected to a control terminal WP of the memory 10.

The CPU 5 monitors the communication mode of the PC 1 (FIG. 1), and in the case of the first communication mode, sets the WE signal from the control terminal WE to "H". As a result, the output of the AND gate 9e of the erroneous rewrite prevention circuit 9 becomes the vertical synchronizing signal VS, which is transmitted to the memory 10 via its control terminal WP.
Supplied from The memory 10 can write and read data in synchronization with the supplied vertical synchronization signal VS.

On the other hand, when the CPU 5 detects that the communication mode of the PC 1 has shifted to the second communication mode, the WE
The signal becomes "L", and the output signal of AND gate 9e is also fixed at "L". Therefore, the memory 10 is set in a write-protected state.

In the second embodiment, usually, the second communication mode is set, so that careless writing of data in the memory 10 cannot be performed.
In the case of performing the data writing in the first mode, the first communication mode can be set by a method that cannot be performed by the user as in the first embodiment.

As described above, the display device in this case can set the data write inhibition / permission in the memory 10 in accordance with the two communication modes.

In this case, the AND gate 9e is used for the erroneous rewrite prevention circuit 9. However, the present invention is not limited to this. For example, one input is used as the vertical synchronizing signal VS,
A two-input one-output switch whose other input is a fixed signal of "L" may be used, and this switch may be controlled to be switched by the control of the CPU 5 in accordance with the above-described communication mode. May be used,
Further, multiple gates may be used. That is, as long as the vertical synchronization signal VS and the signal of "L" can be selected and supplied to the control terminal WP of the memory 10 according to the communication mode, the configuration of the erroneous rewrite prevention circuit 9 is as follows. Is also good.

FIG. 4 is a block diagram showing a main part of a third embodiment of the display device according to the present invention.
9g is a resistor, 14a and 14b are diodes, and portions corresponding to FIGS. 1 and 2 are denoted by the same reference numerals.

In the third embodiment, in the third embodiment, the erroneous rewriting prevention circuit 9 controls the control terminal WP of the memory 10 in accordance with the presence or absence of a power supply voltage of about +5 V from the PC 1. is there.

P having a communication function with the display device
As C, there is one having a specification for supplying a voltage of about +5 V as a power supply voltage for peripheral devices connected to the same interface. In the third embodiment, such P
C, the erroneous rewrite prevention circuit 9 detects the presence or absence of the supply of the power supply voltage of about +5 V to the PC 1 to determine whether or not the PC 1 has a communication function with the display device 2, and the control terminal WP of the memory 10. Is controlled.

Here, the erroneous rewrite prevention circuit 9 is provided with a resistor 9
f, 9g and a transistor 9a.
A power supply voltage of about +5 V from C1 is applied to the base of a transistor 9a via a resistor 9g.
A so-called inverter circuit for supplying the collector output of a to the control terminal WP of the memory 10 is formed. In addition, the power supply voltage output terminal of +5 V of PC1 is a forward diode 14a.
And the power supply 12 is connected to a forward diode 14b.
Are connected to the same terminal of the resistor 9f, and the other terminal of the resistor 9f is connected to the collector of the transistor 9a. And this collector is the memory 10
Is connected to the control terminal WP. The power supply 12
Power supply voltage E ₁ (where, E _1> + about 5V) is also supplied to the power supply terminal V _DD of the memory 10 through the diode 14b.

In the erroneous rewrite prevention circuit 9 having such a configuration, when the power supply voltage of about +5 V is not supplied from the PC1, the transistor 9a is turned off.
Transistor 9a with the power supply voltage E ₁ from the power supply 12
Becomes "H", and data writing to the memory 10 is possible. When a power supply voltage of about +5 V is supplied from PC1, transistor 9a is turned on and its collector output becomes "L", and memory 10 is turned on.
Writing data to the memory is prohibited. Therefore, depending on whether or not the power supply voltage of about +5 V is supplied to the PC 1, the memory 10
It is possible to control the prohibition / permission of writing data to the memory.

Even when the power supply of the display device 2 is turned off and the power supply voltage E ₁ is not supplied to the memory 10, when the power supply voltage of about +5 V is supplied from the PC 1, this power supply voltage causes the diode 14 a to operate. _Is supplied to the power supply terminal _VDD of the memory 10 via the
0 indicates that data can be read. However, since the transistor 9a is on, the memory 10 is in a data write-inhibited state. Therefore, even if the display device 2 is not powered on, the PC 1
Is connected via the communication interface 3, so that data can be read from the memory 10, and it can be always recognized which device is connected.

FIG. 5 is a block diagram showing a fourth embodiment of the display device according to the present invention. Reference numeral 15 denotes a switch circuit, and portions corresponding to those in FIG. I do.

In the same figure, the fourth embodiment has a C
A switch circuit 15 is provided before PU5,
Other configurations are the same as those of the embodiment shown in FIG.

The switch circuit 15 is connected to the display device 2
When the display device 2 is powered on, the communication interface 3 is connected to the CPU 5 to enable communication between the PC 1 and the CPU 5. When the power of the display device 2 is turned off, the communication interface 3 is electrically disconnected from the CPU 5.

As described above, when the power of the display device 2 is turned off, the CPU 5 does not draw out the signal current from the communication interface 3 and does not cause any trouble to the interface driving circuit of the PC 1.

FIG. 6 is a block diagram showing a specific example of the switch circuit 15 in FIG.
-FET, 17 is a clock line, 18 is a data line, and portions corresponding to those in FIG.

In the figure, the switch circuit 15 is composed of two n-channel MOS-FETs 16a and 16b. The drain terminal D is provided on the PC1 side, the source terminal S is provided on the CPU5 side, and the CPU5 is provided on the gate terminal G. Power supply 13
Are connected respectively.

In the switch circuit 15 having such a configuration,
The power supply voltage E from the power supply 13 of the CPU 5 is supplied to the switch circuit 15.
₂ is supplied, that is, when the display device 2 is powered on, the MOS-FET 1
6a, since this voltage voltage E ₂ to the gate of 16b is applied, these MOS-FET 16a, 16b drain of - between the source becomes low impedance, PC1 clock line 1 of the communication interface 3 from (FIG. 5)
7, the data line 18 is a clock terminal of the CPU 5,
PC1 and CPU5 are connected to the data terminals.
Communication with the server.

When the power supply of the display device 2 is cut off, no power supply voltage is applied to the gates of the MOS-FETs 16a and 16b.
The impedance between the drain and the source of 6a and 16b becomes high impedance, and the clock line 17 and the data line 18 are electrically disconnected from the clock terminal and the data terminal of the CPU 5, respectively. Therefore, even if the power supply of the display device 2 is turned off, the CPU 5 does not draw out the signal current from the clock line 17 or the data line 18 and does not cause any trouble to the interface driving circuit of the PC 1.

In this embodiment, the switch circuit 1
5, an n-channel MOS-FET is used, but the present invention is not limited to this.
It is sufficient that the clock line 17 and the data line 18 of the PU 5 can be electrically disconnected.

FIG. 7 is a block diagram showing another specific example of the switch circuit 15 in FIG. 5, where 19 is an analog switch, 20a to 20d are clamp diodes, and 21a to 2d.
1d is a switch element, 22 is a bypass capacitor, and portions corresponding to FIG. 6 are denoted by the same reference numerals.

In the figure, here, the switch circuit 1
For example, an analog switch 19 such as HD14066B is used as 9.

The analog switch 19 has four switch elements 21a to 21d incorporated in the same package, and two of them (here, the switch element 21
c, 21d) to the clock line 17 and the data line 18
It is used to connect and cut off the clock terminal and the data terminal of the CPU 5. Note that the remaining two switch elements (in this case, the switch elements 21a and 21b) are connected to the horizontal synchronization signal H.
S, can be used for communication of the vertical synchronization signal VS.

[0061] When the display device 2 (FIG. 5) to have power is supplied the power supply voltage E ₁ from the power source 12 is supplied, and switching element 21a~21d is turned on,
Thereby, the clock line 17 and the data line 18 are connected to the clock terminal and the data terminal of the CPU 5, respectively.
Communication between the PC 1 and the CPU 5 becomes possible. In this case, the clock line 17, a clock of the data line 18, data is clamp diode 20c, is clamped to the respective power supply voltage E ₁ by 20d, level variation is removed by IC
The input unit of the CPU 5 is protected.

[0062] When the power supply voltage E ₁ from blocked off the display device 2 is power source 12 is not supplied, the switch element 21a~21d is turned off, thereby, the clock line 17, data line 18 respectively CPU5 clock terminal , Are electrically disconnected from the data terminals. Thereby, the same effect as that of the specific example shown in FIG. 6 can be obtained. In this case, if the switch elements 21a and 21b are used for the synchronization signals HS and VS, these synchronization signals H
S and VS are also cut off at the same time.

Here, the power supply terminal V _DD of the memory 10
The power supply 12 may be simply connected, but the PC 1
If there is sufficient room to the signal current interface driving circuit side is a power source 12 for supplying a power supply voltage E ₁ via the bypass capacitor 22 is grounded, the memory 10 between the power source 12 and the bypass capacitor 22 Power supply terminal V
_It may be configured to connect to _DD . According to this, power supply 1
Even from 2 not supplied the power supply voltage E _2, the communication interface from PC1 3 and clamp diodes 20c, 2
The bypass capacitor 22 can be charged via Od, and the memory 10 can be operated at the charged voltage. Of course, when the display device 2 is powered on, the power supply voltage E ₁ is supplied from the power supply 12 to the power supply terminal V _DD of the memory 10.

As described above, in this specific example, even if the power supply 13 of the display device 2 is turned off, the PC 1 can read data from the memory 10.

When the power is not supplied to the display device 2, the control terminal WP of the memory 10 as shown in FIG. 4 is connected to the ground potential through a resistor (not shown). By "L" input), writing of data from the memory 10 is prohibited, whereby the storage contents of the memory 10 can be protected. This is the same for the specific example shown in FIG.

Although the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments, and the above embodiments can be appropriately combined. In addition, as the display device 8, CR
It is not limited to T, but may be a matrix type such as liquid crystal or plasma.

[0067]

As described above, according to the present invention,
Erroneous rewriting of data in the memory can be prevented.

Further, according to the present invention, even if the power supply is cut off, communication between other peripheral devices connected to the same interface is not disabled, and a failure in the interface drive circuit of the PC is prevented. To make things possible.

Further, according to the present invention, even when the power is turned off, data can be read from the memory from the PC, and the specification information of the display can be read.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a display device according to the present invention.

FIG. 2 is a block diagram showing a specific example of an erroneous rewrite prevention circuit in FIG. 1;

FIG. 3 is a configuration diagram illustrating a specific example of an erroneous rewrite prevention circuit in a second embodiment of the display device according to the present invention.

FIG. 4 is a configuration diagram showing a main part of a third embodiment of the display device according to the present invention.

FIG. 5 is a block diagram illustrating a display device according to a fourth embodiment of the present invention;

FIG. 6 is a configuration diagram showing a specific example of a switch circuit in FIG. 5;

FIG. 7 is a configuration diagram illustrating another specific example of the switch circuit in FIG. 5;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 PC 2 Display apparatus 3 Communication interface 4 Synchronization processing circuit 5 CPU 6 Drive circuit 7 Video processing circuit 8 Display device 9 Erroneous rewrite prevention circuit 10 Memory circuit 11 Control data memory 12, 13 Power supply 15 Switch circuit 17 Clock line 18 Data line 19 Analog switch

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Kazufumi Kikuchi 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Pref.

Claims (10)

[Claims] 1. A video processing circuit to which video signals of R, G, and B are input, a display device that performs display based on an output signal of the video processing circuit, and a synchronizing signal input together with the video signal. A display device having a drive circuit for driving the display device, a CPU for controlling the video processing circuit, and a memory circuit directly accessible from an external computer. A display device provided with a rewrite preventing means for controlling the display. 2. The memory circuit according to claim 1, wherein the memory circuit has a write-inhibit / permit control terminal for prohibiting or permitting write, and the rewrite-prevention means is configured to control the memory circuit in accordance with an instruction from the CPU. A display device for controlling the write prohibition / permission control terminal. 3. The level change circuit according to claim 2, wherein the rewrite prevention means includes a level shift circuit for converting a level of a write inhibit / permit signal of the memory circuit output from the CPU. A display device, wherein the write inhibit / permit control terminal of the memory circuit is controlled by an output signal. 4. The memory circuit according to claim 2, wherein the rewrite preventing means is configured to control the memory circuit based on the write inhibit / permit signal of the memory circuit output from the CPU and the synchronization signal input. A display device for controlling the write inhibit / permission terminal. 5. The memory circuit according to claim 1, wherein the memory circuit has a write prohibition / permission control terminal for prohibiting or permitting the writing, and the rewrite preventing unit outputs the video signal and the synchronization signal. A display device for controlling the write inhibit / permission control terminal of the memory circuit in accordance with the presence or absence of a power supply voltage supplied from a computer or a video signal output source. 6. The display device according to claim 5, wherein said rewrite preventing means inhibits writing in said memory circuit when a power supply voltage is supplied from said computer or said video signal output source. 7. The memory device according to claim 1, wherein at least one signal input terminal of the memory circuit and at least one power supply input terminal of the memory circuit are provided.
A display device, comprising: means for bypassing current in a direction from the signal input terminal to the power input terminal. 8. The display device according to claim 7, wherein the means for bypassing the current is a diode. 9. A video processing circuit to which R, G, B video signals are input, a display device for displaying based on an output signal of the video processing circuit, and a synchronizing signal input together with the video signal. Display device, comprising: a drive circuit for driving the display device; and a CPU having an interface different from the video signal and the synchronization signal for controlling the video processing circuit and the drive circuit and communicating with an external computer. 3. The display device according to claim 1, further comprising a switch circuit that opens and closes in response to power on / off of the CPU in a path of an interface between the CPU and the external computer. 10. The switch circuit according to claim 9, wherein the switch circuit is closed when the power of the CPU is on, and is open when the power of the CPU is off. Display device.