JPH09244576A - Image processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make up a deficiency of a difference of luminance of a pixel positioned in a left upward part of a display screen and to eliminate unevenness of luminance of this part so as to improve picture quality by adding an error data of a pixel of the last display line of the previous frame of the display image to an error data of a pixel of the 1st display line of the present frame. SOLUTION: An error diffusion ending pulse is generated when an error of the last pixel of the last line of the previous frame is calculated out. When the error diffusion ending pulse is changed from an 'H' level to an 'L' level, an output of an adder 23 is set in a latch circuit 31. Consequently, the error of the last pixel of the previous frame can be given as an error of a left adjacent pixel B to the leading pixel of the 1st display line of the present frame. Moreover, the error diffusion ending pulse is also generated when an error of the last image of each display line of the present frame is calculated out. Upon calculation of the last error of each display line, the error diffusion ending pulse is changed from the 'H' level to the 'L' level, and the output of the adder 23 is set in the latch circuit 31.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus, and more specifically, to display luminance (error data) for displaying an input image having a high display gradation on a display apparatus having a low display gradation capability. To a peripheral pixel.

[0002]

2. Description of the Related Art In recent years, full-color PDPs (plasma display panels), which make the most of their thin characteristics, have been manufactured for wall-mounted televisions. The PDP is originally a monochrome image display device, but R (red) G is displayed on the display panel.
Color display is realized by applying phosphors of three colors (green) and B (blue).

In addition, the PDP employs a multi-gradation display system in order to improve the image quality. A subfield method is used for multi-gradation display. According to this method, each display cell simultaneously emits light for a light emission time proportional to the weight of write data to the display cell. FIG. 14A shows one frame period (vertical scanning period: 16.7) of PDP with 64 gradations.
ms) is shown. In FIG. 14 (A), SF1 to S
F6 is a subfield. Each field SF1-S
The relative ratio of the emission time of F6 is 1: 2,4,8,16,32
It is. By changing the light emission time for each subfield in this way, it is possible to realize a color display of 64 gradations. To increase the number of gradations, the number of subfields may be increased, but an "address period" for writing data in each subfield is required. Therefore, if the number of subfields is increased, the address period occupied in one frame period is increased, and the light emission time has to be relatively shortened. This reduces the brightness of the display panel.

Therefore, in order to display an input image having a high display gradation on a display device having a low display driving capability, "error diffusion processing" is adopted as a pseudo multi-gradation means. The error diffusion processing means that a display device capable of displaying the number of gradations A is
When a video signal having the above gradation number B is input, the actual gradation number is A by using the information (B-A) that the display device cannot display, but the gradation number that is close to B is pseudo. It is a technology to show to.

FIG. 14B is a characteristic diagram showing the relationship between the gradation of the input image and the gradation of the display image. In FIG. 14 (B), the thick line in the figure shows the characteristic when an input image of 256 gradations (8 bits) is applied with gradation display by applying all bits.
The step-like thin line is a characteristic when the upper 3 bits of the input image of 256 gradations are applied to display 8 gradations. This gradation characteristic shows the case where error diffusion processing is not performed,
A contour part like a human face appears as a step in brightness (gradation). Therefore, it is impossible to display a delicate natural image.

Therefore, as shown in FIG.
By using the brightness difference (hereinafter referred to as error or error data) between the triangle part (dotted part in the figure) created by the gradation property (thick line in the figure) and the 8 gradation property (thin line), Innumerable pseudo halftones (whiskers) are generated in the staircase portion as shown. This halftone error (brightness) is dispersed over the entire screen, which is blurred and recognized by the human eye, and the staircase portion of the 8-gradation characteristic changes smoothly.

In the error diffusion process, first, (1) threshold values are determined, (2) each threshold value is assigned to a display value, and (3)
The display value is determined by comparing the value of the input image with the threshold value and selecting the closest threshold value. Then, (4) an error is calculated from the difference between the selected threshold value and the input image, and (5)
The calculated error is represented by weights (1/16,
3/16, 5/16, 7/16) is added to diffuse to surrounding pixels (Floyd & Steinberg method).

In FIG. 15B, A is the pixel concerned, B is the pixel on the left, C is the upper left pixel, D is the pixel immediately above, and E is the upper right pixel. The error diffusion start position is the first position on the display screen.
It is the first pixel of the display line. The error diffuses from this position in a predetermined direction. The error is from one pixel to the pixel on the right,
It diffuses to the lower left pixel, the pixel directly below, and the lower right pixel. The error diffusion process is performed by such five procedures, of which the operations (3) to (5) are repeated for each pixel of the display screen.

As a result, the error is diffused from the upper left part of the screen toward the lower right part, and the error is accumulated more and more, and carry occurs in the least significant bit of the display value of each pixel. This carry causes a pseudo halftone in the gradation characteristic as shown in FIG. Then, the accumulated error is scattered over the entire screen, and the display screen can be made to look like the number of gradations close to the original image.

Next, a conventional error diffusion circuit will be described. In the configuration diagram of FIG. 16, 1 is m threshold values S1 to Sm.
Is an error detection circuit for detecting any _{one of the} display values X _{1 to} Xm and the error at that time when the difference between the input image and the input image is the smallest. The threshold value and the display value are equal to the number of gradations of the display device (m
Only) are provided, and the display value and the threshold value are associated with each other. 2 is a mask circuit for masking display values outside the error diffusion range, 3 to 6 are mask circuits for masking errors outside the error diffusion range, and 7 to 10 are predetermined weights α1 to α.
4 is a multiplier for multiplying the error, and 11 is an adder for adding all the errors diffused from the peripheral pixels of the pixel.
12 is a line memory that delays the output of the adder 11 (cumulative error: lower bit of carry part) by one display line,
13 to 15 are flip-flops that hold the error from the surrounding pixels.
It is a flop circuit (hereinafter referred to as FF circuit). An adder 16 adds the carry bit, which is the most significant error among the calculation results of the adder 11, to the display value from the error detection circuit 1. Reference numeral 17 is each mask circuit 2 to 6 and line memory 1
2 is a control unit for controlling 2.

Next, the operation of the error diffusion circuit will be described. Fig. 17
FIG. 18 is an operation timing chart when the error is diffused in the horizontal direction, and FIG. 18 is an operation timing chart when the error is diffused in the vertical direction. This time chart shows the case where the error diffusion range is designated for the pixels I3 to I17 of the pixels I1 to I20 on one display line of the input image.

For example, when an 8-bit input image is applied to a display device having a 5-bit display gradation, the error detection circuit 1 first sets m threshold values S1 to Sm from the 8-bit input image.
Any of the 5-bit display values X _{1 to} Xm and the error A at that time, which has the least error in the lower 3 bits after subtracting
´ is detected. This display value Xn corresponds to the first pixel I3 of the first display line.

Further, the mask circuit 2 operates so as to mask the display value outside the error diffusion range based on the mask signal S2 output from the control section 17, and the display value Xn of the pixel A concerned.
Is output to the adder 16. The mask circuit 3 operates so as to mask an error outside the error diffusion range based on the mask signal S1, and the error A ′ of the pixel is output to the adder 11.

From the calculation result of the adder 11, 3 bits below the carry portion are accumulated errors as the line memory 12 and F.
It is written in the F circuit 13. The output of the FF circuit 13 becomes an accumulated error delayed by one clock with respect to the input, that is, the error B ′ of the pixel B located on the left side of the pixel A. The line memory 12 delays the output of the adder 11 by 1 display line and 1 clock based on the read control signal from the control unit 17, and outputs the output to the multiplier 10. This line memory 12
Is the error E ′ of the pixel E on the upper right of the pixel A. The output of the line memory 12 is the FF circuit 14 and the FF.
By delaying each clock by the circuit 15,
The error D ′ of the pixel D located directly above the pixel A, the pixel A
The error C ′ of the pixel C located at the upper left of is obtained. Each mask circuit 4, 5, 6 masks an error outside the error diffusion range based on the mask signal S1. As a result, the peripheral pixels B,
The errors from C, D, and E are output to the multipliers 7 to 10, and the multipliers 7 to 10 multiply the errors by the coefficients α1 to α4 and weight them. The weighted errors are added by the adder 11. When a carry (carry = “1”) occurs in a new error as a result of the operation of the adder 11, this bit is added to the least significant bit of the display value from the error detection circuit 1. . The display value reviewed in this way is output to the display device as a display signal (display image). Also, the new error diffuses to surrounding pixels.

[0015]

However, in the error diffusion method according to the prior art, as shown in FIG. 19, as compared with the pixel A (case) at the center of the display screen, the pixels at the edges of the screen are surrounded by peripheral pixels. The error from is not sufficiently diffused.
That is, in FIG. 19, in the case, with respect to the first pixel A of the first display line, there is no error from the pixel B on the left, the pixel C on the upper left, the pixel D on the upper right, and the pixel E on the upper right.
In the case, there is an error in the pixel B on the left of the last pixel A on the first display line, but there is no error from the pixel C on the upper left, the pixel D immediately above, and the pixel E on the upper right. In the case, the pixel D directly above the first pixel A of the final display line
Although there is an error in the pixel E on the upper right and the pixel E on the upper right, there is no error from the pixel B on the left and the pixel C on the upper left. In the case, there is an error from the pixel B on the left, the pixel C on the upper left, and the pixel D immediately above the pixel A on the final display line, but there is no error from the pixel E on the upper right.

Therefore, as compared with the central part and the lower part of the screen where the errors are sufficiently accumulated, the uneven brightness occurs on the left side and the upper part of the screen where the error is insufficient, and the reproducibility of multi-gradation display is very high. There is a problem of getting worse. The present invention has been created in view of the problems of the conventional example, and compensates for the lack of the difference in the brightness of the pixel located in the upper left part of the display screen, and improves the image quality by eliminating the brightness unevenness in that part. It is an object of the present invention to provide an image processing device that enables the above.

[0017]

As shown in FIG. 1, a first image processing apparatus according to the present invention inputs image data of a pixel whose luminance display is N bits for each frame. , A device for outputting image data of a pixel whose luminance display is M (M <N) bits for each frame, and N− of the pixel obtained by subtracting M-bit image data from the N-bit image data of the pixel. Obtain the M-bit error data,
The error data of the peripheral pixel is added to the error data of the pixel to obtain new error data, and the bit data resulting from the carry of the new error data is added to the M-bit image data to correct the brightness and In an image processing apparatus that diffuses various error data to peripheral pixels, the error data of the pixels of the last display line of the previous frame of the display image is used as the error data diffused from the peripheral pixels of the first display line of the current frame. It is characterized in that it is added to the error data of the pixel.

In the second image processing apparatus of the present invention, the image data of the pixel whose luminance display is N bits is input for each frame, and the image data of the pixel whose luminance display is M (M <N) bits is framed. A device for outputting for each, wherein NM bit error data of the pixel obtained by subtracting M bit image data from the N bit image data is obtained, and error data of peripheral pixels is added to the error data. In the image processing apparatus, the error data is obtained, bit data obtained by carry of the new error data is added to the M-bit image data to correct the brightness, and the new error data is diffused to peripheral pixels. The plurality of pixels between the first display line and the arbitrary display line of the current frame of the image are divided into blocks, and the average value of the error data is calculated for each block. The average value of the error data obtained for each block is added to the error data of the display pixel of the first display line of the next frame as the error data diffused from the peripheral pixels, and the above object is achieved. .

In the first image processing apparatus of the present invention, by adding the error data of the pixels corresponding to the final display line of the previous frame to the error data of the pixels corresponding to the first display line of the current frame, It is possible to supplement the brightness of pixels from the upper left portion (error diffusion start point) to the upper right portion of the display screen. Therefore, since large error data can be given to these pixels from the beginning, uneven brightness from the upper left portion to the upper right portion of the display screen is eliminated.

In the first device of the present invention, the error data of the last pixel of the display line before the last display line of the previous frame of the display image is used as the error data of the first pixel of the first display line of the current frame. By adding, large error data can be given to the leading pixel of the first display line, so that the uneven brightness in the upper left portion of the display screen is eliminated.
Furthermore, by adding the error data of the last pixel of each display line to the error data of the first pixel of the line,
Since large error data can be given to the leading pixel of each display line, the uneven brightness on the left side of the display screen is eliminated.

In the second image processing apparatus of the present invention, the average value of the error data obtained for each block is calculated as the first value of the next frame.
By adding to the error data of the pixel on the display line, the error in the upper left part of the display screen can be compensated. Therefore, since large error data can be given to these pixels from the beginning, the uneven brightness in the upper left portion of the display screen is eliminated.

Further, in the second device of the present invention, the average value of the error data obtained for each block is added to the error data of the first pixel and the last pixel of each display line of the next frame. Since large error data can be given to the pixel from the beginning, the uneven brightness on the left side or the right side of the display screen is eliminated.

[0023]

Next, an embodiment of the present invention will be described with reference to the drawings. 1 to 13 are explanatory views of the image processing apparatus according to the embodiment of the present invention. The image processing device of the present invention is characterized in that image signals for raster-scanning one image are transmitted in time series,
By utilizing the fact that there is a correlation between the frames of the display image, the error data (hereinafter simply referred to as an error) of the pixels at the end portions of the display screen is calculated.

(1) First Embodiment FIG. 1 shows an explanatory diagram of an error diffusion process according to a first embodiment of the present invention. The first error diffusion method utilizes the above characteristics. FIG. 1 is a diagram in which the current frame and the previous frame of the display image are connected for convenience. In FIG. 1, L is the current frame of a certain display image, and L-1 is the previous frame of the display image. The frame constitutes a display screen of m dots × n lines. The shaded area (a) shows the pixel type at the center of the screen, and (b) to (g) show the pixel types at the edge of the screen. Next, the peripheral pixels that give an error to these types of pixels will be shown. The numbers in parentheses below indicate the dot number, line number, and frame number in order. X is an arbitrary dot and Y is an arbitrary line.

(A) Pixels (X, Y,
L) is a basic pattern. However, 1 <Y <n, 1 <
X <m. As for the peripheral pixels that give an error to this pixel, the pixel on the left is B: (m-1, n, L),
The upper left pixel is C: (m-1, n-1, L), the pixel immediately above is D: (m, n-1, L), and the upper right pixel is E: (m + 1, n-1). , L).

(B) The pixel (1, 1, 1) at the upper left of the screen
The neighboring pixels that give an error to L) are
B: (m, n, L-1), the upper left pixel is C:
(M, n-1, L-1), the pixel directly above is D: (1
, N, L−1), and the upper right pixel is E: (2,
n, L-1).

(C) The top pixel (X, 1,
L), that is, peripheral pixels that give an error to the pixels (1 <X <m) on the first display line excluding the pixels at the upper left and upper right of the screen, B: (X -1,1
, L), the upper left pixel is C: (X−1, n,
L-1), the pixel immediately above is D: (X, n, L
−1), the upper right pixel is E: (X + 1, n, L−)
1).

(D) The pixel (m, 1,
The neighboring pixels that give an error to L) are
B: (m-1, 1, L), the upper left pixel is C:
(M-1, n, L-1), the pixel directly above is D: (m
, N, L−1), and the upper right pixel is E: (m,
1, L).

(E) Regarding the peripheral pixels that give an error to the first pixel (1, 2, L) of the second display line of the screen, the pixel on the left is B: (m, 1, L), and the upper left pixel is The pixel is C: (m, n, L-1), the pixel directly above is D: (1, 1, L), and the upper right pixel is
E: (2, 1, L).

(F) Each head pixel (1, 1 at the left end of the screen
Y, L), that is, peripheral pixels that give an error to the leftmost pixel (2 <Y <n) excluding the first pixel of the first and second display lines of the screen, the pixel adjacent to the left is B: (M, n
-1, L), the upper left pixel is C: (m, n-
2, L), the pixel immediately above is D: (1, n-1,
L), the upper right pixel is E: (2, n-1, L
).

(G) The final pixel (m,
As for the peripheral pixels that give an error to (n, L), the pixel on the left is B: (m-1, n, L) and the pixel on the upper left is
C: (m-1, n-1, L) the pixel directly above is D:
The pixel at the upper right of (m, n-1, L) is E: (1
, N, L).

Next, such peripheral pixels B, C, D, E
An error diffusion circuit that gives an error to pixels of 7 to 7 types will be described. FIG. 2 shows a configuration diagram of the error diffusion circuit according to the first embodiment. In FIG. 2, 20 is an error detection circuit, 21, 22, 28 to 30 are mask circuits, 23 is an adder, and 24 is the output (cumulative error) of the adder 23 based on the read control signal SR and the write control signal SW. It is a line memory that delays by one display line (one horizontal period). In the conventional example, writing is completed on the display line immediately before the final display line, but in the present embodiment, writing is performed up to the error of the final display line. Read-out starts from the first pixel of each display line. In this way, the error of each pixel of the last display line of the previous frame can be used for the calculation of the error of the first pixel of the first display line. "0" in the conventional example
The error of the upper left pixel C, the pixel D directly above, and the upper right pixel E can be taken from the final display line of the previous frame as the error of the first pixel.

Reference numerals 25, 26 and 27 denote flip-flop circuits (hereinafter referred to as FF circuits). The FF circuit 25 delays the output of the adder 23 by one clock, and the pixel B on the left side is delayed.
It operates to give an error that diffuses from ′ to the pixel. F
The F circuit 26 delays the output of the line memory 24 by one clock, and operates to give an error that diffuses from the pixel D ′ directly above to the pixel. The FF circuit 27 is the line memory 24.
The output of is delayed by 2 clocks, and the pixel C at the upper left of the pixel is
It operates to give the error from ´.

So far, there is no great difference from the conventional example, but the configuration is different in the following points. Reference numeral 31 is a latch circuit which latches the output (pixel error) of the adder 23 in accordance with the error diffusion end pulse (S5). The latch circuit 31 outputs the error (error B ′) of the adder 23 when calculating the error of the pixels of (b), (e) and (f) types as shown in FIG.
To act as a latch. The error diffusion end pulse is
It occurs when the error of the final pixel of the final display line (n lines) of the previous frame is calculated. When the error diffusion end pulse changes from “H” to “L” level, the output of the adder 23 is set in the latch circuit 31. As a result, the error of the last pixel of the previous frame as the error of the pixel B adjacent to the left can be given to the first pixel of the first display line of the current frame.

The error diffusion end pulse is generated when the error of the last pixel of each display line (1 to n lines) of the current frame is calculated. The error diffusion end pulse is from “H” to “L” when the error of the last pixel of each display line is calculated.
Change to a level. As a result, the output of the adder 36 is set in the latch circuit 31. The latch circuit 31 outputs the error (error B ′) of the adder 23 when calculating the error of the pixels of (b), (e) and (f) types as shown in FIG.
To act as a latch. As a result, the error of the last pixel of each display line can be given to the first pixel of each display line of the current frame as the error of the pixel B on the left side.

A latch circuit 32 latches the output of the latch circuit 31 in accordance with the latch pulse signal (S4).
The latch circuit 32 operates so as to latch the output of the latch circuit 32 as an error C ′ when calculating the error of the pixels of (b), (c), (d), (e) and (f) types. To do. As a result, the error of the last pixel of each display line as the error of the pixel C in the upper left portion can be given to the first pixel of each display line of the current frame.

A latch circuit 33 latches the output of the adder 23 in accordance with the error diffusion start pulse (S3). The latch circuit 33 operates so as to latch the output (error E ′) of the adder 23 when calculating the error between the (d) and (g) type pixels. The error diffusion start pulse is generated when calculating the error of the leading pixel of each display line of the current frame. Error diffusion start pulse is from "H" to "L"
When the level changes, the output of the adder 23 changes to the latch circuit 3
Set to 3. As a result, the error of the first pixel of the current frame as the error of the pixel E in the upper right portion can be given to the last pixel of each display line of the current frame.

A selector 34 selects either the output of the latch circuit 31 or the output of the FF circuit 25 (error B ') according to the error diffusion start pulse. The selector 34 is
(A), (c), (d) and (g) as shown in FIG.
When calculating the error of the pixel of the type, it operates so as to select the error B ′ on the input 1 side, but when calculating the error of the pixel of the types (b), (e) and (f), the input 2 is input. It operates so as to select the output of the side latch circuit 31.

A selector 35 selects either the output of the latch circuit 32 or the output of the FF circuit 27 (error C ') according to the error diffusion start pulse. The selector 35 is
When calculating the error of (a) and (g) type pixels,
It operates to select the error C'on the input 1 side,
When calculating the error of the pixels of (b), (c), (d), (e) and (f) types, the latch circuit 32 on the input 2 side is used.
Works to select the output of.

Reference numeral 36 indicates the output of the latch circuit 33 or the output of the line memory 24 (error E according to the error diffusion end pulse).
It is a selector for selecting any one of ´). Selector 3
6 operates to select the error E ′ on the input 1 side when calculating the errors of the pixels of (a), (e) and (f) types, but (b), (c), ( When calculating the error of pixels of d) and (g) type, the latch circuit 3 on the input 2 side is used.
3 to select the output.

Reference numeral 37 is a multiplier for multiplying the error from the pixel B by a predetermined weight α1 = 7/16, 38 is a multiplier for multiplying the error from the pixel C by the weight α2 = 1/16, and 39 is a pixel A multiplier that multiplies the error from D by the weight α3 = 5/16, 4
0 is a multiplier that multiplies the error of pixel E by the weight α4 = 3/16. Reference numeral 41 is an adder for adding the lower bits of the carry part of the error in the calculation result of the adder 30 to the display value from the error detection circuit 20. The following expression is, for example, a 6-bit display value X _n, X _n-1, X _n-2, X _n-3, X _{n- 4,} X
_The error Y _m . Y _m-1, Y _m-2, Y
Outputs of adder 30 when _m-3, Y _m-4, Y _{m- 5} are added Z _n, Z _n-1, Z _n-2, Z _n-3, Z _n-4, Z _n-5 ． Y
_m-1, Y _m-2, Y _m-3, Y _{m-4, and} Y _m-5 are shown.

[0042]

[Equation 1]

Y _m is a bit in the carry portion, and when the carry increases as a result of adding the error from the peripheral pixels to the error in the display value, X _n-5 changes. The display value can be corrected by changing X _n-5 . For example, the displayed value is "11
In the case of "1000", if carry = 1 goes up,
The display value is corrected to "111001" and the display value becomes "11.
In the case of "1001", if carry = 1 goes up,
The display value is corrected to "1111010".

Reference numeral 42 is a control unit for controlling input / output of the mask circuits 22, 28-30, the latch circuits 31-33, the selectors 34-36 and the line memory 24. Control unit 42
Is a vertical synchronization signal (V-SYNC) and a horizontal synchronization signal (H
-SYNC) and the error diffusion range designation value, the mask signal S1 is output to each of the mask circuits 28 to 30, the mask signal S2 is output to the mask circuit 22, and the read control signal and the write control signal are output to the line memory 24. The mask signals S1 and S2 are "H" when designating the error diffusion range.
To level.

Further, the control unit 42 detects the error diffusion start position and the error diffusion end position for each display line from the vertical synchronization signal, the horizontal synchronization signal and the error diffusion range designation value, and detects the error diffusion start pulse and the latch. A pulse and an error diffusion end pulse are generated. The error diffusion start pulse is generated by the selectors 34 and 3
5 and the latch circuit 33, the latch pulse is output to the latch circuit 32, and the error diffusion end pulse is output to the latch circuit 3.
1, output to the selector 36.

Next, the operation of the error diffusion circuit according to this embodiment will be described. FIG. 3 is an operation timing chart when the error is diffused in the vertical direction. This time chart shows vertical pixels I0 to I20 of one frame of the input image.
This is the case where the error diffusion range is designated for the pixels I2 to I18, and the case where there are 17 display lines is shown. In this embodiment, the case where the errors Y18a, Y18b, ... Of the final pixels of the final display line of the previous frame are used as the errors of the peripheral pixels C, D, E is shown. First, the error detection circuit 20
Is an input image (brightness value), and the display value (brightness) X2 and the error A at that time with the smallest error as in the conventional example.
2 is detected. This display value X2 corresponds to the first pixel I2 of the first display line. The display value X2 is the brightness value of the pixel to be displayed on the display device.

Further, the mask circuit 21 operates so as to mask the display value outside the error diffusion range based on the mask signals S1 and S2 for each display line, and the display value X2 of the pixel is output to the adder 41. . The mask circuit 22 receives the mask signal S
Based on 1, the error outside the error diffusion range is masked, and the pixel error A2 is output to the adder 23.

The lower bit from the carry portion is written in the line memory 24 as a cumulative error according to the calculation result of the adder 23. The line memory 24 delays the output of the adder 23 by one display line based on the read control signal and selects the selector 3
6 is output. The selector 36 operates to select either the output of the latch circuit 33 or the error E ′ masking the output of the line memory 24 according to the error diffusion end pulse. At this time, the selector 36 operates so as to select the error E ′ of the input 1 when calculating the errors of the pixels of (a), (e) and (f) types, but (d), (g )
When calculating the error of the type pixel, it operates so as to select the output of the latch circuit 33 on the input 2 side.

Similarly, for the remaining display lines, the error detection circuit 20 detects the display values X3 to X18 and the errors A3 to A18, and when the predetermined error diffusion processing is continued, the adder 23 outputs Y2b to Y18b. Like Then, when the error Y18b of the final pixel I18 of the final display line is obtained, it is used as the error of the peripheral pixels C, D, E of the first display line of the next frame (see FIG. 3).

The output from the line memory 24 is the error E'of the pixel E on the upper right of the pixel. When the output of the line memory 24 is delayed by one clock by the FF circuit 26 and the FF circuit 27, the error D of the pixel D immediately above the pixel A concerned is delayed.
', The error C'of the pixel C at the upper left of the pixel A is obtained. Then, the multiplier 37 weights the error from the pixel B by α1 = 7/16
And the multiplier 38 weights the error from the pixel C by α2 =
Multiply by 1/16, the multiplier 39 multiplies the error from the pixel D by the weight α3 = 5/16, and the multiplier 40 by the weight α4 = 3/16
Operates to multiply the error by the pixel E. As a result, when a carry occurs in the operation result of the adder 30, the adder 41 sets this carry bit = "1" to the error detection circuit 2
Operates to add to the displayed value from 0. As a result, the adder 41 outputs Z2 to Z18 as display signals to the display device. The new error diffuses to the pixels of the second frame.

FIG. 4 shows an operation timing chart when the error is diffused in the horizontal direction. This time chart shows the case where the error diffusion range is specified for 17 pixels of the pixels in the horizontal direction of one display line of the input image, and shows the case where there are 17 display pixels. In FIG.
As shown in FIG. 1, as the error from the pixel E on the upper right,
It shows a case where the error of the first pixel of the display line is given to the last pixel of the display line. In this case, the error detection circuit 20 detects the display value X2 and the error A2 at that time, the mask circuit 21 masks the display value outside the error diffusion range based on the mask signal S2, and the mask circuit 22 sets the mask signal S1. Based on this, it operates to mask errors outside the error diffusion range. Further, the adder 23 outputs the calculation result (error) Y2a to the latch circuit 33. The latch circuit 33 latches the error Y2a for one horizontal period based on the error diffusion start pulse S3.

The selector 36 calculates the error of the pixels of (d) and (g) type according to the error diffusion end pulse,
It operates so as to select the output of the latch circuit 33 on the input 2 side. This causes the first error as the error from the pixel E on the upper right.
The error of the first pixel of the display line can be added to the error of the last pixel of the display line. Is the pixel B on the left
The case where an error of the last pixel of the first display line is given to the first pixel of the second display line as an error from In this case, the error detection circuit 20 detects the display value X18 and the error A18 at that time, the mask circuit 21 masks other than the display value of the pixel, and the mask circuit 22 masks the error outside the error diffusion range. Operate. Further, the adder 23 outputs the calculation result (error) Y18a to the latch circuit 31.
Then, the latch circuit 31 latches the error Y18a for one horizontal period based on the error diffusion end pulse S5, and the selector 34 inputs the error Y18a in order to calculate the error of the pixels of (b) and (e) type according to the error diffusion end pulse. It operates so as to select the output of the latch circuit 31 on the second side. As a result, the error of the last pixel of the first display line can be added to the error of the first pixel of the second display line as an error from the pixel B on the left side.

Shows the case in which the error of the last pixel of the first display line is given to the first pixel of the third display line as the error from the upper left pixel C. In this case, the adder 23
The calculation result Y18a is latched by the latch circuit 32 based on the latch pulse. Then, the selector 35 operates so as to select the output of the latch circuit 32 on the input 2 side in order to calculate the error of the pixels of (b), (e), and (f) types according to the error diffusion end pulse. As a result, the error of the last pixel of the first display line can be added to the error of the first pixel of the third display line as an error from the upper left pixel C.

Is the second error as the error from the pixel E on the upper right.
It shows a case where the error of the first pixel of the display line is given to the last pixel of the display line. In this case, the error detection circuit 20 detects the display value X2 and the error A2 at that time, and the mask circuit 21 masks the display value outside the error diffusion range.
The mask circuit 22 operates so as to mask errors outside the error diffusion range. Further, the adder 23 outputs the operation result Y2b to the latch circuit 33.

The selector 36 calculates the error of the (d) and (g) type pixels according to the error diffusion end pulse.
It operates so as to select the output of the latch circuit 33 on the input 2 side. As a result, the error from the pixel E on the upper right is
The error of the first pixel of the display line can be added to the error of the last pixel of the display line. Is the pixel B on the left
The error from the last pixel of the second display line is given to the first pixel of the third display line. In this case, the error detection circuit 20 detects the display value X18 and the error A18 at that time, the mask circuit 21 masks the display value outside the error diffusion range, and the mask circuit 22 masks the error outside the error diffusion range. To work. Also, adder 2
3 outputs the error Y18b to the latch circuit 31. And
The latch circuit 31 latches the error Y18b for only one horizontal period, and the selector 34 selects the output of the latch circuit 31 on the input 2 side in order to calculate the error of the (b) and (e) type pixels according to the error diffusion end pulse. To work. As a result, the error of the last pixel of the second display line can be added to the error of the first pixel of the third display line as an error from the pixel B on the left side.

Is the third error as the error from the pixel E on the upper right.
The figure shows a case where the error of the first pixel of the display line is used to calculate the error of the last pixel of the display line. In this case, the error detection circuit 20 detects the display value X2 and the error A2 at that time, the mask circuit 21 masks the display value outside the error diffusion range based on the mask signal S2, and the mask circuit 22 sets the mask signal S1. Based on this, it operates to mask errors outside the error diffusion range. Further, the adder 23 outputs the error Y2b to the latch circuit 33. Latch circuit 33
Latches the error Y2b for one horizontal period, and the selector 36
Is a latch circuit 33 on the input 2 side in order to calculate the error of the (d) and (g) type pixels according to the error diffusion end pulse.
Works to select the output of. As a result, the error of the first pixel of the second display line can be added to the error of the last pixel of the display line as an error from the pixel E on the upper right.

In this way, according to the image processing apparatus of the first embodiment of the present invention, as shown in FIG. 1, the pixel C at the upper left portion, the pixel D immediately above and the pixel E at the upper right portion are provided. The error of each pixel of the last display line (n) of the previous frame is added to the error of the pixels of (b), (c) and (d) type of the first display line of the current frame as an error diffused from This makes it possible to compensate for the errors that are lacking in these (b), (c) and (d) type pixels. Therefore, since a large error can be given to these pixels from the beginning, the upper left part of the display screen (error diffusion start point)
It is possible to eliminate the uneven brightness.

In addition, in the first embodiment of the present invention, as the error diffused from the pixel E in the upper right part, the error of the leading pixel of each display line of the current frame of the display image is calculated as the error of the current frame. (D) of each display line
By adding to the error of the last pixel of type (g),
It is possible to compensate for the errors that are lacking in the final pixels of these (d) and (g) types. Therefore, since large error data can be diffused to the final pixel of each display line, the uneven brightness on the right side of the display screen can be eliminated.

Further, in the first embodiment of the present invention, as the error diffused from the pixel B on the left side, the error of the last pixel of each display line of the current frame of the display image is calculated as the error of the current frame. (B), (e) of each display line
By adding to the errors of the leading pixels of types (f) and (f), it is possible to compensate for the errors that are lacking in the leading pixels of types (b), (e) and (f). Therefore,
Since a large error can be diffused to the leading pixel of each display line, the uneven brightness on the left side of the display screen can be eliminated. The circuit can be configured by adding a latch circuit and a selector, and the brightness can be easily corrected.

(2) Second Embodiment FIG. 5 is an explanatory diagram of the error diffusion processing according to the second embodiment of the present invention. The second embodiment is different from the first embodiment in that the error of the pixel at the edge of the display screen is calculated by utilizing the fact that “there is a correlation between the frames of the display image”. . Generally, one display
Images of several tens of frames (about 60 frames in the case of TV images) are continuously displayed per second, and there is no significant difference between the frames and there is a correlation. Furthermore, focusing on the pixels on a certain display line in the same frame,
It is rare that the luminance level of the peripheral pixels of the pixel changes significantly, and it can be said that there is a correlation.

Therefore, in the present embodiment, first, the area at the end of the current frame of the display screen is divided into m × n pixel blocks, and the average value of the error components of the pixels in the blocks is calculated. In the next frame, the average error calculated in each block of the previous frame is diffused to the pixels located at the edges of the display screen. By doing so, it becomes possible to calculate the error of the pixel with a correlated value.

In FIG. 5A, L is the current frame of a certain display screen, and (1) to (13) are blocks. Blocks (1) to (7) are obtained by dividing 4 × 28 pixels located on the first to fourth display lines into seven. Blocks (8), (10), and (12) are the fifth
4 × 16 pixels from the first dot to 4 dots of the display line to the 16th display line are divided into three.
Blocks (9), (11), and (13) are from the 5th display line to the 5th display line.
4x from the last dot of 16 display lines to the front 4 dots
12 pixels are divided into three. Each block is composed of 4 × 4 pixels. For the average error of each block, add all the errors of each pixel, and add
It is one-half.

In FIG. 5B, L + 1 is the next frame of this display screen. In the present embodiment, the average error calculated in block (1) is used when calculating the error between the first pixel to the fourth pixel of the first display line and the first pixel of the second to fourth display lines of the display screen. , The pixel B adjacent to the left, the pixel C on the upper left, and the pixel D immediately above are used as errors. The average error obtained in the block (2) is the error of each of the pixel E on the upper right, the pixel D on the upper right, and the pixel C on the upper left when calculating the error between the first pixel to the twelfth pixel on the first display line. To use as. The average error obtained in the block (3) is the error of each of the pixel E on the upper right, the pixel D on the upper right, and the pixel C on the upper left when calculating the error of the fifth pixel to the sixteenth pixel of the first display line. To use as. The average error obtained in the block (4) is the ninth pixel to the twentieth pixel of the first display line.
When calculating the error of the pixel, it is used as the error of each of the pixel E on the upper right, the pixel D on the upper right, and the pixel C on the upper left. The average error obtained in the block (5) is the error of each of the pixel E on the upper right, the pixel D on the upper right, and the pixel C on the upper left when calculating the error of the 13th pixel to the 24th pixel of the first display line. To use as. The average error obtained in the block (6) is the error of each of the pixel E at the upper right, the pixel D immediately above, and the pixel C at the upper left when calculating the error of the 17th pixel to the 28th pixel of the first display line. To use as. The average error obtained in the block (7) is the pixel E at the upper right and the pixel immediately above when calculating the error between the 21st pixel to the 28th pixel of the first display line and the final pixel of the 2nd to 4th display lines. It is used as the error of each pixel D.

The average error obtained in the block (8) is used as the error between the pixel B on the left and the pixel on the upper left when calculating the error of the leading pixel of the fifth to eighth display lines. The average error obtained in the block (9) is the fifth to eighth
When calculating the error of the last pixel of the display line, it is used as the error of the upper right pixel E. The average error obtained in the block (10) is used as the error between the pixel B on the left side and the pixel on the upper left side when calculating the error of the leading pixel of the ninth to twelfth display lines. The average error obtained in the block (11) is used as the error of the upper right pixel E when calculating the error of the final pixel of the ninth to twelfth display lines. Block (1
The average error obtained in 2) is used as the error between the pixel B on the left side and the pixel on the upper left side when calculating the error of the head pixel of the 13th to 16th display lines. The average error obtained in the block (13) is used as the error of the upper right pixel E when calculating the error of the final pixel of the 13th to 16th display lines.

Next, such blocks (1) to (13)
An error diffusion circuit that applies the average error of 1 to the pixels at the end of the display screen will be described. FIG. 6 shows a configuration diagram of the error diffusion circuit according to the second embodiment. In FIG. 6, 51
Is an error detection circuit, 52, 22, 74 to 76 are mask circuits, and 53 is an adder. An adder 54 adds the outputs of the adder 53 according to the enable signal Se and accumulates the error of each block. 55 is a flip-flop circuit (hereinafter referred to as FF) that holds the output of the adder 54 for only one clock.
Circuit). Reference numeral 56 is a memory for storing the error of each block. The memory 56 has a capacity for accumulating a cumulative error of two frames. Memory 56 is 1
An area M1 for storing the cumulative error of the frame and an area M2 for storing the cumulative error of the second frame are provided.

Reference numeral 57 is a selector for selecting either the output of the FF circuit 55 or the output of the memory 56 for each display line based on the switching signal Sa. 58 is a memory 56
Is an arithmetic unit that calculates the average error of each block from the output of. The calculator 58 operates to calculate the average error by dividing the error of each block by the number of pixels in the block, which is 4 × 4. A line memory 59 delays the output of the adder 53 by one horizontal period based on the read control signal SR and the write control signal SW.

Numeral 60 is an arithmetic unit 5 according to the latch pulse P1.
It is a latch circuit for latching 8 outputs (average error of each block). The latch circuit 60 outputs the output of the adder 53 (error B ′) when calculating the error of the pixels of (b), (e) and (f) types as described in the first embodiment.
To act as a latch. As a result, as the error of the pixel B on the left side, the blocks (1), (8), and
The average error of (10) and (12) is calculated as the first error of the current frame.
~ It can be given to the first pixel of the 16th display line.

Reference numeral 61 is an arithmetic unit 5 according to the latch pulse P2.
8 is a latch circuit for latching the output of 8. Latch circuit 6
Similarly, 1 is the calculator 5 when calculating the error of the pixels of the (b), (c), (d), (e) and (f) types.
It operates so as to latch the output of 8 as an error C '.
As a result, blocks (1) to (8) of the previous frame,
Each average error of (10) and (12) can be given to the pixel of the first display line and the first pixel of the first to sixteenth display lines of the current frame as an error of the pixel C in the upper left part.

Numeral 62 is an arithmetic unit 5 according to the latch pulse P3.
8 is a latch circuit for latching the output of 8. Latch circuit 6
2 operates to latch the output of the calculator 58 as an error D ′ when calculating the error of the pixels of the (b), (c) and (d) types. As a result, each average error of the blocks (1) to (7) of the previous frame can be given to each pixel of the first display line as an error of the pixel D immediately above.

Reference numeral 63 is a calculator 5 according to the latch pulse P4.
8 is a latch circuit for latching the output of 8. Latch circuit 6
3 operates so as to latch the output (error E ′) of the calculator 58 when calculating the error of the pixels of (d) and (g) types. As a result, the average error of the blocks (7), (9), (11), and (13) of the previous frame can be given to the final pixel of each display line of the current frame as the error of the pixel E in the upper right portion. Reference numerals 64 to 66 are latch circuits for aligning the output timings of the latch circuits 61 to 63 based on the latch pulse P5. 71, 72, 7
Reference numeral 3 is an FF circuit, which has the same function as the FF circuits 25 to 27 according to the first embodiment.

A selector 67 selects either the output of the latch circuit 60 or the error B'masking the output of the FF circuit 71 according to the select signal SS1. The selector 67 selects the error B ′ on the input 1 side when calculating the error of the pixels of (a), (c), (d) and (g) types as shown in FIG. It works, but (b),
When calculating the error of the pixels of types (e) and (f), it operates so as to select the output of the latch circuit 60 on the input 2 side.

Reference numeral 68 is a selector for selecting either the output of the latch circuit 64 or the error C ′ obtained by masking the output of the FF circuit 73 according to the select signal SS2. The selector 68 operates so as to select the error C ′ on the input 1 side when calculating the error of the pixels of (a) and (g) types, but (b), (c), (d), When calculating the error of the pixels of types (e) and (f), it operates so as to select the output of the latch circuit 64 on the input 2 side.

Reference numeral 69 is a selector for selecting either the output of the latch circuit 65 or the error D'which masks the output of the FF circuit 72 according to the select signal SS2. The selector 69 operates so as to select the error D ′ on the input 1 side when calculating the error of the pixels of (a), (f), and (g) types, but (b), (c), and When calculating the error of the pixel of the (d) type, the output of the latch circuit 65 on the input 2 side is selected.

A selector 70 selects either the output of the latch circuit 66 or the error E'masking the output of the line memory 59 according to the select signal SS3. The selector 70 operates so as to select the error E ′ on the input 1 side when calculating the errors of the pixels of (a), (e) and (f) types, but (b), (c), When calculating the error of the (d) and (g) type pixels, the operation is performed so as to select the output of the latch circuit 66 on the input 2 side.

Incidentally, 77 to 80 are multipliers, and have the same functions as the multipliers 37 to 40 according to the first embodiment. Reference numeral 81 is an adder that adds the lower bits of the carry portion of the error in the calculation result of the adder 76 to the display value from the error detection circuit 51. The calculation formula is shown in the first embodiment. Reference numeral 82 denotes mask circuits 52, 74 to 76, adder 54, memory 56, selector 57, calculator 58, line memory 59, latch circuits 60 to 66, and selector 67 to.
It is a control unit that controls the input and output of 70. The control unit 82 has the following functions in addition to the functions of the control unit 42 described in the first embodiment. The control unit 82 detects the error diffusion start position and the error diffusion end position and detects the latch pulse P1.
-P5 and selector signals SS1-SS3 are generated. The latch pulses P1 to P5 are output from the control unit 82 to each latch circuit immediately before each block calculates the error, and the selector signals SS1 to SS3 calculate the error of the pixel of (a) type as shown in FIG. And (b) to (g) type pixel error calculation.

The control unit 82 controls the blocks (1) to (13).
When the error is calculated by, the enable signal Se is output to the adder 54 and the switching signal Sa is output to the selector 57. The enable signal Se is reset for each display line and each of the blocks (1) to (13) in order to add the error of only the pixels in the block. Switching signal Sa
Is a signal for adding the error added in the previous display line to the error in the next display line, and is output to the selector 57.

The control unit 82 specifies the write address (ADD) so as to write the error of each block (1) to (13) in the memory area M1 and outputs the write enable signal WE to control the memory 56. . The control unit 82 also outputs the read enable signal RE to the memory 56 when the average error (DATA) is given to the error diffusion circuit. Further, the control unit 82 obtains the number of pixels in the block from the block division information, and outputs this number of pixels to the calculator 58. The other configurations and those having the same names as those in the first embodiment have the same functions, and thus the description thereof will be omitted.

Next, the operation of the error diffusion circuit according to the second embodiment will be described. 7A and 7B are operation timing charts when the intra-block error of the error diffusion circuit is calculated. FIG. 7A is a time chart for calculating the cumulative error of the seven blocks on the first display line. Figure 7
In (A), the adder 53 outputs the errors A0 to A3 of the block (1) of the first display line to the adder 54, and similarly, the errors B0 to B3 of the block (2) and the error C0 of the block (3). -C3, errors D0-D3 of block (4), errors E0-E3 of block (5), errors F0-F3 of block (6), and errors G0-G3 of block (7) are sequentially output to the adder 54. To work. The output of the adder 54 is delayed by one clock by the FF circuit 55, and the delayed errors a0 to a3, b0 to b3, c0 to c3,
d0-d3, e0-e3, f0-f3 and g0-g3
Are selected by the selector 57 in accordance with the switching signal Sa. When the selector 57 selects the output of the FF circuit 55, the errors a0 to a3, b0 to b3, c0 to c
3, d0-d3, e0-e3, f0-f3 and g0-g
3 is fed back to the adder 54.

Then, the adder 54 outputs the enable signal Se.
Error a0 for each block of the first display line based on
a3, b0-b3, c0-c3, d0-d3, e0-e
3, f0 to f3 and g0 to g3 are sequentially added. At this time, when the error is added for each block, the control unit 82 specifies the write address (ADD = aa) and stores the cumulative error am = a0-a3 of the first display line of the block (1) in the memory area M1. Write. The control unit 82 outputs the write enable signal WE to the memory 56. Cumulative error bm = b0 to b3, cm = c of other blocks (2) to (7)
0-c3, dm = d0-d3, em = e0-e3, fm
= F0 to f3 and gm = g0 to g3, the control unit 82 specifies the write address (ADD = ab, ac ...) And outputs the write enable signal WE to write the same. In the case of the next frame (L + 1), the memory area is changed from M1 to M.
To change to 2, the write address ADD is bb, bb,
Specify bc ...

Further, FIG. 7B shows the second display line 7
7 shows a calculation time chart of the cumulative error of one block. In FIG. 7B, the adder 53 outputs the errors A0 to A3 of the block (1) of the second display line to the adder 54, and similarly, the errors B0 to B3 of the block (2) and the errors of the block (3). Error C0 to C3, error D0 of block (4)
D3, errors E0 to E3 of block (5), errors F0 to F3 of block (6), and error G of block (7)
It operates so as to sequentially output 0 to G3 to the adder 54.

The difference from the operation of the first display line is that of the second
Of the first display line stored in the memory area M1, the accumulated errors am, bm, cm, dm, em, fm
And gm are read and added to the error of the display line. Specifically, the control unit 82 controls the selector 5
When the switching signal Sa is output to 7, the selector 57 selects the output of the memory 56, and the accumulated errors am, bm, cm, dm, em, fm, and gm obtained on the first display line are fed back to the adder 54. To be done. And
Errors a0 to a2, b0 to b2, c0 to c2, d0 to d2, e from the adder 53 delayed by the FF circuit 55
0 to e2, f0 to f2 and g0 to g2 have accumulated errors am,
bm, cm, dm, em, fm and gm are added.
As a result, when the cumulative error is added for each block, the control unit 82 specifies the write address (ADD = aa) and writes the error of the second display line of the block (1) in the memory area M1. The accumulated errors of the other blocks (2) to (7) are also designated by the write address (ADD = ab, ac ...), and the write enable signal WE is output and written in the same manner. By repeating such an operation, the accumulated error of the seven blocks from the first display line to the fourth display line as shown in FIG. 5 can be stored in the memory 56, respectively.

In the subsequent operation, the average value of the cumulative errors of each of the seven blocks (1) to (7) is calculated, and the average error is diffused to all the pixels of the first display line of the next frame. . FIG. 8 is an operation time chart (at the time of latch writing) of the error diffusion circuit according to the embodiment of the present invention. In the present embodiment, the calculator 58 starts calculating the average value of each block from the idle time between the frames of the display screen,
Immediately before the error calculation of the first pixel of the first display line of the next frame, these average errors (DATA) are latched by the latch circuit 6.
Latch at 0-63.

In FIG. 8, the controller 82 outputs the read enable signal RE to the memory 56 and specifies the number of pixels in the block to the calculator 58 immediately before the error calculation. Then, each block (1) to read from the memory 56
Cumulative error am, bm, cm, dm, em, fm of (7)
And gm are divided by the number of pixels in the block (4 × 4).
This is the average error for each block. This average error is given to the latch circuits 60, 61, 62 and 63.

The latch circuit 60 outputs the arithmetic unit 58 (average error of the block (1)) based on the latch pulse P1.
The latch circuit 61 latches the output of the calculator 58 based on the latch pulse P2, and the latch circuit 62 latches the output of the calculator 58 according to the latch pulse P3. Then, the latch circuit 63 latches the output (average error of the block (2)) of the calculator 58 according to the latch pulse P4. After that, the latch circuits 64 to 66 operate so that the output timings of the latch circuits 61 to 63 are aligned based on the latch pulse P5.

When the control section 82 outputs the select signal SS1 to the selector 67, the select signal SS2 to the selectors 68 and 69, and the select signal SS3 to the selector 70, the selector 67 latches the input 2 side latch. Selector 6 operates to select the output of circuit 60.
8 operates to select the output of the latch circuit 64 on the input 2 side, the selector 69 operates to select the output of the latch circuit 65 on the input 2 side, and the selector 70 operates to select the output of the latch circuit 66 on the input 2 side. Operates to select the output.

As a result, the selector 67 gives the average error of the block (1) to the head pixel of the first display line as the error of the pixel on the left side, and the selector 68 outputs the error of the pixel at the upper left of the block (1). The average error is given to the first pixel of the first display line, the selector 69 gives the average error of the block (1) to the first pixel of the first display line as the error of the pixel immediately above, and the selector 70 gives the error of the upper right pixel. It operates so as to give the average error of the block (2) to the leading pixel of the first display line. By repeating such an operation, as shown in FIG.
The error of each pixel can be calculated using the average error of the seven blocks on the first display line as shown in FIG.

FIG. 9 is an operation time chart (after the second display line) of the error diffusion circuit according to the second embodiment of the present invention. After the second display line, the block (1),
The cumulative error is calculated by giving the average error of (8), (10), and (12), and the final pixel of each display line is divided into blocks (7), (9), (11), and (13). A cumulative error is calculated by giving an average error.

Therefore, in the error calculation of the leading pixel, the latch circuit 60 latches the output of the calculator 58 (average error of the block (1)) based on the latch pulse P1. The other latch circuits 61 to 63 are inoperative. When calculating the error of the final pixel, the latch circuit 63 latches the output of the calculator 58 (average error of the block (7)) based on the latch pulse P4, and the latch circuit 63 operates. The other latch circuits 60 to 62, 64 and 65 are inoperative. At this time, the selector 67 operates so as to select the output of the latch circuit 60 on the input 2 side. Until the final pixel excluding the first pixel, the selector 67 is set to F on the input 1 side.
The selector 6 operates to select the output of the F circuit 71.
8 operates to select the output of the FF circuit 73 on the input 1 side, and the selector 69 operates to select the output of the line memory 59 on the input 1 side. When reaching the final pixel, the selector 70 operates so as to select the output of the latch circuit 66 on the input 2 side.

As a result, the selector 67 gives the average error of the block (1) to the head pixel of the second display line as the error of the pixel on the left side, and the selector 70 outputs the average error of the block (7) as the error of the upper right pixel. It operates to give an error to the last pixel of the second display line. By repeating such an operation, blocks (1), (8), (10) are added to the head pixel of each display line of the display screen as shown in FIG.
And (12) are given the average error to calculate the accumulated error, and the last pixel of each display line is given the average error of the blocks (7), (9), (11) and (13) and accumulated. The error can be calculated.

As described above, in the image processing apparatus according to the second embodiment of the present invention, the distance from the first display line to the fourth display line of the current frame of the display image is increased by 4 times.
The pixel of × 28 is divided into seven blocks, an average error is obtained for each of the blocks (1) to (7), and the average error obtained for each block is the pixel C in the upper left portion, the pixel D immediately above, and the upper right pixel. The error diffused from the partial pixel E is added to the error of each pixel of the first display line of the next frame.

For this reason, since a large error is given to each pixel of the first display line from the beginning, the error shortage of the pixels in the upper part of the display screen should be compensated by the average error of each block (1) to (7). You can As a result, the uneven brightness on the upper part of the display screen is eliminated, and the display quality of the PDP, the liquid crystal display or the like can be improved. Further, in the present embodiment, the pixels of 4 × 16 lines between the first pixel and the four pixels of each display line of the current frame of the display image are divided into four blocks, and this block (1), Calculate the average error for each of (8), (10), and (12),
The average error obtained for each block is added to the error of the first pixel of each display line of the next frame as an error diffused from the pixel B on the left and the pixel C on the upper left.

For this reason, since a large error is given to the leading pixel of each display line from the beginning, the error shortage of the pixel on the left side of the display screen is calculated by the respective blocks (1), (8),
It can be compensated by the average error of (10) and (12).
This eliminates uneven brightness on the left side of the display screen. Further, in the present embodiment, the pixels of 4 × 16 lines between the last pixel of each display line of the current frame of the display image and the four previous pixels are divided into four blocks, and this block ( 7), (9), (11), and (13), the average error is calculated, and the average error calculated for each block is used as the error diffused from the pixel E in the upper right part, and each display line of the next frame is displayed. Is added to the error of the last pixel. Therefore, since a large error can be given to these final pixels from the beginning, the uneven brightness on the right side of the display screen is eliminated.

(3) Comparison between this Embodiment and Prior Art FIGS. 10 to 19 show diagrams for comparing the error diffusion image according to the embodiment of the present invention with the error diffusion image according to the conventional example. . Both figures are duplicates of a photograph taken of an image. FIG. 10A shows a diffused image obtained by the conventional error diffusion circuit, and FIG. 10B shows a diffused image obtained by the error diffusion circuit according to the present invention. In this image, a signal having 256 gradations is subjected to error diffusion processing from the left to the right of the screen, and is displayed in two gradations (white and black images).

In the conventional method, the upper left part (error diffusion start position) of all frames is rounded, and uneven brightness appears. On the other hand, in the present invention, since the error from the other is not diffused in the first frame (at the time of power-on), the upper left portion (error diffusion start position) is rounded, but in the second frame and thereafter, this roundness is It disappears, and it is clear that there is no uneven brightness in the upper left part.

FIG. 11A is an error diffusion image of the conventional system in which error diffusion processing is performed from the top to the bottom of the screen.
1 (B) shows an error diffusion image according to the present invention. Also in this case, in the conventional method, the upper left part of all the frames is rounded and uneven brightness appears. On the other hand, in the present invention, the roundness disappears in all frames, and the uneven brightness is eliminated in the upper left part.

FIG. 12A shows a conventional error diffusion image, and FIG. 12B shows an error diffusion image according to the present invention. This image has been subjected to error diffusion processing so that the gradation is reduced from white to black from the left to the right of the screen, and when it becomes black, the gradation increases again toward white. is there. Also in this case, in the conventional method, the central portions of all the frames are rounded and uneven brightness appears. On the other hand, in the present invention, the constriction disappears after the second frame,
The uneven brightness in the center of the screen is eliminated.

FIG. 13A shows a conventional error diffusion image, and FIG. 13B shows an error diffusion image according to the present invention. This image has been subjected to error diffusion processing so that the gradation is reduced from white to black from the top to the bottom of the screen, and when it becomes black, the gradation increases again toward white. is there. Also in this case, in the conventional method, the central portions of all the frames are rounded and uneven brightness appears. On the other hand, in the present invention, the constriction disappears in all, and the uneven brightness in the central portion of the screen is eliminated.

[0098]

As described above, in the image processing apparatus of the present invention, the error data of the specific pixel in the previous frame is converted into the error of each pixel of the first display line and the first pixel of the second display line of the current frame. By adding it to the data, the brightness of the upper left portion of the display screen (error diffusion start point) can be supplemented. Therefore, since large error data can be given to these pixels from the beginning, the uneven brightness in the upper left portion of the display screen is eliminated.

In another image processing apparatus of the present invention, the average value of the error data obtained for each block is added to the error data of the pixels of the first display line of the next frame to obtain the luminance of the upper left portion of the display screen. Can be supplemented. Therefore, the uneven brightness in the upper left portion of the display screen is eliminated. This greatly contributes to the improvement of the display quality of plasma displays and liquid crystal display devices.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of an error diffusion process according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of an error diffusion circuit according to the first embodiment of the present invention.

FIG. 3 is an operation timing chart (vertical direction) of the error diffusion circuit according to the first embodiment of the present invention.

FIG. 4 is an operation timing chart (horizontal direction) of the error diffusion circuit according to the first embodiment of the present invention.

FIG. 5 is an explanatory diagram of error diffusion processing according to the second embodiment of the present invention.

FIG. 6 is a configuration diagram of an error diffusion circuit according to a second embodiment of the present invention.

FIG. 7 is an operation timing chart when an intra-block error is calculated in the error diffusion circuit according to the second embodiment of the present invention.

FIG. 8 is an operation timing chart at the time of latch writing in the error diffusion circuit according to the second embodiment of the present invention.

FIG. 9 is an operation timing chart (after the second display line) of the error diffusion circuit according to the second embodiment of the present invention.

FIG. 10 is a photographic diagram (part 1) comparing an error diffusion image according to the present invention with an error diffusion image of a conventional example.

FIG. 11 is a photographic diagram (part 2) comparing an error diffusion image according to the present invention with an error diffusion image of a conventional example.

FIG. 12 is a photographic diagram (No. 3) comparing the error diffusion image according to the present invention with the error diffusion image of the conventional example.

FIG. 13 is a photographic diagram (part 4) comparing an error diffusion image according to the present invention with an error diffusion image of a conventional example.

FIG. 14 is a diagram (No. 1) for explaining multi-gradation of the display device according to the conventional example.

FIG. 15 is a diagram (No. 2) for explaining the multi-gradation of the display device according to the conventional example.

FIG. 16 is a configuration diagram of an error diffusion circuit according to a conventional example.

FIG. 17 is an operation timing chart (horizontal direction) of the error diffusion circuit according to the conventional example.

FIG. 18 is an operation timing chart (vertical direction) of the error diffusion circuit according to the conventional example.

FIG. 19 is an explanatory diagram of an error diffusion method according to a conventional example.

[Explanation of symbols]

1, 20, 51 ... Error detection circuit, 2-6, 21, 22,
28-30, 52, 74-76 ... Mask circuit, 7-1
0, 37-40, 77-80 ... Multipliers, 11, 16, 2
3, 41, 53, 54, 81 ... Adder, 12, 24, 5
9 ... Line memory, 13-15, 25-27, 55, 7
1-73 ... Flip-flop circuit, 31-33, 60
... 66 ... Latch circuit, 34-36, 57, 67-70 ...
Selector, 17, 42, 82 ... control unit, 56 ... memory,
58 ... A calculator.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H04N 5/66 101 G06F 15/68 310J

Claims (7)

[Claims] 1. A device for inputting image data of a pixel whose luminance display is N bits and outputting image data of a pixel whose luminance display is M (M <N) bits, wherein N
NM bit error data obtained by subtracting M bit image data from bit image data is obtained, error data of peripheral pixels is added to the error data of the pixel to obtain new error data, and the new error data of the new error data In an image processing apparatus for adding bit data by carry to M-bit image data to correct brightness and diffusing new error data to peripheral pixels, the error data diffused from the peripheral pixels is displayed as the display. An image processing apparatus, wherein error data of a pixel on a final display line of a previous frame of an image is added to error data of a pixel on a first display line of a current frame. 2. As error data diffused from peripheral pixels, error data of a last pixel of a display line before a last display line of a previous frame of the display image is converted to error data of a first pixel of the first display line of the current frame. The image processing apparatus according to claim 1, wherein the image processing apparatus adds the error data. 3. As error data diffused from peripheral pixels, error data of the first pixel of each display line of the current frame of the display image is converted to error data of the last pixel of each display line of the current frame. The image processing apparatus according to claim 1, wherein the image is added. 4. The error data of the last pixel of each display line of the current frame of the display image is used as the error data diffused from the peripheral pixels, and the error data of the first pixel of each display line of the current frame next. The image processing apparatus according to claim 1, wherein the image processing apparatus adds the data. 5. A device for inputting image data of a pixel whose luminance display is N bits and outputting image data of a pixel whose luminance display is M (M <N) bits, wherein said N bit image data The error data of NM bits of the pixel is calculated by subtracting the M-bit image data from the error data, error data of peripheral pixels is added to the error data to obtain new error data, and the new error data is carried. In an image processing device that adds bit data to M-bit image data to correct the brightness and diffuses new error data to peripheral pixels, an arbitrary display line from the first display line of the current frame of the display image. Is divided into blocks, the average value of the error data is calculated for each block, and the average value of the error data calculated for each block is determined by the surrounding pixels. As the error data diffused, the image processing apparatus characterized by adding the error data of the display pixels of the first display line of the next frame. 6. A plurality of pixels between the first pixel and an arbitrary pixel of each display line of the current frame of the display image are divided into blocks, and an average value of error data is obtained for each block, The average value of the error data obtained for each block is added to the error data of the leading pixel of each display line of the next frame as error data diffused from surrounding pixels. Image processing device. 7. A plurality of pixels between the last pixel of each display line of the current frame of the display image and an arbitrary previous pixel are divided into blocks, and an average value of error data is obtained for each block. 6. The average value of the error data obtained for each block is added to the error data of the last pixel of each display line of the next frame as error data diffused from surrounding pixels. The image processing device according to item 1.