JPH09232547A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain sufficient shield effect between a noise sensitive macro and a logic macro, reduce the circuit area, and enable improvement in integration, by constituting an input/output buffer by connecting in parallel a predetermined number of logic circuits made of logic cells. SOLUTION: By providing a perfect SOG structure in which logic cells are arranged on the entire chip surface including an inner region 2A and an I/O buffer region, a noise sensitive macro 3 or the like is arranged at a corner portion 11 which is a conventional I/O buffer region. In a semiconductor integrated circuit of this form, by surrounding other two sides by a power supply line 10A and a ground line 10B, the noise sensitive macro 3 may be sufficiently electrically isolated from a logic macro 4 which is a noise generation source. Thus, since noise generated by the macro 4 is shielded by the power supply line 10A and the ground line 10B, almost all the effects on the noise sensitive macro 3 may be eliminated.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit such as a gate array including a macro such as an analog circuit which is easily affected by noise.

[0002]

2. Description of the Related Art In a general chip configuration of a gate array of this kind, an I / O buffer as an input / output circuit requires a higher driving capability than each internal functional circuit block. The cell configuration is different from that of the I / O buffer, and the former is separately disposed in the inner region and the latter is disposed in the outer I / O region. Naturally, the macro which is a functional circuit block is arranged in the internal area. However, if there is a macro that is easily affected by noise such as an analog circuit, that is, a noise-sensitive macro, the noise-sensitive macro is a macro such as another logic circuit or the like. In some cases, noise was generated or a malfunction occurred due to the influence of noise from the / O buffer or the like.

In this type of conventional semiconductor integrated circuit described in Japanese Patent Application Laid-Open No. Hei 4-30470, as a noise prevention measure, a noise susceptible macro is surrounded by a shield block such as a power supply line or a ground line to be a noise source. Was electrically isolated from the macro.

Referring to FIG. 3, which is a schematic plan view of a conventional semiconductor integrated circuit, the conventional semiconductor integrated circuit has a pad area 8 in which a pad 7 for connection to the outside is arranged on a peripheral portion of a substrate 1. It has an I / O area 6 in which an I / O buffer 5 is arranged and an internal area 2 in which a noise-sensitive macro 3 and a logic macro 4 such as other logic circuits are arranged. Shield block 1 consisting of a shielded power supply line, ground line, etc.
0 is provided.

As described above, since the shield block 10 surrounding the noise-sensitive macro 3 occupies a considerable area,
Many logic cells become unusable around the noise sensitive macro 3. This area cannot be ignored in consideration of the improvement in the degree of integration and the reduction in chip size.

[0006]

In the above-described conventional semiconductor integrated circuit, since the internal area in which the macro is arranged and the I / O area in which the I / O buffer is arranged are separated, the noise of the logic macro is shielded. Therefore, it is necessary to surround the noise-sensitive macro with a shield block, but there is a disadvantage that the occupied area of the shield block is not negligible in view of the trend of improvement in integration and reduction in chip area.

[0007]

SUMMARY OF THE INVENTION A semiconductor integrated circuit according to the present invention includes a noise sensitive macro which is a functional circuit block in which a plurality of identical logic cells are regularly arranged on one main surface of a semiconductor substrate and which is easily affected by noise. In a gate array type semiconductor integrated circuit including: the internal area of the entire logic gate structure in which the logic cell is arranged on the entire surface including the input / output buffer area of the one main surface and the noise sensitive macro is arranged at a corner portion; And a shield wiring arranged so as to surround two sides on the inner area side of the sensitive macro, and the input / output buffer is constituted by a predetermined number of parallel connections of logic circuits each including the logic cell.

[0008]

FIG. 3 shows an embodiment of the present invention.
Referring to FIG. 1 also shown in a schematic plan view with common reference characters / numerals attached to common components, the semiconductor integrated circuit of this embodiment shown in FIG.
And a pad area 8 in which a pad 7 for connection to the outside is arranged in a peripheral portion of the semiconductor device, and a corner portion 11 of a complete SOG (Sea Of Gates) chip including a conventional I / O area spread by logic cells. And an internal area 2A in which the macro 3 is arranged and the logic macro 4 is arranged in other parts.

A terminal is provided with a power supply line 10A connected to the pads 71 and 73 of the pad area 8 and a ground line 10B connected to the pads 72 and 74, and shielded around the two sides on the inner area side of the noise sensitive macro 3. Operate as a block.

These power supply line 10A and ground line 10
B may be composed of a wide aluminum wiring.

As described above, the complete S in which the logic cells including the internal area and the I / O buffer area are arranged on the entire surface of the chip is provided.
With the OG configuration, noise-sensitive macros and the like can be arranged in the corner section 11 which is a conventional I / O buffer area. Therefore, the semiconductor integrated circuit of the present embodiment
By surrounding the other two sides with the power supply line 10A and the ground line 10B, the noise-sensitive macro 3 can be electrically separated sufficiently from the logic macro 4 which is a noise generation limit.
Generated by the power line 10A and the ground line 10B
, The effect on the noise sensitive macro 3 can be almost eliminated.

In addition, since a complete SOG configuration eliminates an I / O buffer area, it is necessary to configure an I / O buffer with logic cells constituting the SOG. In this case, as described in the related art, the I / O buffer requires a higher driving capability than the logic circuit of the internal logic macro. Therefore, in this embodiment, a required I / O buffer function is realized by connecting the logic cells in parallel.

FIG. 2 is a circuit diagram showing the configuration of the I / O buffer according to the present embodiment.
P channel M connected in series between power supply VDD and ground GND
OS transistor Pi (i is 1 to n) and N-channel MO
CMOS gate circuit Gi comprising S transistor Ni
Are constituted by n parallel connections corresponding to the required driving capability.

In operation, each of the CMOS gate circuits Gi outputs a corresponding output signal O to the pad 7 in response to the supply of the complementary input signals H1 and H2 to the gates of the transistors Pi and Ni.

With such a configuration, the semiconductor integrated circuit of the present embodiment can sufficiently separate the logic macro 4 from the noise-sensitive macro 3, reduce the circuit area, and improve the degree of integration. Can be.

[0016]

As described above, in the semiconductor integrated circuit of the present invention, a noise-sensitive macro is arranged at a corner of an internal area of a complete SOG structure in which logic cells are arranged on the entire surface including an input / output buffer area. 2 inside noise sensitive macro
A shield wiring arranged so as to surround the sides, and by forming an input / output buffer with a predetermined number of parallel connections of a logic circuit composed of logic cells, a sufficient shielding effect between the noise-sensitive macro and the logic macro is provided. And the circuit area can be reduced, and the degree of integration can be improved.

[Brief description of drawings]

FIG. 1 is a schematic plan view showing one embodiment of a semiconductor integrated circuit of the present invention.

FIG. 2 is a circuit diagram showing a configuration of an I / O buffer of the semiconductor integrated circuit according to the present embodiment.

FIG. 3 is a schematic plan view showing an example of a conventional semiconductor integrated circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Substrate 2, 2A Internal area 3 Noise sensitive macro 4 Logic macro 5 I / O buffer 6 I / O area 7 Pad 8 Pad area 10 Shield block 10A Power supply line 10B Ground line 11 Corner part G1-Gn CMOS gate circuits N1-Nn , P1 to Pn transistors

Claims (3)

[Claims] 1. A gate array semiconductor integrated circuit including a noise sensitive macro which is a functional circuit block in which a plurality of identical logic cells are regularly arranged on one main surface of a semiconductor substrate and which is easily affected by noise. The logic cell is arranged on the entire surface including the input / output buffer area of the main surface, and the inner area of the whole logic gate structure in which the noise sensitive macro is arranged at the corner portion and the two sides on the inner area side of the noise sensitive macro are surrounded. And a shield wiring disposed on the input / output buffer. 2. The semiconductor integrated circuit according to claim 1, wherein the logic cell comprises first and second conductivity type MOS transistors connected in series between a power supply and ground. 3. The semiconductor integrated circuit according to claim 1, wherein the shield wiring is a power supply line and / or a ground line.