JPH04151863A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To improve device characteristics and increase level of integration, by making a region having CMOS gate cell rows and a region having bipolar CMOS gate cell rows directly face a third region having analog circuit elements, and making the third region directly face a contact region. CONSTITUTION:A contact region 12 having a lot of contacts along the periphery of a semiconductor chip 11 is formed. In the space surrounded by the contact region 12, a first region 13 and a second region 14 are arranged so as to directly face a third region 15 having analog circuit element rows wherein a lot of analog circuit elements are arranged. The first region 13 has a plurality of CMOS gate cell rows, and the second region 14 has a plurality of bipolar CMOS gate cell rows. Hence it is not necessary for wirings to pass a region where wirings are unnecessary and to detour, so that wirings are shortened. Thereby characteristics of a device can be improved, and level of integration can be increased.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention relates to a semiconductor integrated circuit device in which a digital circuit and an analog circuit are integrated on a common semiconductor substrate, and in particular, a semiconductor integrated circuit device having a plurality of P-channel MO5l-transistors and a plurality of N-channel transistors. A first region having a gate cell row in which a large number of single gate cells made up of Mos transistors are arranged, and a gate cell row in which a large number of basic gate cells made up of a plurality of P-channel bipolar MOS transistors and a plurality of N-channel bipolar MOS transistors are arranged. and a third region having an analog circuit element row in which a large number of analog circuit elements for processing analog signals are arranged on a common semiconductor substrate, and a contact formed in a peripheral portion of the semiconductor substrate. The present invention relates to a semiconductor integrated circuit device formed by being integrated in a portion other than a region.

(Prior art) When realizing an analog/digital mixed circuit with a gate array, conventionally the analog circuit is constructed using a unit gate cell, that is, a 1-transistor, a resistor, etc. in a basic cell. The disadvantages are that optimization is difficult and the degree of integration is low. In order to solve such drawbacks, for example, Japanese Patent Application Laid-Open No. 2-102571 discloses a CMOS gate cell array having a plurality of 1111-order gate cells each consisting of a P-channel MO5l-Ransisk and an N-channel MO5+-Ransisk. The arranged first region and the P channel bipolar MO3+
- A second area in which a plurality of bipolar CMOS gate cell rows each having a plurality of unit gate cells each consisting of a Lancisk N-channel bipolar MO5l transistor are arranged, and a third area in which a plurality of analog circuit dedicated elements are arranged in a matrix. A semiconductor integrated circuit device in which a second region is arranged between the first and third regions has been proposed in a semiconductor integrated circuit device in which a second region is arranged between the first and third regions.

FIG. 5 is a plan view diagrammatically showing the structure of such a conventional semiconductor integrated circuit device. A contact region 2 with contacts for inputting and outputting signals is arranged along the periphery of the semiconductor chip 1, and in a space surrounded by the contact region 1, a first region 3 having a CMOS gate cell array is formed. , a second region 4 having a bipolar CMOS gate cell row, and a third region 5 having an analog circuit element row, such that the third region is sandwiched between the first and second regions 3 and 4. It is located in By adopting such a configuration, it is possible to optimize the analog circuit and increase the degree of integration.

(Problems to be Solved by the Invention) In the conventional semiconductor integrated circuit device shown in FIG.
The connection between the first, second and third regions 3.4 and 5 and the contact region 2 can be easily made and the first, third and second regions 3.5 and 4 can be contacted. )? It can also be connected in series with +1 area 2. However, when trying to connect the first region 3 and the third region 5, since the second region 4 exists between them, the wiring 6 must be formed so as to pass through the second region 4, or As shown by the wiring 7, it is necessary to arrange the wiring so as to bypass the second region 4. When the wiring 6 is formed passing through the second region 4, there is a drawback that the use of bipolar CMOS cells in that portion is restricted. Furthermore, if the wiring 7 is formed in a detour manner, the wiring becomes long, which has the drawback of deteriorating the characteristics of the device, and also has the drawback of increasing the wiring area and reducing the degree of integration.

An object of the present invention is to eliminate the drawbacks of a semiconductor integrated circuit device that constitutes two conventional analog-digital mixed circuits, and to eliminate the drawbacks of a semiconductor integrated circuit device that constitutes two consecutive analog-digital mixed circuits, and to It is an object of the present invention to provide a semiconductor integrated circuit device in which connection can be made between the first and second regions without passing through or detouring through a second region having a bipolar CMOS gate cell array.

(Means and effects for solving the problems) The present invention provides a first region having a gate cell row in which a large number of basic gate cells each including a plurality of P-channel MO3+- transistors and a plurality of N-channel MO5l- transistors are arranged; A second area has a gate cell row in which a large number of basic gate cells each consisting of a plurality of P-channel bipolar MO3) transistors and a plurality of N-channel bipolar MO3I- transistors are arranged, and a large number of analog circuit elements for processing analog signals are arranged. In a semiconductor integrated circuit device formed by integrating a third region having a row of analog circuit elements in a common semiconductor substrate in a portion other than a contact region formed in a peripheral portion of the semiconductor substrate, the third region is arranged so as to directly face the contact region, and the first and second regions are arranged so as to directly face at least the third region.

In such a semiconductor integrated circuit device of the present invention, C
Since the first region having the MO3 basic gate cell row and the second region having the bipolar (JO5 basic gate cell row) are arranged directly opposite the third region having the analog circuit element, the first and third areas can be directly connected.

Of course, the first, second, and third regions can be directly connected to the contact 1 to region, and also the second region and the third region can be directly connected. Therefore, wiring is not routed through areas that do not originally require wiring, and the gate cells in this area can be used as effectively as possible.

In addition, since there is no need to detour the wiring, the wiring can be shortened, improving the characteristics of the device, and the area of the wiring area can be reduced.
The degree of integration can be improved accordingly.

(Embodiment) FIG. 1 is a diagrammatic plan view showing the basic configuration of a semiconductor integrated circuit device according to the present invention. A contact region 12 having a large number of contacts is formed along the periphery of the semiconductor chip 11, and in a space surrounded by this contact region, a first region 13 having a plurality of CMOS gate cell rows and a plurality of bipolar CMOS gate cell rows are formed. A second region 14 having a plurality of analog circuit elements is arranged so as to directly face a third region 15 having an analog circuit element row in which a large number of analog circuit elements are arranged. With this configuration,
The first, second and third regions 13.14 and 15 can be connected to the contact region 12 via interconnections 16.17 and 18, respectively. In addition, the first region 13 and the third region 15 can be connected in series to the contact region 12 via the wiring 19, or the second region 14 and the third region 15 can be connected in series to the contact region 12 via the wiring 20. You can connect to. Further, the first region 13, the second region 14, and the third region 15 are connected to the wiring 21.
The contacts 1 to 12 can be connected in series through the contacts 1 to 12. In the present invention, the term "areas directly facing each other" does not mean only a configuration in which nothing exists between them, but also a configuration in which wiring areas, isolation areas, etc. are arranged. be.

FIG. 2 is a diagrammatic plan view showing the structure of an embodiment of a semiconductor integrated circuit device according to the present invention. In this example, input/output to the outside is performed using analog signals, and digital signal processing is performed only internally. therefore,
Contact region 12 arranged around the semiconductor chip 11
A third region 15 in which a plurality of analog circuit element rows are formed is arranged along the entire circumference of the third region 15 to define a closed space. In addition, a plurality of CMOS games 1 to 1 having cell rows
The region 13 is formed in a substantially cross shape, and the portions 13a to 13d protruding outward from the four sides are the third analog region 15.
Place it so that it is directly facing the and the first area 13
four second regions 14 in which bipolar CMOS gate cell rows are formed in the space defined between
Place a to 14d.

In this example, the first region 13 is defined by its protruding portion 13a.
The wiring I9 extending above ~23d connects the contact area 12 via the analog area 15, and connects the first area 13, second area 14, and third area 15 to the wiring 2.
1 can be connected in series to the contact region 12.

FIG. 3 is a diagrammatic cross-sectional view showing the structure of another embodiment of the semiconductor integrated circuit device according to the present invention. In this example, instead of inputting and outputting only analog signals, digital signals are directly inputted and outputted to the first region 13 having the CMOS gate cell array. For this reason, in this example, a closed space is not created in the third region having analog circuit elements, and two third regions 15a and 15b are used.
are vertically separated and arranged so that the first region 13 directly faces the contact region 12. That is, C.M.O.
A first region 13 having S gate cell rows is arranged in a cross shape, and its protruding portions 13a to 13d are contact regions 12.
Place it so that it is directly facing the Bipolar C1'IQ
Four second regions 14a to 14d having s-gate cell rows
This is similar to the embodiment shown in FIG. 2 in that it is arranged within the space defined by the first and third regions.

In this example, the first region 13 can be directly connected to the contact region 12 by the wiring 16 .

Further, the first region 13 and the third region 15 can be connected in series to the contact region 12 via the wiring M19, and the first, second and third regions 15 can be connected via the wiring 21.
Similar to the previous example, 3.14 and 15 can be connected in series to the contact region 12.

FIG. 4 is a diagrammatic sectional view showing the structure of a semiconductor integrated circuit device according to another embodiment of the present invention. In this example, second regions 1.4a to 14d and third regions 15a to 15d are arranged in four corner spaces surrounded by a cross-shaped first region 13 and contacts 1 to 12. . This is effective when there are more direct connections between the first region 13 in which the CMOS gate cell array is formed and the contact region 12 than in the embodiment shown in FIG.

The present invention is not limited to the embodiments described above, and numerous changes and modifications are possible. For example, the first, second
and the arrangement of the third region is such that the first and second regions are
Any arrangement may be used as long as the third region is in contact with the first to third regions. Further, in the above-described embodiment, the second region having the bipolar C0M5 gate cell row was arranged so as to directly face the contact 1 to region, but the second region is arranged so as to be surrounded by the first and second regions. You can also do that.

(Effect of the invention) In the semiconductor integrated circuit device according to the present invention described above,
A first region having an array of CMOS gate cells and a second region having an array of bipolar CMOS gate cells are directly opposed to a third region having an analog circuit element, and the third region is directly opposed to a contact region. Therefore, the wiring connecting the first region and the third region is connected to the second region.
There is no need to pass through the second region and there is no need to detour the second region.
It is possible to increase the utilization efficiency of MOS gate cells and shorten the length of the wiring, which in turn improves the characteristics of the device and reduces the area of the wiring area, which increases the degree of integration. You can improve.

[Brief explanation of drawings]

1 is a diagrammatic plan view showing the basic configuration of a semiconductor integrated circuit device according to the present invention; FIG. 2 is a diagrammatic plan view showing the configuration of an embodiment of the semiconductor integrated circuit device according to the present invention; The figure is a diagrammatic plan view showing the configuration of another embodiment, FIG. 4 is a diagrammatic plan view showing the configuration of another embodiment, and FIG. 5 is a diagram showing the configuration of a conventional semiconductor integrated circuit. FIG. 11...Semiconductor chip 12...Contact region 13, 14.15...First, second, third region 16~
21... Wiring Figure 1 15 Analog key fitting Figure 4

Claims (1)

[Claims] 1. A first region having a gate cell column in which a large number of basic gate cells each composed of a plurality of P-channel MOS transistors and a plurality of N-channel MOS transistors are arranged; a plurality of P-channel bipolar MOS transistors; a second region having a gate cell row in which a large number of basic gate cells each composed of N-channel bipolar MOS transistors are arranged; and a third region having an analog circuit element row in which a large number of analog circuit elements for processing analog signals are arranged. In a semiconductor integrated circuit device formed by integrating on a common semiconductor substrate in a portion other than a contact region formed in a peripheral portion of the semiconductor substrate, the third region is arranged so as to directly face the contact region. A semiconductor integrated circuit device, wherein the first and second regions are arranged so as to directly face at least the third region. 2. Claim 1, characterized in that a part of the first region is arranged so as to directly face the contact region.
The semiconductor integrated circuit device described above.