JPH09232538A - Semiconductor integrated circuit device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform planarization by selectively arranging an insulating film in a low-altitude portion of a substrate having a step. SOLUTION: A memory array portion in which a stack capacitor 409 is formed has an altitude approximately 0.5μm higher than that of a lower portion (peripheral circuit portion). After an SOG film portion applied on a semiconductor substrate main surface having a relatively low is exposed to light to form an exposed SOG film 417, an unexposed portion is removed using an alkaline solution. A via-hole is formed in a desired part of an SOG film 418 and then a metal wiring 419 is formed, thus providing a multilayer wiring structure. In this case, since the semiconductor substrate main surface on which the SOG film 418 is formed is substantially planarized in the memory array portion and the peripheral circuit portion, easy formation of a pattern at an M1 wiring spacing of 1μm pitch is enabled.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to the semiconductor technical field,
In particular, a dynamic random access memory (DRAM: Dynamic) represented by a memory device.
The present invention relates to a technique effectively applied to a Random Access Memory (IC) IC.

[0002]

2. Description of the Related Art A DRAM IC is a memory array portion (a portion where a plurality of memory cells are regularly integrated) on one semiconductor substrate and an input / output circuit (I / O) located around the memory array portion. ) And the like are configured in the peripheral circuit section.

Recently, along with the high integration and large capacity of this DRAM / IC, the memory cell structure has been three-dimensionally typified by a DRAM having a stack type capacitor. In such a DRAM, an elevation difference inevitably occurs on the surface of the base between the memory array section and its peripheral circuit section in the manufacturing process. In order to successively form fine wiring patterns on a semiconductor substrate having this difference in elevation, that is, a step, the focus margin in the photolithography process and the processing mark in the dry etching process are used.
In order to secure the gin, it is necessary to flatten the semiconductor substrate having the step.

Conventional planarization techniques include chemical mechanical polishing (CMP: Chemical Mechanical).
Although a typical technique is the l-Pulsing technique, there remain problems in terms of mass productivity and reproducibility (film flattening of the entire semiconductor wafer).

Another method is disclosed in JP-A-6-97159.
As disclosed in Japanese Patent Laid-Open Publication No. 2003-242242, there has been considered a technique for forming a relatively low interlayer insulating film in a peripheral circuit portion to be thick by using a photolithography technique to achieve planarization.

[0006]

The technique disclosed in the above publication will be described below with reference to the drawings including consideration of the inventors.

The flattening technique disclosed in the above publication is performed by the process flow shown in FIG. That is, the process flow is such that an underlayer of CVD-SiO2 is formed on the main surface of a semiconductor substrate composed of a memory array section having a relatively high main surface and a peripheral circuit section having a relatively low main surface. Step 101 of forming, step 102 of depositing a BPSG (boron phosphorus silicate glass) film, which is the main component of the planarization film, on the main surface of the semiconductor substrate, step 103 of forming an organic photoresist pattern for leaving the resist film only in the peripheral circuit portion, Dry etching step 104 of the BPSG film in the memory array section
Then, a resist removing step 105 on the peripheral circuit section, a surface cleaning step 106, and a step 107 of forming a substantially flat interlayer insulating film by eliminating the elevation difference between the memory array section and the peripheral circuit section by BPSG reflow. Such a series of steps requires steps such as resist application, exposure, and development because etching processing using an organic photoresist is performed, and the steps are more complicated than the CMP technique described above.

Further, in the dry etching step 104 of the BPSG film of the memory array portion, the BPSG of the memory array portion is
It is necessary to precisely control the etching stop of the film.

Further, the processing temperature for performing the BPSG reflow is higher than 800 degrees. This process temperature is much higher than the melting point of aluminum, which is 660 degrees, and it is not possible to apply a low-resistance wiring using aluminum to the lower layer of such a BPSG film. Further, when the silicon (semiconductor region) and the metal have a structure in direct contact with each other, the contact portion is silicidized by the reflow processing temperature to have a high resistance, which is not applicable.

The problem to be solved by the present invention is a simplified etching process which does not use an organic photoresist forming step or a dry etching step on a main surface portion of a semiconductor substrate having a relatively low altitude, and has a high reliability at a low temperature. The purpose is to provide a planarization insulating film.

One object of the present invention is to provide a novel semiconductor integrated circuit device which enables fine wiring on the main surface of a semiconductor substrate having a difference in elevation.

Another object of the present invention is to provide a novel semiconductor integrated circuit device having a memory array.

Another object of the present invention is to provide a novel semiconductor integrated circuit device having a memory array having a laminated capacitor.

Another object of the present invention is to provide a novel method of manufacturing a semiconductor integrated circuit device which enables fine wiring on the main surface of a semiconductor substrate having a difference in elevation.

Another object of the present invention is to provide a method of manufacturing a novel dynamic random access memory capable of fine wiring.

Still another object of the present invention is to provide a novel semiconductor device having a simplified process.

[0017]

According to one aspect of the present invention, a plurality of semiconductor element regions are formed on a main surface of a semiconductor substrate, and multi-layer wirings are formed on the main surface of the substrate with an interlayer insulating film interposed therebetween. A semiconductor integrated circuit device, wherein a first wiring portion and a second wiring portion are respectively formed on a first main surface portion and a second main surface portion of the base main surface, and the first wiring portion is the second wiring portion. An interlayer insulating film having a height difference higher than that of the first wiring part and the interlayer insulating film selectively formed on substantially the entire second wiring part and selectively provided with the upper part of the first wiring part and the interlayer insulating film. Another insulating film which is continuous with the upper part of the two wiring parts and has a flat surface is formed, and a plurality of upper wirings are formed on the other insulating film.

Further, the present invention is a semiconductor integrated circuit device having a plurality of semiconductor element regions formed on a main surface of a semiconductor substrate, and multilayer wiring formed on the main surface of the substrate via an interlayer insulating film. A memory array forming a capacitor is formed on the first main surface portion of the base main surface, peripheral circuits of the memory array are formed on the second main surface portion of the base main surface, and the main surface portion of the memory array is An interlayer insulating film having a height difference higher than that of the main surface of the peripheral circuit and having a photosensitized interlayer insulating film selectively formed on almost the entire main surface of the peripheral circuit,
Another insulating film having a flat surface is formed on the main surface of the memory array and on the peripheral circuit main surface where the interlayer insulating film is selectively provided. In, a plurality of upper wirings are formed.

Further, one of the present invention is a semiconductor integrated circuit device in which a plurality of semiconductor element regions are formed on a main surface of a semiconductor substrate, and multilayer wiring is formed on the main surface of the substrate with an interlayer insulating film interposed therebetween. A memory array forming a capacitor having a laminated structure is formed on a first main surface portion of the base main surface, and a peripheral circuit of the memory array is formed on a second main surface portion of the base main surface, The main surface portion of the memory array has a higher elevation difference than the main surface portion of the peripheral circuit, and a photo-processed interlayer insulating film is selectively formed on substantially the entire main surface portion of the peripheral circuit. And another insulating film which is continuous with the upper surface of the peripheral circuit main surface where the interlayer insulating film is selectively provided and has a flat surface, and a plurality of upper wirings are formed on the other insulating film. What is done And it features.

Further, one of the present invention is a semiconductor integrated circuit device in which a plurality of semiconductor element regions are formed on a main surface of a semiconductor substrate, and multilayer wiring is formed on the main surface of the substrate with an interlayer insulating film interposed therebetween. And a plurality of MISFETs on each of the first main surface portion and the second main surface portion of the main surface of the semiconductor substrate.
Forming a first wiring and a second wiring having a relative difference in elevation on the first main surface portion and the second main surface portion of the base main surface, the first wiring and the second wiring, respectively. The step of applying a photosensitive insulating film, the photosensitive insulating film is exposed to light to form an interlayer insulating film selectively subjected to a photosensitive process on the second wiring having a relatively high altitude. A step of forming another insulating film which is continuous with the first wiring upper part and the second wiring upper part where the interlayer insulating film is selectively provided and has a flat surface on the other insulating film. A method of manufacturing a semiconductor integrated circuit device, comprising: forming an upper wiring pattern.

Further, one of the present inventions is that
A method of manufacturing a random access memory, comprising: a MIS having a memory cell formed on a first main surface portion of a main surface of a semiconductor substrate.
A step of arranging a plurality of FETs and a plurality of MISFETs forming a peripheral circuit on the second main surface portion of the semiconductor substrate main surface, a lower electrode forming a memory cell, a dielectric film on the first main surface portion of the base main surface And arranging a plurality of capacitors for the memory cell formed of the upper electrode, and applying a photosensitive insulating film on the first main surface part and the second main surface part after arranging the capacitors. Subjecting the photosensitive insulating film to an exposure process to form an interlayer insulating film selectively subjected to a photosensitive process on a second main surface portion having a relatively high altitude; A step of forming another insulating film continuous with an upper part of the second wiring where the interlayer insulating film is selectively provided and having a flat surface, and a step of pattern-forming an upper wiring on the other insulating film. It is characterized by consisting of.

Further, another aspect of the present invention is a method of manufacturing a semiconductor device, wherein an interlayer insulating film is formed on a main surface of a substrate on which a semiconductor element is formed and a wiring layer is formed on the interlayer insulating film. A photosensitive silicon-containing film is formed on the main surface of the substrate on which the device is formed, and the film is exposed to ultraviolet rays partially to remove the film in the unexposed area by etching, and the film is reformed on the main surface of the substrate at a relatively low altitude. Is performed to selectively form an interlayer insulating film made of a silicon oxide film.

The basic idea of the present invention is that an interlayer insulating film is selectively provided on a relatively low principal surface portion of a semiconductor substrate principal surface without using a high temperature process, and a semiconductor substrate principal surface is formed. The height of the main surface is almost the same as that of the main surface. The specific formation of the interlayer insulating film is as follows. After forming a film of a photosensitive silicon composition, short wavelength ultraviolet light is irradiated to a portion having a low altitude, and a film of an unirradiated portion is removed by using a removing liquid and left. The film is heated to modify the film in an atmosphere containing oxygen. Then, this modified film is used as it is as an interlayer insulating film.

[0024]

BEST MODE FOR CARRYING OUT THE INVENTION An example of a flattening process flow in which the present invention is applied to a dynamic random access memory (DRAM) will be specifically described with reference to FIG.

First, the transistor (transfer MISF
ET) and stacked capacitors (information storage capacitors)
A CVD-SiO ₂ film forming step 301 is performed on the substrate on which the film has been formed. Thereafter, a polysilazane-based inorganic SOG film forming step 302 is performed. In this step, a chemical solution containing a silazane polymer in a xylene solvent is spin coated,
Baking using a hot plate is performed in the atmosphere at 0 ° C. for 3 minutes. Although this baking removes the organic solvent, it should be noted that if a temperature higher than 100 ° C. is used, the patterning will not be successful.

Next, short wavelength ultraviolet light (193 nm) is irradiated using a reticle having a chrome light shield (step 3).
03). Then, in a wet etching step 304 using an alkaline aqueous solution (resist developing solution), the SOG film is patterned so as to leave the film in a low altitude portion. Then, the baking process 30 of the remaining SOG film is performed.
5, the film reforming process 306 is performed at 400 ° C. in an oxygen atmosphere with water vapor added to form a dense silicon oxide film.

In the film modifying process 306, a gas containing nitrogen is used to form plasma for processing.
A silicon nitride film is obtained by heating to 600 ° C. or higher and processing in a nitrogen or ammonia gas atmosphere. This nitride film can be used as a processing stopper layer at the time of dry etching or chemical mechanical polishing (CMP) processing, and also as a passivation film for preventing moisture from entering.

Next, one embodiment of the present invention will be described in more detail with reference to process sectional views. 2 to 10 show DRA.
FIG. 6 is a cross-sectional view of a semiconductor substrate in a manufacturing process of M.

First, as shown in FIG. 2, an n-type well 402, a p-type well 403, B are formed on a silicon semiconductor substrate 401.
The P layer 404 was sequentially formed. Element isolation is well known LOCO
S separation technology is applied. That is, the element isolation is performed by LOCOS (Local Oxidation of Silicon) oxide film 40 formed by selectively oxidizing the silicon semiconductor substrate 401.
It consists of 5. Then, after forming the LOCOS oxide film, the polysilicon gate electrode 4 is formed through a gate oxide film (not shown).
06 is formed. Then, the silicon oxide films 407 and 408 are covered so as to cover the polysilicon gate electrode 406.
Are formed using the CVD technique. Further, a stack type capacitor 409 forming a memory cell is formed on the main surface of the p well 403. The electrodes of the stack type capacitor 409 have a fin structure, and a lower electrode 409a having a fin structure made of, for example, polysilicon is connected to an n + semiconductor region (not shown) selectively formed in the p well 403. , A dielectric film formed on the surface of the lower electrode 409a, for example, a silicon nitride film (SiN)
And an upper electrode 409b made of polysilicon formed on the surface of the dielectric film.

Subsequently, a silicon oxide film 410 was deposited, a BPSG film 411 was formed by chemical vapor deposition (CVD), and then heat treatment was performed in nitrogen at 880 ° C. for 10 minutes. A sectional view of the semiconductor substrate in this state is shown in FIG.

The memory array portion (also referred to as a memory mat portion) in which the stack type capacitor 409 is formed has a height of about 0.5 μm higher than a lower portion (peripheral circuit portion) on the right side of the drawing. That is, in the main surface of the semiconductor substrate that has undergone the above steps, the first wiring portion (first main surface portion) that constitutes the memory array and the second wiring portion (second main surface portion) that constitutes the peripheral circuit are formed. Can make a difference in elevation.

Subsequently, as shown in FIG. 3, a metal wiring 412 made of a refractory metal material such as tungsten is used.
To form The metal wiring 412 is connected to, for example, an n + semiconductor region (source region and drain region) provided in the p well 403 through a through hole provided in the BPSG film 411 in the peripheral circuit portion. Also,
Although not shown in the figure, the metal wiring 412 is formed in the n-well 4
02 is connected to the p + semiconductor region (source region and drain region).

After forming the metal wiring 412, a plasma silicon oxide film 413 is formed and then a polysilazane-based inorganic SOG (Spin on Glass) 414 is formed. The film thickness was adjusted by adjusting the rotation speed so that the finished film thickness of the flat portion was 0.5 μm in consideration of the step difference. Since a large amount of organic solvent (xylene) is contained in the film as applied, it was baked on a hot plate at 80 ° C. for 3 minutes. If the baking temperature exceeds 100 ° C., the pattern forming characteristics deteriorate.

Next, as shown in FIG. 4, a light shield 415 is provided.
Was used to irradiate short wavelength ultraviolet light 414. This process is A
A reticle with a chrome shield was used with an rF laser source. The exposure amount was 100 mJ / cm ² . When a sufficient exposure amount is obtained, as shown in FIG. 5, the entire SOG film irradiated with ultraviolet rays causes a cross-linking reaction almost uniformly, and the photosensitive S
An OG film 417 is obtained.

After forming the photosensitive SOG film 417 by exposing a part of the SOG film (the SOG film part covering the main surface of the semiconductor substrate having a relatively low altitude),
The unexposed portion was removed with an alkaline solution which is usually used for developing a resist. The semiconductor substrate with the unexposed SOG film removed is shown in FIG.

Subsequently, in order to remove water, it was baked at 150 ° C. for 3 minutes using a hot plate. Then, the temperature of this substrate was raised to 400 ° C. in dry nitrogen, and the gas was switched to oxygen. 0.1g at the same time in this gas
/ Min of pure water was vaporized and added. After treating for 15 minutes, the nitrogen was switched to dry nitrogen again, the same treatment for 15 minutes was performed, and the temperature was returned to room temperature and taken out. The cross section of this sample is shown in FIG. As shown in this figure, the reflow phenomenon was observed in the process of heating in the baking and nitrogen. As shown in FIG. 8, an SOG film 418 is further formed on the sample in this state. Then, a via hole (that is, a through hole) was formed in a desired portion over the SOG film 418, and then a metal wiring 419 was formed to obtain a multilayer wiring structure shown in FIG. The metal wiring 419 (M1 wiring) is made of, for example, TiN.
It has a -Al-TiN laminated structure and is composed of a metal material mainly containing Al. The pattern formation of the M1 wiring is executed by a photolithography technique using ordinary projection exposure. At this time, since the main surface of the semiconductor substrate on which the SOG film 418 is formed is substantially flattened in the memory array section and the peripheral circuit section, the pattern of the M1 wiring can be formed, and the wiring interval and the pitch of 1 μm can be easily formed. Can be patterned.

Further, an interlayer insulating film 420 made of BPSG
After forming the via hole, the tungsten plug 421 is formed by the etch back method, and the metal wiring 42 is formed.
2 (M2 wiring) was formed. Like the metal wiring 419, the metal wiring 422 is made of, for example, a metal material having a TiN-Al-TiN laminated structure.

Further, a protective film 423 was formed to obtain an integrated circuit having the structure shown in FIG. The protective film 423 may be, for example, a laminated film of a plasma TEOS film and an organic SOG film.

As described above, according to the present invention, wide area flattening can be realized by a simple process of ultraviolet light irradiation and wet treatment.

Next, the modification treatment of the SOG film of the present invention will be described in more detail. In FIG. 11, polyhydrosilazane SOG was spin-coated on a Si substrate and then at 120 ° C. for 3 minutes.
It is an infrared absorption spectrum (501) of the film baked at 170 ° C. for 3 minutes. There are 2 N-H bonds at 3371 cm- ^1.
A Si-H bond is recognized at 164 cm- ¹ . Besides this, 2
The absorption of -C-H of the organic solvent is recognized at 935 and 2836 cm-1. Put this sample in a quartz annealing furnace,
The temperature was raised in nitrogen to 400 ° C. over 25 minutes. After 5 minutes, the atmosphere was switched to steam-added oxygen. The amount of water vapor added was 0.1 / min by controlling the liquid flow rate, and was added as water vapor by a vaporizer. After treating for 15 minutes in this steam-added oxygen, switching to nitrogen again, treatment for 10 minutes, cooling to room temperature, and taking out. As a result of measuring the film thickness, it was confirmed that a 500 nm silicon oxide film was formed. Further, the infrared absorption spectrum (601) shown in FIG. 12 was obtained. 3649Cm- ¹ to the absorption of Si-OH, also 3386Cm- ¹ is N-H bond is observed slightly, as shown in Table 1 0.5% HF (1/99
It was also confirmed from the etching rate with respect to the HF) aqueous solution that a dense film was formed.

[0041]

[Table 1]

The film thickness of this film is determined by the number of rotations during spin coating. This characteristic is shown in FIG. FIG. 13 shows characteristic curves of the SOG chemical liquid of xylene solvent and the SOG chemical liquid of nonane solvent, respectively, and both obtained substantially the same rotation speed-dependent characteristic.

Further, FIG. 14 shows the wet etching characteristics of the film after the SOG film modification. The films modified at 400 ° C. and the film modified at 450 ° C. are shown.
As a result of performing step etching, a dense film of 21.2 nm / min was formed for the film modified at 400 ° C. and 14.8 nm / min for the film modified at 450 ° C. I understood. The etching characteristics of the silicon thermal oxide film (Th-SiO) are shown in FIG. 14 for comparison with the modified film.

The polyhydrosilazane has been described so far, and its basic molecular structure is as shown in FIG. It has been described that n is a natural number and has a molecular weight of about 2000. In addition to this, a ladder-type polyhydrosiloxane SOG having the basic molecular structure shown in FIG.
Polyhydrosiloxane S having basic molecular structure shown in 7
It may be OG. However, polysilazane shown in FIG. 17 is most convenient for effectively performing the film modification treatment by adding steam.

Next, the photosensitivity and pattern formation characteristics of the polysilazane SOG film will be described in more detail. FIG. 18 shows the ultraviolet wavelength dependency of the transmittance of the hydrosilazane SOG film spin-coated and baked at 80 ° C. The light source has a wavelength of 3
65 nm i-line, 300 nm mercury lamp, 248 nm
KrF laser of 193 nm and ArF laser of 193 nm were used. It can be seen that there is an absorption edge near 220 nm and absorption is on the shorter wavelength side.

Next, FIG. 19 shows the dependence of the SOG film thickness and the etching rate on the exposure dose when using a 193 nm ArF laser. In FIG. 19, 1301 is a residual film characteristic curve of hydrosilazane SOG, and 1302 is an etching characteristic curve of hydrosilazane SOG. The initial SOG film thickness was 350 nm. The etching solution is tetramethylammonium hydroxide (TMA
H) as an aqueous solution. A change was observed at 10 to 30 mJ / cm 2, and when the exposure amount exceeded the threshold, an etching rate of about 300 nm / min was obtained.

Next, FIG. 20 shows how the pattern forming regions are distributed depending on the conditions of the exposure amount and the alkali solution concentration. When the condition that the amount of exposure is large and the concentration of the alkaline solution is more than the appropriate concentration is satisfied, a pattern is formed (negative pattern) on the exposed portion, and conversely, either the amount of the exposure or the concentration of the alkaline solution is formed. If is not satisfied, no pattern is formed. In this intermediate region, there is a region where a positive pattern can be formed. D ₀ represents the threshold of alkaline solution concentration.

Next, FIG. 21 shows the dependence of the etching rate on the alkali developer concentration when an exposure amount of 100 mJ / cm ² was applied. When the concentration of TMAH in the liquid was 5% or more, an etching rate of about 300 / min was obtained.

Next, the characteristic evaluation results of the film formed by the process flow shown in FIG. 1 will be described. Here, the SOG of the present invention is indicated as NEB (None Etch Back) -SOG. For reference, plasma silicon oxide film, organic S
The values of the OG film and Th-SiO (silicon oxide film by thermal oxidation) are also included in part. The film thickness can be controlled by the rotation speed as shown in FIG. Uniformity of film thickness is 3.5%
Is good at. The stress is on the order of 1 × 10 ⁹ dyn / cm ²
Although it is slightly higher than the organic film, the crack limit is 1 micrometer. The wet etching rate is about 14 to 22 nm / min, which is about twice as high as that of the plasma silicon oxide film, which is within the allowable range of the manufacturing process and there is no problem.

FIG. 22 is a plan view showing a DRAM chip 1601 to which the planarization insulating film of the present invention is applied. High altitude memory array (memory mat) units 1603 and 160
Peripheral circuit portion 1602 excluding 4, 1605 and 1606
A flattening insulating film (interlayer insulating film) was formed by the method described above. That is, the exposed SOG film is selectively formed on the surface of the peripheral circuit portion 1602. This SOG
By forming the film, a flat interlayer insulating film can be formed on the main surface of the semiconductor substrate in which there is no difference in elevation between the memory array section and the peripheral circuit section. Therefore, the metal wiring formed on the interlayer insulating film has no obstacle, and the wiring pattern rule (wiring interval, etc.) on the memory array section and the peripheral circuit section can be the same, and high-density wiring and A highly reliable DRAM can be obtained.

Next, a DR having a crown type capacitor
An embodiment of the present invention applied to AM will be described.

FIG. 23 is a sectional view of a manufacturing process of a DRAM having a crown type capacitor capable of ensuring a large storage capacity. Here, the n-type well 1702, p is formed on the substrate 1701.
A mold well 1703 is formed, followed by a BP layer 1704,
A LOCOS 1705, a polysilicon electrode 1706, a silicon oxide film 1707, a silicon oxide film 1708, and a crown capacitor lower electrode 1709 are sequentially formed. The lower electrode 1709 is made of a polysilicon film or a laminated metal of TiN-W. This lower electrode 170
9A and 9B, a capacitor insulating film 1710 is formed. Although the capacitor insulating film 1710 is a tantalum oxide film,
If a ferroelectric thin film such as T, STO, or PZT is applied, a capacitor having a larger capacity and resistant to noise and soft error can be obtained. Subsequently, a crown capacitor upper electrode 1711 and a silicon oxide film 1712 are formed. At this stage, there is a large difference in altitude between the array portion of the memory cell having the crown type capacitor and its peripheral circuit portion.
Therefore, the main surface of the semiconductor substrate was flattened in the same manner as in the above-mentioned embodiment. That is, a light-sensitive SOG film is formed by applying a photosensitive SOG film on the main surface of the semiconductor substrate.
193 nm through transparent substrate with 4 and 1715
Of short wavelength ultraviolet light 1717 was irradiated. Wet treatment was performed, and at this time, both fine and wide areas including a pattern of 0.2 μm were formed at the same time. As described above, the present invention supports wide area flattening including a fine region. As shown in FIG. 23, the SOG film which has been exposed is also embedded in the concave portion of the crown capacitor upper electrode 1711 to flatten the entire memory array portion.

As described above, the interlayer insulating film formed on the relatively low main surface for flattening of the present invention is a dense film and is selectively patterned by a simple method of irradiation with ultraviolet light. Can be formed. Therefore, a groove or a hole is formed in the interlayer insulating film.
So called damascene wiring,
A phase shift reticle in which the interlayer insulating film of the present invention is applied to a shifter, a multilayer wiring in which the interlayer insulating film of the present invention is applied instead of a metal dummy wiring to perform planarization, the interlayer insulating film of the present invention and a chemical machine. The technique of the present invention can also be applied to planarization by polishing (CMP) and embedding of an insulator for trench type element isolation.

[0054]

According to the conventional method, the BPSG film is dry-etched by using the photoresist pattern as a mask to remove the unnecessary photoresist, and then the flattening process is performed at a high temperature over 800 ° C.

On the other hand, according to the specific method of the present invention, the steps of dry etching and photoresist removal can be omitted, and the process temperature can be suppressed to 450 ° C. or lower, so that the production cost can be reduced. It has become possible to manufacture a highly reliable semiconductor device. Therefore, the following effects are obtained.

(1) According to the present invention, a high-reliability flattening insulating film which is dense at low temperature is formed by a simplified etching process which does not use an organic photoresist forming step or a dry etching step on a low-elevation main surface portion of a semiconductor substrate. Can be provided.

(2) According to the present invention, it is possible to obtain a highly reliable semiconductor integrated circuit device in which fine wirings are formed on the main surface of a semiconductor substrate having a difference in elevation.

(3) According to the present invention, it is possible to obtain a high density semiconductor integrated circuit device having a memory array.

(4) According to the present invention, it is possible to easily provide a semiconductor integrated circuit device having a memory array provided with a capacitor having a highly reliable laminated structure.

(5) According to the present invention, it is possible to obtain a semiconductor integrated circuit device which enables fine wiring on the main surface of a semiconductor substrate having a difference in elevation.

According to the present invention, a dynamic random access memory having a fine wiring structure, particularly a memory cell having a fin type or crown type stacked capacitor can be easily obtained.

[Brief description of drawings]

FIG. 1 is a flow chart of forming a flattening interlayer insulating film according to the present invention.

FIG. 2 is a main-portion cross-sectional view of the semiconductor integrated circuit device in the manufacturing process of the embodiment of the present invention.

3 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device, following FIG.

FIG. 4 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device, following FIG.

5 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device, following FIG.

FIG. 6 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device, following FIG.

7 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device, following FIG.

8 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device, following FIG.

9 is a main-portion cross-sectional view in the manufacturing process of the semiconductor integrated circuit device, which is subsequent to FIG. 8;

10 is a main-portion cross-sectional view in the manufacturing process of the semiconductor integrated circuit device, which is subsequent to FIG. 9;

FIG. 11 is a diagram showing an infrared absorption spectrum of a formed film after baking an SOG film in the present invention.

FIG. 12 is a diagram showing an infrared absorption spectrum of a formed film after curing an SOG film in the present invention.

FIG. 13 is a diagram showing the coating rotation speed dependence of the film thickness of the SOG film in the present invention.

FIG. 14 is a diagram showing the etching dependence of the SOG film in the present invention.

FIG. 15 is a view showing a molecular structure of polyhydrosilazane SOG which is an embodiment of the present invention.

FIG. 16 is a view showing a molecular structure of a ladder-type polyhydrosiloxane SOG which is another embodiment of the present invention.

FIG. 17 is a view showing a molecular structure of polyhydrosiloxane SOG which is another embodiment of the present invention.

FIG. 18 is a diagram showing ultraviolet light transmission characteristics of the SOG coating film of the present invention.

FIG. 19 is a diagram showing the exposure dose dependency of the SOG coating film thickness and etching rate in the present invention.

FIG. 20 is a diagram showing SOG film pattern formation characteristics.

FIG. 21 is a diagram showing the dependence of the etching rate on the alkali developer concentration.

FIG. 22 is a plan view showing a pattern formation region of a DRAM which is an embodiment of the present invention.

FIG. 23 is a sectional view of a manufacturing process of a DRAM having a crown-type capacitor which is an embodiment of the present invention.

FIG. 24 is a flow chart of forming a conventional planarization interlayer insulating film.

[Explanation of reference numerals] 101 ... CVD-SiO ₂ film forming step, 102 ... BPS
G film deposition step, 103 ... Photoresist pattern forming step, 104 ... Dry etching step, 105 ... Resist removing step, 106 ... Surface cleaning step, 107 ... BPSG reflow step, 201 ... Substrate, 202 ... Stepped device formation Part 203 ... BPSG film, 204 ... Photoresist, 301 ... CVD-SiO2 film forming step, 302 ...
SOG film forming step, 303 ... Short wavelength ultraviolet light irradiation step, 3
04 ... Wet etching step, 305 ... Baking step,
306 ... Membrane reforming process step, 401 ... Substrate, 402 ... N-type well, 403 ... P-type well, 404 ... BP layer, 405
LOCOS, 406 ... Polysilicon electrode, 407 ... Silicon oxide film, 408 ... Silicon oxide film, 409 ... Capacitor, 410 ... Silicon oxide film, 411 ... BPSG
Films, 412 ... Metal wirings, 413 ... Plasma silicon oxide films, 414 ... SOG films, 415 ... Light shields, 416 ... Short wavelength ultraviolet light blocking, 417 ... Photosensitive SOG films, 418 ... SO
G film, 419 ... Metal wiring, 420 ... Silicon oxide film, 4
21 ... Metal plug, 422 ... Metal wiring, 423 ... Insulating film. 1201 ... Hydrosilazane SOG ultraviolet light transmittance characteristic curve, 1301 ... Hydrosilazane SOG residual film characteristic curve, 1302 ... Hydrosilazane SOG etching characteristic curve, 1401 ... Negative pattern forming region, 1402 ...
Areas where the film remains and no pattern is formed, 1403 ...
Areas where no film remains and no pattern is formed, 1404 ...
Positive pattern forming area, 1501 ... Etching rate characteristic curve, 1601 ... Chip, 1602 ... Photosensitive insulating film forming area, 1603 ... Memory mat area, 1604 ... Memory mat area, 1605 ... Memory mat area, 1701
... substrate, 1702 ... n-type well, 1703 ... p-type well, 1704 ... BP layer, 1705 ... LOCOS, 170
6 ... Polysilicon electrode, 1707 ... Silicon oxide film, 1
708 ... Silicon oxide film, 1709 ... Capacitor lower electrode, 1710 ... Capacitor insulating film, 1711 ... Capacitor upper electrode, 1712 ... Silicon oxide film, 1713 ... Shading body, 1714 ... Shading body, 1715 ... Shading body, 1716
... transparent substrate, 1717 ... short wavelength ultraviolet light, 1718 ... exposed SOG film.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Nobuyoshi Kobayashi 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Hitachi, Ltd. Semiconductor Division

Claims (26)

[Claims] 1. A semiconductor integrated circuit device comprising a plurality of semiconductor element regions formed on a main surface of a semiconductor substrate, and multilayer wiring formed on the main surface of the substrate with an interlayer insulating film interposed therebetween. A first wiring portion and a second wiring portion are formed on the first main surface portion and the second main surface portion, respectively, of the first surface.
The wiring portion has a height difference higher than that of the second wiring portion, and a photosensitized interlayer insulating film is selectively formed on almost the entire second wiring portion, and the upper portion of the first wiring portion and the interlayer insulating film are formed. Is continuous with the upper part of the selectively provided second wiring part, another insulating film having a flat surface is formed, and a plurality of upper wirings are formed on the other insulating film. Semiconductor integrated circuit device. 2. The semiconductor integrated circuit device according to claim 1, wherein the photosensitized interlayer insulating film is formed of a photosensitive silicon-containing film irradiated with ultraviolet rays. 3. A semiconductor integrated circuit device comprising a plurality of semiconductor element regions formed on a main surface of a semiconductor substrate, and multilayer wiring formed on the main surface of the semiconductor substrate with an interlayer insulating film interposed therebetween. A memory array forming a capacitor is formed on the first main surface portion of the surface, a peripheral circuit of the memory array is formed on the second main surface portion of the base main surface, and the main surface portion of the memory array is formed of the peripheral circuit. An interlayer insulating film having a height difference higher than that of the main surface portion is selectively formed on substantially the entire peripheral circuit main surface portion, and an upper portion of the main surface portion of the memory array and the interlayer insulating film are selectively provided. Another integrated film which is continuous to the upper part of the peripheral circuit main surface portion and has a flat surface is formed, and a plurality of upper wirings are formed on the other insulating film. Circuit device. 4. The semiconductor integrated circuit device according to claim 3, wherein the photosensitized interlayer insulating film is formed of a photosensitive silicon-containing film irradiated with ultraviolet rays. 5. A semiconductor integrated circuit device having a plurality of semiconductor element regions formed on a main surface of a semiconductor substrate, and multilayer wiring formed on the main surface of the semiconductor substrate with an interlayer insulating film interposed therebetween. A memory array forming a capacitor having a laminated structure is formed on a first main surface portion of the surface, a peripheral circuit of the memory array is formed on a second main surface portion of the base main surface, and the main surface portion of the memory array is An interlayer insulating film having a height difference higher than that of the main surface of the peripheral circuit and having a photosensitized interlayer insulating film is selectively formed on substantially the entire main surface of the peripheral circuit, and the upper surface of the main surface of the memory array and the interlayer insulating film are selected. And a plurality of upper wirings are formed on the other insulating film, which is continuous with the upper surface of the peripheral circuit main surface portion and has a flat surface. Semiconductor integration Road devices. 6. The semiconductor integrated circuit device according to claim 5, wherein the photosensitized interlayer insulating film is formed of a photosensitive silicon-containing film irradiated with ultraviolet rays. 7. The semiconductor integrated circuit device according to claim 5, wherein the capacitor having the laminated structure is of a fin type. 8. The semiconductor integrated circuit device according to claim 5, wherein the capacitor having the laminated structure is of a crown type. 9. A method of manufacturing a semiconductor integrated circuit device, comprising: forming a plurality of semiconductor element regions on a main surface of a semiconductor substrate; and forming multilayer wiring on the main surface of the substrate with an interlayer insulating film interposed therebetween. Forming a plurality of MISFETs on the first main surface portion and the second main surface portion of the semiconductor main body surface, respectively, the first main surface portion and the second main surface portion of the base main surface having a relative elevation difference, respectively. Forming a wiring and a second wiring; applying a photosensitive insulating film to the first wiring and the second wiring; performing an exposure process on the photosensitive insulating film; Forming an interlayer insulating film that is selectively subjected to photosensitization on two wirings, the first wiring upper portion and the second wiring upper portion where the interlayer insulating film is selectively provided are continuous, and the surface thereof is flat. Forming another insulating film having a surface, the other The step of patterning the upper wiring on the insulating film,
And a method for manufacturing a semiconductor integrated circuit device. 10. The step of forming an interlayer insulating film comprises forming a photosensitive silicon-containing film, partially irradiating it with ultraviolet rays, etching and removing a film of an unexposed portion, and performing a film modification treatment to obtain a silicon film. The method for manufacturing a semiconductor integrated circuit device according to claim 9, wherein the method is an oxide film. 11. The method for manufacturing a semiconductor integrated circuit device according to claim 10, wherein the photosensitive silicon-containing film is hydrosiloxane or hydrosilazane. 12. The photosensitive silicon-containing film is Si--H.
11. The method of manufacturing a semiconductor integrated circuit device according to claim 10, wherein the silicon composition has a bond. 13. The method for manufacturing a semiconductor integrated circuit device according to claim 10, wherein the wavelength of the ultraviolet rays is 250 nanometers or less. 14. In the step of removing the film of the unirradiated portion by etching, alcohol, ether,
11. The method for manufacturing a semiconductor integrated circuit device according to claim 10, wherein wet etching is performed using at least one of liquefied hydrocarbon and alkaline solution. 15. A step of arranging a plurality of MISFETs forming a memory cell on a first main surface portion of a main surface of a semiconductor substrate and a plurality of MISFETs forming a peripheral circuit on a second main surface portion of a main surface of a semiconductor substrate. Arranging a plurality of capacitors for a memory cell composed of a lower electrode forming a memory cell, a dielectric film, and an upper electrode on the first main surface portion of the main surface; 1 a step of applying a photosensitive insulating film on the main surface portion and the second main surface portion, exposing the photosensitive insulating film, and selectively selecting the second main surface portion having a relatively high altitude. A step of forming a photosensitized interlayer insulating film on another insulating film continuous with the first wiring upper part and the second wiring upper part where the interlayer insulating film is selectively provided, and having a flat surface. Forming the other The step of patterning the upper wiring on the membrane,
Dynamic random, characterized by consisting of
Access memory manufacturing method. 16. The step of forming an interlayer insulating film comprises forming a photosensitive silicon-containing film, partially irradiating it with ultraviolet rays, etching away a film in an unexposed portion, and performing a film modification treatment to form a silicon film. The method for manufacturing a semiconductor integrated circuit device according to claim 15, wherein the oxide film is used. 17. The method of manufacturing a dynamic random access memory according to claim 16, wherein the photosensitive silicon-containing film is hydrosiloxane or hydrosilazane. 18. The photosensitive silicon-containing film is Si--H.
17. The method of manufacturing a semiconductor integrated circuit device according to claim 16, wherein the silicon composition has a bond. 19. The method of manufacturing a dynamic random access memory according to claim 16, wherein the wavelength of ultraviolet rays is 250 nanometers or less. 20. In the step of removing the film of the non-irradiated portion by etching, alcohol, ether,
The method of manufacturing a dynamic random access memory according to claim 16, wherein wet etching is performed using at least one of liquefied hydrocarbon and alkaline solution. 21. A method of manufacturing a semiconductor device, comprising: forming an interlayer insulating film on a main surface of a base on which a semiconductor element is formed and forming a wiring layer on the interlayer insulating film; Forming a photosensitive silicon-containing film, partially irradiating it with ultraviolet rays, etching away the film in the unirradiated part, and performing a film modification treatment on the main surface part of the substrate with a relatively low altitude to form a silicon oxide film A method of manufacturing a semiconductor device, which comprises selectively forming an interlayer insulating film. 22. The method of manufacturing a semiconductor device according to claim 21, wherein the photosensitive silicon-containing film is a silicon composition having a Si—H bond. 23. The method of manufacturing a semiconductor device according to claim 21, wherein the photosensitive silicon-containing film is hydrosiloxane or hydrosilazane. 24. The method of manufacturing a semiconductor device according to claim 21, wherein the wavelength of the ultraviolet rays is 250 nanometers or less. 25. In the step of removing the film of the unirradiated portion by etching, alcohol, ether,
22. The method of manufacturing a semiconductor device according to claim 21, wherein wet etching is performed using at least one of liquefied hydrocarbon and alkaline solution. 26. The method of manufacturing a semiconductor device according to claim 21, wherein the film modification treatment is performed in a gas atmosphere containing water vapor or oxygen at 250 ° C. or higher.