JPH09232433A - プログラム可能ゲート・アレイ構成メモリ - Google Patents

プログラム可能ゲート・アレイ構成メモリ

Info

Publication number
JPH09232433A
JPH09232433A JP9030203A JP3020397A JPH09232433A JP H09232433 A JPH09232433 A JP H09232433A JP 9030203 A JP9030203 A JP 9030203A JP 3020397 A JP3020397 A JP 3020397A JP H09232433 A JPH09232433 A JP H09232433A
Authority
JP
Japan
Prior art keywords
memory
user
logic
fpga
configuration
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9030203A
Other languages
English (en)
Japanese (ja)
Other versions
JPH09232433A5 (https=
Inventor
Charles M C Tan
チャールズ・エム・シー・タン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HP Inc
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of JPH09232433A publication Critical patent/JPH09232433A/ja
Publication of JPH09232433A5 publication Critical patent/JPH09232433A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/1776—Structural details of configuration resources for memories
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1735—Controllable logic circuits by wiring, e.g. uncommitted logic arrays
    • H03K19/1736—Controllable logic circuits by wiring, e.g. uncommitted logic arrays in which the wiring can be modified
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)
  • Memory System (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
JP9030203A 1996-02-14 1997-02-14 プログラム可能ゲート・アレイ構成メモリ Pending JPH09232433A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US599,883 1996-02-14
US08/599,883 US5737766A (en) 1996-02-14 1996-02-14 Programmable gate array configuration memory which allows sharing with user memory

Publications (2)

Publication Number Publication Date
JPH09232433A true JPH09232433A (ja) 1997-09-05
JPH09232433A5 JPH09232433A5 (https=) 2005-01-06

Family

ID=24401488

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9030203A Pending JPH09232433A (ja) 1996-02-14 1997-02-14 プログラム可能ゲート・アレイ構成メモリ

Country Status (3)

Country Link
US (1) US5737766A (https=)
EP (1) EP0790706A3 (https=)
JP (1) JPH09232433A (https=)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20220022120A (ko) * 2019-04-23 2022-02-24 아르보 컴퍼니 엘엘엘피 이중 기능 셀 어레이를 재구성하기 위한 시스템 및 방법
US11435800B2 (en) 2019-04-23 2022-09-06 Arbor Company, Lllp Systems and methods for reconfiguring dual-function cell arrays
US11463524B2 (en) 2020-06-29 2022-10-04 Arbor Company, Lllp Mobile IoT edge device using 3D-die stacking re-configurable processor module with 5G processor-independent modem

Families Citing this family (50)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09293015A (ja) * 1996-04-24 1997-11-11 Mitsubishi Electric Corp メモリシステムおよびそれに用いられる半導体記憶装置
US6758755B2 (en) 1996-11-14 2004-07-06 Arcade Planet, Inc. Prize redemption system for games executed over a wide area network
US5821776A (en) * 1997-01-31 1998-10-13 Actel Corporation Field programmable gate array with mask programmed analog function circuits
US5959466A (en) 1997-01-31 1999-09-28 Actel Corporation Field programmable gate array with mask programmed input and output buffers
US6150837A (en) 1997-02-28 2000-11-21 Actel Corporation Enhanced field programmable gate array
US5940627A (en) * 1997-03-13 1999-08-17 Compaq Computer Corporation User selectable feature set for a flash ROM based peripheral
US5978862A (en) * 1997-08-08 1999-11-02 Toshiba America Information Systems, Inc. PCMCIA card dynamically configured in first mode to program FPGA controlling application specific circuit and in second mode to operate as an I/O device
US6078735A (en) * 1997-09-29 2000-06-20 Xilinx, Inc. System and method for generating memory initialization logic in a target device with memory initialization bits from a programmable logic device
US7003593B2 (en) * 1997-12-17 2006-02-21 Src Computers, Inc. Computer system architecture and memory controller for close-coupling within a hybrid processing system utilizing an adaptive processor interface port
US7373440B2 (en) 1997-12-17 2008-05-13 Src Computers, Inc. Switch/network adapter port for clustered computers employing a chain of multi-adaptive processors in a dual in-line memory module format
US6076152A (en) 1997-12-17 2000-06-13 Src Computers, Inc. Multiprocessor computer architecture incorporating a plurality of memory algorithm processors in the memory subsystem
US6339819B1 (en) * 1997-12-17 2002-01-15 Src Computers, Inc. Multiprocessor with each processor element accessing operands in loaded input buffer and forwarding results to FIFO output buffer
US7565461B2 (en) 1997-12-17 2009-07-21 Src Computers, Inc. Switch/network adapter port coupling a reconfigurable processing element to one or more microprocessors for use with interleaved memory controllers
US6996656B2 (en) * 2002-10-31 2006-02-07 Src Computers, Inc. System and method for providing an arbitrated memory bus in a hybrid computing system
US7146441B1 (en) * 1998-03-16 2006-12-05 Actel Corporation SRAM bus architecture and interconnect to an FPGA
EP0984403A1 (en) * 1998-09-01 2000-03-08 Mindport B.V. Security system
US6347346B1 (en) * 1999-06-30 2002-02-12 Chameleon Systems, Inc. Local memory unit system with global access for use on reconfigurable chips
DE19946752A1 (de) 1999-09-29 2001-04-12 Infineon Technologies Ag Rekonfigurierbares Gate-Array
US6438737B1 (en) 2000-02-15 2002-08-20 Intel Corporation Reconfigurable logic for a computer
WO2002009285A2 (en) * 2000-07-20 2002-01-31 Celoxica Limited System, method and article of manufacture for dynamic programming of one reconfigurable logic device from another reconfigurable logic device
US20020010825A1 (en) * 2000-07-20 2002-01-24 Alex Wilson Memory resource arbitrator for multiple gate arrays
AU2001270874A1 (en) * 2000-07-20 2002-02-05 Celoxica Limited System, method and article of manufacture for controlling the use of resources
US20030028690A1 (en) * 2000-07-20 2003-02-06 John Appleby-Alis System, method and article of manufacture for a reconfigurable hardware-based multimedia device
KR100386253B1 (ko) * 2000-11-28 2003-06-02 엘지전자 주식회사 패러티 비트를 이용한 에프피지에이 레지스터의 라이트데이터 확인회로
KR100413762B1 (ko) * 2001-07-02 2003-12-31 삼성전자주식회사 뱅크 수를 가변할 수 있는 반도체 장치 및 그 방법
MXPA04004117A (es) * 2001-11-01 2004-09-10 Mattel Inc Juego de tablero por medio de tejos.
ATE397806T1 (de) * 2002-03-18 2008-06-15 Nxp Bv Implementierung eines konfigurationsspeichers für auf nachschlagtabellen basierte rekonfigurierbare logische architektur
US7406573B2 (en) * 2002-05-09 2008-07-29 Src Computers, Inc. Reconfigurable processor element utilizing both coarse and fine grained reconfigurable elements
US20030212853A1 (en) * 2002-05-09 2003-11-13 Huppenthal Jon M. Adaptive processor architecture incorporating a field programmable gate array control element having at least one embedded microprocessor core
CN100359602C (zh) * 2002-06-20 2008-01-02 中兴通讯股份有限公司 一种有效利用现场可编程门阵列中的存储器的方法
US6983456B2 (en) * 2002-10-31 2006-01-03 Src Computers, Inc. Process for converting programs in high-level programming languages to a unified executable for hybrid computing platforms
US6941539B2 (en) * 2002-10-31 2005-09-06 Src Computers, Inc. Efficiency of reconfigurable hardware
US6964029B2 (en) * 2002-10-31 2005-11-08 Src Computers, Inc. System and method for partitioning control-dataflow graph representations
US7299458B2 (en) 2002-10-31 2007-11-20 Src Computers, Inc. System and method for converting control flow graph representations to control-dataflow graph representations
US7225324B2 (en) * 2002-10-31 2007-05-29 Src Computers, Inc. Multi-adaptive processing systems and techniques for enhancing parallelism and performance of computational functions
US7155708B2 (en) * 2002-10-31 2006-12-26 Src Computers, Inc. Debugging and performance profiling using control-dataflow graph representations with reconfigurable hardware emulation
US7185225B2 (en) * 2002-12-02 2007-02-27 Marvell World Trade Ltd. Self-reparable semiconductor and method thereof
US7340644B2 (en) * 2002-12-02 2008-03-04 Marvell World Trade Ltd. Self-reparable semiconductor and method thereof
US20060001669A1 (en) * 2002-12-02 2006-01-05 Sehat Sutardja Self-reparable semiconductor and method thereof
US7890686B2 (en) * 2005-10-17 2011-02-15 Src Computers, Inc. Dynamic priority conflict resolution in a multi-processor computer system having shared resources
US7716100B2 (en) * 2005-12-02 2010-05-11 Kuberre Systems, Inc. Methods and systems for computing platform
WO2007120439A2 (en) * 2006-04-14 2007-10-25 Raytheon Company Data storing
US7697329B2 (en) * 2007-01-31 2010-04-13 Sandisk 3D Llc Methods and apparatus for using a configuration array similar to an associated data array
US7843729B2 (en) * 2007-01-31 2010-11-30 Sandisk 3D Llc Methods and apparatus for using a configuration array similar to an associated data array
EP2367454B1 (en) * 2008-11-24 2016-07-06 Srl, Llc Article of footwear
US8718079B1 (en) 2010-06-07 2014-05-06 Marvell International Ltd. Physical layer devices for network switches
JP5500282B1 (ja) * 2013-02-28 2014-05-21 日本電気株式会社 障害修復装置、障害修復方法、及び、障害修復プログラム
US9536590B1 (en) * 2014-09-03 2017-01-03 Marvell International Ltd. System and method of memory electrical repair
US10037187B2 (en) * 2014-11-03 2018-07-31 Google Llc Data flow windowing and triggering
US10802735B1 (en) * 2019-04-23 2020-10-13 Arbor Company, Lllp Systems and methods for reconfiguring dual-function cell arrays

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5343406A (en) * 1989-07-28 1994-08-30 Xilinx, Inc. Distributed memory architecture for a configurable logic array and method for using distributed memory
US5099150A (en) * 1989-09-29 1992-03-24 Sgs-Thomson Microelectronics, Inc. Circuit block for programmable logic devices, configurable as a user-writable memory or a logic circuit
GB9223226D0 (en) * 1992-11-05 1992-12-16 Algotronix Ltd Improved configurable cellular array (cal ii)
US5414377A (en) * 1992-12-21 1995-05-09 Xilinx, Inc. Logic block with look-up table for configuration and memory
EP0665998A4 (en) * 1993-08-03 1996-06-12 Xilinx Inc FPGA CIRCUIT WITH MICROPROCESSOR.
US5600597A (en) * 1995-05-02 1997-02-04 Xilinx, Inc. Register protection structure for FPGA
US5583450A (en) * 1995-08-18 1996-12-10 Xilinx, Inc. Sequencer for a time multiplexed programmable logic device

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20220022120A (ko) * 2019-04-23 2022-02-24 아르보 컴퍼니 엘엘엘피 이중 기능 셀 어레이를 재구성하기 위한 시스템 및 방법
JP2022525557A (ja) * 2019-04-23 2022-05-17 アーバー・カンパニー・エルエルエルピイ 二重機能セルアレイを再構成するためのシステムおよび方法
US11435800B2 (en) 2019-04-23 2022-09-06 Arbor Company, Lllp Systems and methods for reconfiguring dual-function cell arrays
US11797067B2 (en) 2019-04-23 2023-10-24 Arbor Company, Lllp Systems and methods for reconfiguring dual-function cell arrays
US12287687B2 (en) 2019-04-23 2025-04-29 Arbor Company, Lllp Systems and methods for integrating batteries to maintain volatile memories and protect the volatile memories from excessive temperatures
US11463524B2 (en) 2020-06-29 2022-10-04 Arbor Company, Lllp Mobile IoT edge device using 3D-die stacking re-configurable processor module with 5G processor-independent modem
US11895191B2 (en) 2020-06-29 2024-02-06 Arbor Company, Lllp Mobile IoT edge device using 3D-die stacking re-configurable processor module with 5G processor-independent modem
US12470628B2 (en) 2020-06-29 2025-11-11 Arbor Company, Lllp Mobile IoT edge device using 3D-die stacking re-configurable processor module with 5G processor-independent modem

Also Published As

Publication number Publication date
US5737766A (en) 1998-04-07
EP0790706A2 (en) 1997-08-20
EP0790706A3 (en) 1999-01-07

Similar Documents

Publication Publication Date Title
JPH09232433A (ja) プログラム可能ゲート・アレイ構成メモリ
US6191998B1 (en) Programmable logic device memory array circuit having combinable single-port memory arrays
US5809281A (en) Field programmable gate array with high speed SRAM based configurable function block configurable as high performance logic or block of SRAM
KR100504969B1 (ko) 메모리용대기제어부를가진집적회로
JP3471088B2 (ja) 改良されたプログラマブル論理セルアレイアーキテクチャ
US6105105A (en) Data processing system using configuration select logic, an instruction store, and sequencing logic during instruction execution
KR100458371B1 (ko) 프로그램가능한 논리 셀 어레이의 구성 방법 및 구성 장치
JP3106998B2 (ja) メモリ付加型プログラマブルロジックｌｓｉ
US7957208B1 (en) Flexible memory architectures for programmable logic devices
US6803782B2 (en) Arrayed processing element redundancy architecture
US6029236A (en) Field programmable gate array with high speed SRAM based configurable function block configurable as high performance logic or block of SRAM
USRE37060E1 (en) Apparatus for serial reading and writing of random access memory arrays
US6288970B1 (en) Programmable logic device memory array circuit having combinable single-port memory arrays
US5099453A (en) Configuration memory for programmable logic device
US6870393B2 (en) Field programmable device
JPH03139863A (ja) 半導体集積回路
US7225321B2 (en) Reprogrammable microprogram based reconfigurable multi-cell logic concurrently processing configuration and data signals
US6680871B1 (en) Method and apparatus for testing memory embedded in mask-programmable logic device
US7554358B1 (en) Programmable logic devices with user non-volatile memory
JP2015082671A (ja) 半導体装置
JPH0563551A (ja) プログラマブル論理回路装置
US6359811B1 (en) Semiconductor integrated circuit with random access memory testing
KR100403480B1 (ko) 반도체 메모리 장치 및 이를 이용한 읽기/쓰기 동작 방법
JP2022525557A (ja) 二重機能セルアレイを再構成するためのシステムおよび方法
CN116741230A (zh) 可编程逻辑电路、动态改写可编程逻辑电路的方法和装置

Legal Events

Date Code Title Description
A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20050523

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20050804

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20060105

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A711

Effective date: 20060629

A072 Dismissal of procedure [no reply to invitation to correct request for examination]

Free format text: JAPANESE INTERMEDIATE CODE: A072

Effective date: 20070130