JPH09232397A - Semiconductor wafer provided with strained layer and intensity evaluation method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To evaluate damage intensity or a slip resistant dislocation intensity based on the measurement of the stress-strain characteristic of a wager itself to which a skew layer is guided by executing evaluation based on the degree of deterioration on an upper yield stress value and a lower yield stress value in the stress-strain characteristic. SOLUTION: The intensity of the semiconductor wafer having the strained layer which is intentionally guided from outside on one main face where the device of the semiconductor wafer is not formed is evaluated based on the degree of deterioration on the upper yield stress value MP1 and the lower yield stress value MP2 in the stress-strain characteristic being the mechanical intensity characteristic of the semiconductor wafer. A satisfactory correlation exists between the deterioration quantity of the upper yield stress value MP1 of the semiconductor wafer which the stained layer is guided by a lapping method and slip dislocation defect guide quantity. When the upper yield stress value of the wafer having the strained layer which is intentionally guided from outside is within the range of 90 to 100% compared to a case when the external strain does not exist, satisfactory slip resistant intensity is shown.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor wafer on which a semiconductor device such as an IC or VLSI is formed and its evaluation method. More specifically, it is intended to getter metal impurities, and to deliberately from the outside. The present invention relates to a method for evaluating the strength of a wafer having an introduced strained layer against slip dislocation defects.

[0002]

2. Description of the Related Art Conventionally, a semiconductor wafer, especially a silicon wafer, has been subjected to a treatment for forming a strain layer introduced from the outside, which is called an external gettering treatment such as sandblasting. This external gettering process is performed on the metal impurities contained in the semiconductor wafer, IC and VL.
This is carried out to remove impurities such as SI, which are typified by heavy metals such as iron and copper, which are introduced from the outside in the semiconductor device manufacturing process, from the device active region of the semiconductor device and its vicinity.

However, in the external gettering treatment, for example, in the case of the sandblast method, SiO ₂ powder is sprayed onto one main surface of the semiconductor wafer on which no device is formed, thereby forming a strained layer on this main surface. As described above, since the strained layer is mechanically formed,
The mechanical strength of the semiconductor wafer itself may be reduced. In fact, in a wafer with a strained layer formed, slip dislocations due to thermal stress called slip dislocation often occur due to high-temperature heat treatment performed in the semiconductor device manufacturing process, and the frequency is that the strained layer is not formed. Much higher than wafers. Therefore, it is necessary to control the amount of strain to be introduced in order to prevent the occurrence of slip dislocation in the semiconductor device manufacturing process, but there is not necessarily a satisfactory evaluation method for controlling the amount of strain.

For example, the damage strength of the strained layer formed by the sandblast method is 110 for the processed wafer.
It has been evaluated by the density of OSF (oxidation-induced stacking fault) generated on the surface on which the strained layer is formed by performing an oxidation treatment in an atmosphere containing oxygen at a temperature of 0 to 1200 ° C. and the density of crystal defects such as dislocation loops . It has also been performed that a wafer is heat-treated in a form simulating the heat treatment in a semiconductor device manufacturing process, and the presence or absence of slip dislocation is evaluated by an X-ray topography method or a selective etching method. In addition, a method of evaluating damage of the introduced strained layer by an optical method or an X-ray diffraction method is disclosed (Japanese Patent Laid-Open No. 1-211937).
JP-A-5-203590).

[0005]

However, although the crystal defect density after the above-mentioned oxidation treatment shows a correlation with the damage of the strained layer, the presence or absence of slip dislocations on the wafer in the actual semiconductor device manufacturing process. There is a problem that it does not show a good correlation with. Further, the method of simulating the heat treatment in the semiconductor device manufacturing process has a drawback in that the results vary widely and many samples are required to obtain reliable data.

Furthermore, since these conventional methods are methods for evaluating damage to the strained layer of a semiconductor wafer in which strain is introduced, the strength characteristics of the semiconductor wafer itself cannot be directly evaluated from the results.

The present invention has been made to solve the problems and problems of the conventional evaluation method as described above, and based on the measurement of the stress-strain characteristic of the wafer itself in which the strained layer is introduced, the damage strength or the resistance is measured. It is an object of the present invention to realize a method for evaluating slip dislocation strength, and to provide an external gettering-processed semiconductor wafer that does not generate slip dislocations in a semiconductor device manufacturing process based on the evaluation method.

[0008]

Generally, there is a certain degree of correlation between the damage strength of a strained layer introduced into a semiconductor wafer and the occurrence of slip dislocations in the semiconductor manufacturing process. It was confirmed that the yield stress value in the temperature region where the semiconductor wafer exhibits plastic deformation is important as a correlation factor between the amount of strain introduced into the wafer and the damage strength or slip resistance of the semiconductor wafer itself. More specifically, various experimental results confirm that the mechanical strength of the wafer itself, especially the degree of decrease in the upper yield stress value and the lower yield stress value in the stress-strain characteristics, has a strong correlation with the occurrence of slip dislocations. did.

The inventors of the present invention have variously determined the relationship between the stress and strain in the temperature region exhibiting plastic deformation and the correlation with the slip transition for a semiconductor wafer in which a strained layer is intentionally introduced from the outside and a semiconductor wafer in which the strained layer is not introduced. As a result of examination, when the yield stress value of a semiconductor wafer having a strained layer is manufactured so as to be within a predetermined ratio with respect to the yield stress value of a semiconductor wafer having no strained layer, it is possible to obtain excellent slip resistance. It was confirmed.

Therefore, the semiconductor wafer of the present invention is a wafer having a strained layer intentionally introduced from the outside on one principal surface which does not form a device of the wafer, and the semiconductor material is in a temperature range in which it exhibits plastic deformation. The stress-strain curve is characterized in that the upper yield stress value is in the range of 90 to 100% as compared with the case without external strain.

Further, a wafer having a strain layer intentionally introduced from the outside on one main surface which does not form a device of a semiconductor wafer, wherein the stress-strain curve in a temperature region where the semiconductor material shows plastic deformation is: The yield stress value is
It is characterized by being in the range of 70 to 100% as compared with the case where there is no external distortion.

[0012]

Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a diagram illustrating the principle of the strength evaluation method for a semiconductor wafer having a strained layer according to the present invention. The stress-strain curve C shown in the figure is applied to a test piece prepared from a semiconductor wafer to be measured,
The relationship between the strain and the stress generated by applying a load such as compression or bending is shown. As the load is applied to the test piece, the stress increases and passes the proportional limit T2 and the elastic limit T3, and reaches the upper yield point T3. The upper yield stress value at the upper yield point T3 is MP1. After passing through the upper yield point T3, the stress decreases as the strain increases and reaches the descending yield point T4. The yield stress value at the yield point T4 is MP2. After that, the stress increases again as the strain increases, and finally reaches the break point T5 and breaks.

FIG. 2 is an example of a stress-strain diagram of a semiconductor wafer in which a strained layer is introduced by the lapping method, and the amount of lapping strain is displayed as a parameter. As shown in FIG. 2, in the stress-strain curves C1 to C3 of the wafer in which the lapping strain layer is introduced, compared with the stress-strain curve C4 of the wafer in which the strain layer is not intentionally introduced from the outside,
The upper yield stress value decreases. [Table 1] shows the amount of slip dislocation defects introduced for the semiconductor wafers C1 to C3 having a strained layer introduced by the lapping method and the wafer C4 not intentionally introducing a strained layer from the outside. The slip occurrence area a. u. Indicates that the wafer is divided into squares at regular intervals and the slip occurrence portion is counted. The smaller the value, the better the slip resistance.

[0014]

[Table 1]

In Experiment 1 of [Table 1], the wafer was put in and out of the heat treatment furnace at 800 ° C., and in Experiment 2, the wafer was put in and out of the heat treatment furnace at 1000 ° C. As can be seen from [Table 1], there is a good correlation between the amount of decrease in the upper yield stress of a semiconductor wafer having a strained layer introduced by the lapping method and the amount of slip dislocation defects introduced. As described above, the upper yield stress value of the wafer having the strain layer intentionally introduced from the outside is 90 to 100 as compared with the case without the external strain.
It has been found that if it is in the range of%, good slip resistance is exhibited.

FIG. 3 is an example of a stress-strain diagram of a semiconductor wafer in which a strained layer is introduced by the sandblast method.
The amount of sandblast distortion is displayed as a parameter. As shown in FIG. 3, in the stress-strain curves D1 to D3 of the wafer in which the sandblast strain layer is introduced, the lowering yield stress value is lower than in the stress-strain curve D4 of the wafer in which the strain layer is not intentionally introduced from the outside. To do. In [Table 2],
Semiconductor wafer D1 having a sandblasted strained layer introduced
D3 and wafer D without intentionally introducing a strained layer from the outside
Regarding No. 4, the slip dislocation defect introduction amount is shown in comparison.

[0017]

[Table 2]

In Experiment 1 of [Table 2], the wafer was put in and out of the heat treatment furnace at 800 ° C., and in Experiment 2, the wafer was put in and out of the heat treatment furnace at 1000 ° C. As can be seen from [Table 2], there is a good correlation between the amount of decrease in the yield stress of the semiconductor wafer having the sandblasted strain layer introduced and the amount of slip dislocation defects introduced. As described above, when the down stress value of the wafer having the strain layer intentionally introduced from the outside is in the range of 70 to 100% as compared with the case where there is no external strain, good slip resistance can be exhibited. all right.

As described above, in the semiconductor wafer in which the strained layer is introduced by the external gettering treatment, as compared with the wafer in which the strained layer is not introduced, the upper yield stress value and the lower yield stress value of the stress-strain curve are It was confirmed that one or both tended to decrease. Based on this, the upper yield stress value of the semiconductor wafer in which the strained layer is introduced is in the range of 90 to 100% as compared with that of the semiconductor wafer in which the strained layer is not introduced, or the yield stress value is 70 to
By setting the content in the range of 100%, a semiconductor wafer having excellent slip resistance could be manufactured.

[0020]

As described above, according to the strength evaluation method for a semiconductor wafer having a strained layer according to the present invention, the upper yield stress value or the lower yield stress value of a wafer into which a strained layer is intentionally introduced from outside is A semiconductor wafer having excellent characteristics can be realized by manufacturing the wafer without a strained layer so that the yield stress value or the yield stress value falls within a predetermined range.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of a strength evaluation method for a semiconductor wafer having a strained layer according to the present invention.

FIG. 2 is a stress-strain diagram of a semiconductor wafer having a strained layer introduced by a lapping method.

FIG. 3 is a stress-strain diagram of a semiconductor wafer in which a strained layer is introduced by a sandblast method.

[Explanation of symbols]

C Stress-strain diagram of semiconductor wafer with strained layer introduced by lapping method D Stress-strain diagram of semiconductor wafer with strained layer introduced by sandblasting method T1 Proportional limit T2 Elastic limit T3 Upper yield point T4 Fall yield point T5 Fracture Point MP1 Upper yield stress value MP2 Lower yield stress value

Claims (3)

[Claims] 1. Based on the degree of decrease in the upper yield stress value and the lower yield stress value of the stress-strain characteristic, which is the mechanical strength characteristic of the semiconductor wafer, the one main surface on which the device of the semiconductor wafer is not intentionally formed. A method for evaluating the strength of a semiconductor wafer having a strained layer, which comprises evaluating the strength of a semiconductor wafer having a strained layer introduced from the outside. 2. A wafer having a strain layer intentionally introduced from the outside on one principal surface of a semiconductor wafer which does not form a device, wherein the stress-strain curve in a temperature region in which the semiconductor material exhibits plastic deformation, A semiconductor wafer having a deliberately introduced strained layer, characterized in that the upper yield stress value is in the range of 90 to 100% compared to the case without external strain. 3. A wafer having a strain layer which is intentionally introduced from the outside on one principal surface which does not form a device of a semiconductor wafer, wherein a stress-strain curve in a temperature region in which the semiconductor material shows plastic deformation, A semiconductor wafer having a deliberately introduced strained layer, characterized in that the yield stress value is in the range of 70 to 100% compared to the case without external strain.