JPH09232383A - 半導体装置 - Google Patents

半導体装置

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Publication number
JPH09232383A
JPH09232383A JP3387096A JP3387096A JPH09232383A JP H09232383 A JPH09232383 A JP H09232383A JP 3387096 A JP3387096 A JP 3387096A JP 3387096 A JP3387096 A JP 3387096A JP H09232383 A JPH09232383 A JP H09232383A
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JP
Japan
Prior art keywords
matching
loop
semiconductor device
wire
circuit
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Granted
Application number
JP3387096A
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English (en)
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JP2795251B2 (ja
Inventor
Kazunori Asano
和則 麻埜
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NEC Corp
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NEC Corp
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Publication of JP2795251B2 publication Critical patent/JP2795251B2/ja
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Expired - Lifetime legal-status Critical Current

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Abstract

(57)【要約】 【課題】内部整合回路型高出力FETにおいて回路占有
面積を増加することなく大インダクタンスを得る。 【解決手段】ボンディングワイヤ9Aが、少なくとも1
回転のループ部10を備える。

Description

【発明の詳細な説明】
【0001】
【発明の属する技術分野】本発明は半導体装置に関し、
特に高周波用の内部整合回路型の高出力FETなどの半
導体装置に関する。
【0002】
【従来の技術】一般に、高周波帯で用いられる高出力F
ETは、複数のFET素子の並列接続から成りその入力
および出力インピーダンスが極めて低く数Ω程度である
のに対し、これら入出力の高周波信号を伝送する伝送回
路のインピーダンスは50Ω程度である。このため、効
率よく入出力信号を素子に結合するためインピーダンス
整合回路(以下整合回路)を用いる。この整合回路をパ
ッケージ内に有する半導体装置を内部整合回路型と呼
び、この種の半導体装置の主用途である無線装置の設計
・製造が容易となるため広く用いられるようになってき
ている。
【0003】従来、この種の半導体装置の内部整合回路
は、集中定数のL−C−LT型共振回路と分布定数のイ
ンピーダンス変換回路との組合せによるものが広く用い
られている。一般に、回路構成を単純化するため、集中
定数回路のLすなわちインダクタンスとしてボンデング
ワイヤ自身が持つインダクタンスを用いる。
【0004】従来のこの種の半導体装置である内部整合
型の高出力FETを平面図およびX−X断面図でそれぞ
れ示す図5(A),(B)を参照すると、この従来の半
導体装置は、パッケージ1内に複数(ここでは7個)の
FET素子から成る半導体チップ2と、入力側,出力側
の各インピーダンス変換回路Zi,Zo用の回路基板
3,4と、入力側,出力側の各誘電体キャパシタCi,
Coである薄膜のコンデンサ5,6と、入力側,出力側
リード7,8とを装着し、各コンポーネント2〜8間を
ボンディングワイヤ9で接続する。
【0005】従来の半導体装置の等価回路を示す図5
(C)を参照すると、入力側インピーダンス変換回路Z
iとFET2のゲートとの間にボンディングワイヤ9の
LiとキャパシタCiとから成る一段のL−C−L共振
回路を、出力側インピーダンス変換回路ZoとFET2
のドレインとの間にボンディングワイヤ9のLoとキャ
パシタCoとから成る一段のL−C−L共振回路をそれ
ぞれ備える。
【0006】ここで、インダクタンスLi,Lo(以下
L)をボンディングワイヤで構成する場合、このLの値
はワイヤの長さ,ワイヤ径,およびワイヤで形成される
山の高さによって調整する。経験則として近似的には、
ワイヤ径が25μmφの場合Lは0.56nH/(長
さ)mmで表すことができる。
【0007】ところで上述のようにボンディングワイヤ
と薄膜コンデンサで構成された内部整合回路の場合、X
−Ku帯(8〜15GHz)等の比較的高い周波数帯で
はインダクタンスL,キャパシタンスCの値は小さくて
も十分整合をとれる回路の構成が可能であるが、L−S
帯(1〜4GHz)等の比較的低い周波数帯域では整合
をとるために大きなL,Cを必要とする。その場合、C
については高誘電率基板を用いる等の対策が行われる。
一方、Lについてはワイヤを長くするか、あるいは細い
ワイヤを用いることが考えられる。しかしながらワイヤ
部分の電流密度が大きくなる高出力FETの場合は細い
ワイヤを用いることは信頼度上制約がある。また単純に
ワイヤを長くすることもパッケージサイズを大きくする
ため、コストの増加要因となる。
【0008】例えばL−S帯の場合、上記Lとして2n
H以上のインダクタンスを必要とするが、この値を実現
するためには25μmφのワイヤを用いた時、長さ2m
m以上必要となり、ワイヤで形成される山の高さも0.
7mm以上、ボンディング間距離は1.4mm以上を必
要とする。
【0009】
【発明が解決しようとする課題】上述した従来の半導体
装置は、ボンディングワイヤのインダクタンスを利用し
て所要のインダクタンスを得る構成であるので、使用周
波数帯が低い場合、所要のインダクタンスを確保するた
めワイヤ径を細くするか、長くするかの必要があり、前
者の場合には電流密度の上昇から信頼度上の制約があ
り、後者の場合にはパッケージサイズが大きくなるため
コストの増加要因となるという欠点があった。
【0010】本発明の目的は、内部整合回路型高出力F
ETのインダンクタンス素子を小型化して回路面積の増
加によるコスト増加要因を抑制した半導体装置を提供す
ることにある。
【0011】
【課題を解決するための手段】本発明の半導体装置は、
半導体チップとこの半導体チップの入力端および出力端
のインピーダンスを外部回路と整合させるための入力お
よび出力インピーダンス整合用の整合回路とをそれぞれ
有し、前記整合回路の各々が前記半導体チップとの間お
よび前記整合回路の内部の回路素子間の接続用のボンデ
ィングワイヤを前記インピーダンス整合用のインダクタ
ンスとして利用する半導体装置において、前記ボンディ
ングワイヤが、少なくとも1回転のループ部を備えて構
成されている。
【0012】
【発明の実施の形態】次に、本発明の実施の形態を図5
と共通の構成要素には共通の参照文字/数字を付して同
様に平面図およびX−X断面図でそれぞれ示す図1
(A),(B)を参照すると、この図に示す本実施の形
態の半導体装置は、従来と共通のパッケージ1と、半導
体チップ2と、回路基板3,4と、コンデンサ5,6
と、入力側,出力側リード7,8とに加えて、ボンディ
ングワイヤ9の代りに少なくとも1回転のループ10を
有するボンディングワイヤ9Aを備える。
【0013】このループ10を形成することにより、ル
ープ部分でインダクタンスをかせぐことができ、コンパ
クトに大きなLを持つインダクタが得られる。
【0014】例えばループ半径0.2mmで1回転のル
ープを形成した場合、山の高さは0.3mm、ボンディ
ング間距離は0.6mmで十分であるため整合回路の小
型化およびパッケージの小型化を図ることが可能とな
る。
【0015】次に、ワイヤにループを形成するループ形
成工程を示す図2,図3を参照して本実施の形態の半導
体装置の製造方法について説明すると、まず、図2
(A)で、半導体チップ2の入力側のボンディングパッ
ド13に熱圧着あるいは超音波圧着により20〜30μ
mφのAu線から成るボンディングワイヤ9をワイヤ押
え11を用いて固定しながらボンディングする。次に、
図2(B)に示すようにワイヤ送り出し部12を操作
し、所定の高さまでワイヤを伸ばした状態でワイヤルー
プ10の中心となるループ心棒15を横から挿入する。
ループ10の半径はこのループ心棒15の半径で調整す
る。次に、図2(C)に示すようにワイヤ送り出し部1
2をワイヤが心棒に巻き付くように下降させ、ワイヤ9
が半周したところでループ心棒15を一時的に後退させ
る。次に、図3(A)に示すようにワイヤ9がループ1
0を形成するようにワイヤ送り出し部12を一周させな
がら、同時にループ内にループ心棒15を挿入する(図
3(B))。次にワイヤ送り出し部12のワイヤ送出端
が心棒の軸を中心にして一周して戻ってきてからワイヤ
9の他の端となるコンデンサ5のボンディング箇所に移
動させ、上記と同様の圧着法によりボンディングを行う
(図3(C))。最後に、形成されたループ10からル
ープ心棒15を引き抜く。以上の工程により1回転のル
ープ10を含むボンディングワイヤ9Aを形成すること
が可能となる。
【0016】またループ10を形成する工程を複数回行
うことにより2回転以上のループを形成することも可能
である。ただしループ部分が複数になると隣接するワイ
ヤと接触する可能性があるため、ループの数には制限が
ある。
【0017】上述の説明は入力側のボンディングワイヤ
の形成方法についてであるが、出力側あるいはその他の
ボンディングワイヤ形成についても同様である。
【0018】なお、上記製造方法によるワイヤボンディ
ングを精度よく行うためには、自動ボンダにおいてワイ
ヤ送り出し部の回転動作と心棒の軸方向の移動を最適に
制御することが有効である。
【0019】次に、本発明の第2の実施例を特徴ずける
ボンディングワイヤ9Bを半導体装置の模式断面図で示
す図4を参照すると、この図に示す本実施の形態の第1
の実施の形態との相違点は、ボンディングワイヤ9Bに
ループ10を2箇所形成していることである。
【0020】このような構造にすることで、ワイヤ9が
近接する場合にも複数のループ10を形成でき、インダ
クタンスを大きくすることができる。この場合のループ
10の形成方法は上述の工程でループ10を一回形成し
た後、ワイヤ送り出し部12とループ心棒15とを平行
移動させ、上述と同様の工程でさらにループ10を一つ
形成する工程を加えることで可能となる。
【0021】
【発明の効果】以上説明したように、本発明の半導体装
置は、ボンディングワイヤが、少なくとも1回転のルー
プ部を備えることにより、占有面積を高めることなく大
きなインダクタンスを得ることができるので半導体装置
の小型化が可能となり、コスト増大要因を抑圧できると
いう効果がある。
【図面の簡単な説明】
【図1】本発明の半導体装置の第1の実施の形態を示す
平面図および断面図である。
【図2】本実施の形態の半導体装置のループ形成方法を
示す工程図である。
【図3】本実施の形態の半導体装置のループ形成方法を
示す工程図である。
【図4】本発明の半導体装置の第2の実施の形態を示す
平面図および断面図である。
【図5】従来の半導体装置の一例を示す平面図,断面図
および等価回路の回路図である。
【符号の説明】
1 パッケージ 2 半導体チップ 3,4 回路基板 5,6 コンデンサ 7,8 リード 9,9A,9B ボンディングワイヤ 10 ループ 11 ワイヤ押え 12 ワイヤ送り出し部 13 ボンディングパッド 15 ループ心棒

Claims (3)

    【特許請求の範囲】
  1. 【請求項1】 半導体チップとこの半導体チップの入力
    端および出力端のインピーダンスを外部回路と整合させ
    るための入力および出力インピーダンス整合用の整合回
    路とをそれぞれ有し、前記整合回路の各々が前記半導体
    チップとの間および前記整合回路の内部の回路素子間の
    接続用のボンディングワイヤを前記インピーダンス整合
    用のインダクタンスとして利用する半導体装置におい
    て、 前記ボンディングワイヤが、少なくとも1回転のループ
    部を備えることを特徴とする半導体装置。
  2. 【請求項2】前記ボンディングワイヤの一本が、少なく
    とも2箇所に前記ループ部を備えることを特徴とする請
    求項1記載の半導体装置。
  3. 【請求項3】 前記ループ部が、前記ボンディングワイ
    ヤの接続工程時と同時に形成されることを特徴とする請
    求項1または2記載の半導体装置。
JP3387096A 1996-02-21 1996-02-21 半導体装置 Expired - Lifetime JP2795251B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3387096A JP2795251B2 (ja) 1996-02-21 1996-02-21 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3387096A JP2795251B2 (ja) 1996-02-21 1996-02-21 半導体装置

Publications (2)

Publication Number Publication Date
JPH09232383A true JPH09232383A (ja) 1997-09-05
JP2795251B2 JP2795251B2 (ja) 1998-09-10

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Country Link
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009016408A1 (en) * 2007-07-31 2009-02-05 Bae Systems Plc Flexible joint
JP2009512384A (ja) * 2005-10-19 2009-03-19 エヌエックスピー ビー ヴィ 接続部に結合された電極を有する素子を備える装置
JP2017531914A (ja) * 2014-09-23 2017-10-26 ホアウェイ・テクノロジーズ・カンパニー・リミテッド 無線周波数電力コンポーネントおよび無線周波数信号送受信デバイス

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03173446A (ja) * 1989-12-01 1991-07-26 Matsushita Electron Corp 半導体装置
JPH04179244A (ja) * 1990-11-14 1992-06-25 Nec Corp 半導体装置
JPH04186645A (ja) * 1990-11-16 1992-07-03 Sanyo Electric Co Ltd マイクロ波集積回路の製造方法
JPH06334000A (ja) * 1993-05-20 1994-12-02 Hitachi Ltd 高周波回路モジュール及びその製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03173446A (ja) * 1989-12-01 1991-07-26 Matsushita Electron Corp 半導体装置
JPH04179244A (ja) * 1990-11-14 1992-06-25 Nec Corp 半導体装置
JPH04186645A (ja) * 1990-11-16 1992-07-03 Sanyo Electric Co Ltd マイクロ波集積回路の製造方法
JPH06334000A (ja) * 1993-05-20 1994-12-02 Hitachi Ltd 高周波回路モジュール及びその製造方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009512384A (ja) * 2005-10-19 2009-03-19 エヌエックスピー ビー ヴィ 接続部に結合された電極を有する素子を備える装置
WO2009016408A1 (en) * 2007-07-31 2009-02-05 Bae Systems Plc Flexible joint
JP2017531914A (ja) * 2014-09-23 2017-10-26 ホアウェイ・テクノロジーズ・カンパニー・リミテッド 無線周波数電力コンポーネントおよび無線周波数信号送受信デバイス
US10347596B2 (en) 2014-09-23 2019-07-09 Huawei Technologies Co., Ltd. Radio frequency power component and radio frequency signal transceiving device

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