JPH09230376A - Liquid crystal display device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal display substrate which is unsusceptible to disconnection of the drain signal line by forming a breaking opposing layer separately from the gate signal line, exposing at least the central portion exclusive of the peripheral portion from the opening section formed in the insulation film and forming a layer superposed with the drain signal line. SOLUTION: The breaking opposing layer 5 is slightly separated from the gate signal line 2. In the region surrounded by the gate signal line 2 and the layer 5, a pixel electrode 4 composed from an ITO film is formed. Then whole area of the surface thus processed is formed with an insulation film consisting of silicon nitride; the insulation film is installed with an opening section 70A which exposes the central section exclusive of the peripheral section of the pixel electrode 4 and an opening section 70B which exposes the central section exclusive of the peripheral section of the layer 5. In addition, in the crossing region of the thin film transistor TFT forming region superposed on a part of the gate signal line 2 on the insulation film and the drain signal line 3, a successively laminated body with a-Si films is formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display substrate and a manufacturing method thereof, and more particularly to an active matrix type liquid crystal display substrate and a manufacturing method thereof.

[0002]

2. Description of the Related Art Active matrix type liquid crystal substrates are
It is known that a thin film transistor as a switching element is provided in each pixel region arranged in a matrix.

That is, a thin film transistor which is turned on by a scanning signal supplied to a gate signal line is provided in each pixel region on the liquid crystal side surface of one transparent substrate of the transparent substrates arranged to face each other with the liquid crystal interposed therebetween. Pixel electrodes and the like to which a pixel signal supplied from the drain signal line is applied via the turned-on thin film transistor are formed.

The gate signal line and the drain signal line intersect each other and are formed so as to partition each pixel region, and are supplied with different signals so that they are insulated from each other through the interlayer insulating film. Is formed.

As a liquid crystal display substrate having such a structure, for example, Japanese Patent Laid-Open No. 63-309921 or "12.5 type active matrix type color liquid crystal display employing a redundant structure", Nikkei Electronics, pages 193-210. , December 15, 1986, published by Nikkei McGraw-Hill Inc., etc.

[0006]

However, it has been pointed out that in the liquid crystal display substrate having such a structure, the disconnection often occurs when the drain signal line is formed.

In the manufacture of a liquid crystal display substrate, the drain signal line is often formed after the gate signal line and the thin film transistor are formed. When the drain signal line is formed, a semiconductor or the like is formed in the drain signal line formation region. This is because the residue may remain without being completely etched.

In this way, when a semiconductor signal residue, foreign matter, etc. are present and the drain signal line is formed across this residue,
The drain signal line will break at the residue.

Even if the residue of the semiconductor or the like does not cause such disconnection of the drain signal line, the residue extends to the area where the adjacent pixel electrode is formed, for example. In the case where it has happened, there is an adverse effect that a leak current flows between the drain signal line and the pixel electrode.

The present invention has been made under such circumstances.

An object of the present invention is to provide a liquid crystal display substrate having a structure in which disconnection of the drain signal line is hard to occur.

Another object of the present invention is to provide a liquid crystal display substrate having a structure in which the adverse effects of the presence of residues such as semiconductors are eliminated.

Another object of the present invention is to provide a method of manufacturing a liquid crystal display substrate in which disconnection of the drain signal line is hard to occur.

Still another object of the present invention is to provide a method of manufacturing a liquid crystal display substrate which eliminates the harmful effects of the presence of residues such as semiconductors.

[0015]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, a thin film transistor which is turned on by supplying a scanning signal through a gate signal line to each pixel region on the liquid crystal side surface of one of the transparent substrates which are arranged to face each other through the liquid crystal, and the thin film transistor. A pixel electrode to which a pixel signal from the drain signal line is supplied via the thin film transistor, wherein the drain signal line is positioned above the gate signal line in the liquid crystal display substrate. A conductive disconnection failure countermeasure layer is formed under the insulating film in the line formation region, and the disconnection failure countermeasure layer is formed separately from the gate signal line and at least in the central portion except its peripheral portion. Is exposed from the opening formed in the insulating film and is formed so as to overlap with the drain signal line. It is.

In the liquid crystal display substrate having such a structure, even if the residue of the semiconductor layer forming the thin film transistor is formed over the adjacent pixel electrode across the drain signal line forming region, a disconnection defect in the insulating layer is caused. When forming the opening for exposing the countermeasure layer, at least the residue present in that portion is completely removed.

Since the drain signal line is formed so as to be superimposed on the disconnection defect countermeasure layer from which the residue has been removed, a leak current may flow from the drain signal line to the pixel electrode side through the residue. Disappears.

Further, when the drain signal line is formed due to a disconnection in the signal line for some reason during the formation of the drain signal line, the drain signal line is directly superposed on the conductive disconnection failure countermeasure layer over most of the region. Since it is formed by being formed, the disconnection is automatically repaired.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a liquid crystal display substrate and a method of manufacturing the same according to the present invention will be described below with reference to the drawings.

Example 1. First, FIG. 2 is a plan view showing a configuration on a liquid crystal side surface of one transparent substrate 1 among transparent substrates arranged to face each other with a liquid crystal interposed therebetween.

In FIG. 1, there is a transparent substrate 1, and a gate signal line 2 is formed on the surface of the transparent substrate 1 on the liquid crystal side so as to extend in the x direction and juxtaposed in the y direction. The drain signal line 3 is formed so as to be insulated from the gate signal lines 2 and extend in the y direction and be arranged in parallel in the x direction.

Unit pixel regions (regions surrounded by dotted lines A in the figure) are formed in a rectangular region surrounded by each gate signal line 2 and drain signal line 3, and these unit pixel regions are arranged in a matrix. The display section (the area surrounded by the dotted line B in the figure) is formed by the.

In each unit pixel region, a transparent pixel electrode occupying most of the unit pixel region is formed, a thin film transistor is formed on one gate signal line, and a stray capacitance is formed on the other gate signal line. ing. That is, an equivalent circuit in each unit pixel area is shown in FIG. 3, and the thin film transistor TFT is turned on by the scanning signal (voltage) supplied through the gate signal line 2, and the thin film transistor TFT is turned on via the turned on thin film transistor TFT. The pixel signal (voltage) supplied from the drain signal line 3 is applied to the pixel electrode 4. In addition, the stray capacitance Cadd
Is provided to store the pixel signal for a long time when the thin film transistor TFT is turned off. The pixel electrode 4, the thin film transistor TFT, and the stray capacitance C
The detailed configuration of add will be described later.

Then, as shown in FIG. 2, on the outer periphery of the transparent substrate 1 corresponding to the outer periphery of the display portion, the gate electrode terminal 2T constituted by the extended portion of the gate signal line 2 and the drain signal line 3 are formed. A drain electrode terminal 3T composed of the extending portion is provided.

Another transparent substrate (not shown) is arranged in the display section through the liquid crystal, and a common electrode common to each unit pixel region, a color filter and the like are arranged on the liquid crystal side surface of the transparent substrate. Has been formed. The liquid crystal is sealed between the transparent substrates by a sealing material formed on the dotted line (dotted line B) in the figure.

FIG. 1 is a plan view showing a detailed structure of the unit pixel area, and shows a view corresponding to the area A in FIG. A cross-sectional view taken along line IV-IV in FIG. 1 is shown in FIG. 4, and a cross-sectional view taken along line V-V is shown in FIG.

First, on the main surface of the transparent substrate 1, gate signal lines 2 extending in the x direction and arranged in parallel in the y direction in the figure are formed of, for example, an Al / Ta film.

A hole 2A having a larger area than that of the intersection region is provided at the intersection of the gate signal line and a later-described drain signal line 3. This hole 2A is formed after the drain signal line 3 is formed through the insulating film.
When it is discovered that an electrical short circuit with the drain signal line 3 occurs, a part of the gate signal line 2 is cut with a laser beam or the like, and only the portion where the electrical short circuit occurs is island-shaped. It is formed to be isolated from.

An anodic oxide film formed by anodization is formed on the surface (including the side surface) of the gate signal line 2. This anodic oxide film is made of Al
A so-called hillock is generated from the gate signal line 2 formed of the / Ta film, and an electrical short circuit is prevented from penetrating the insulating film and the drain signal line 3 and the like formed thereon. Even if the film (7A) has a defect, the gate line and the drain line are not short-circuited.

A disconnection defect countermeasure layer 5 made of an Al-Ta film is formed in a drain signal line 3 formation region, which will be described later. The disconnection defect countermeasure layer 5 is slightly separated from the gate signal line 2 and is drained. The central axis of the signal line 3 is substantially the same as that of the signal line 3, and the signal line 3 is formed wider. The disconnection failure countermeasure layer 5 has no anodic oxide film formed on its surface.

Further, in a region surrounded by the gate signal line 2 and the disconnection failure countermeasure layer 5, a pixel electrode 4 made of, for example, an ITO (Indium-Tin-Oxide) film is formed occupying most of the region.

An insulating film 7A made of a silicon nitride film is formed on the entire surface processed in this way. The insulating film 7A functions as a gate insulating film in the formation region of the thin film transistor TFT. Further, the insulating film 7A excludes the opening 70A exposing the central portion excluding the peripheral portion of the pixel electrode 4 and the opening 70B particularly provided in this embodiment, that is, the peripheral portion of the disconnection failure countermeasure layer 5. An opening 70B that exposes the central portion is provided.

Further, the thin film transistor TFT forming region which is overlapped with a part of one side (the upper side in the drawing) of the gate signal line 2 on the insulating film 7A and the intersection of the drain signal line 3 with the gate signal line 2 are formed. A-Si in the region
Film 7B and a-Si film 7 doped with a high concentration of n-type impurities
A sequential laminated body with C is formed (see FIG. 4). Here, in the stacked body in the formation region of the thin film transistor TFT, the a-Si film 7B is used as a semiconductor layer and a high concentration of n is obtained.
The a-Si film 7C doped with a type impurity functions as a contact layer, and the stacked body (including the insulating film 7A) 7 in the intersection region of the drain signal line 3 and the gate signal line 2 is an interlayer insulating film. It is supposed to function as.

Further, the surface thus processed has
A drain signal line 3 made of Al / Cr extending in the y-direction and arranged in parallel in the x-direction is formed. in this case,
The drain signal line 3 is formed by being laminated on the disconnection failure countermeasure layer 5 exposed from the opening 70A of the insulating film 7A (see FIGS. 4 and 5).

The drain electrode 3A of the thin film transistor TFT is formed integrally with the drain signal line 3 made of Al / Cr, and the source electrode 3B is made of the same material as the drain electrode 3A, and is adjacent to the pixel electrode 4. Is formed by being connected to.

Further, one electrode 3C of the stray capacitance Cadd is formed of Al / Cr so as to overlap with a part of the gate signal line 2 on the other side (lower side in the figure), and this electrode 3C is formed by the adjacent pixels. It is connected to the electrode 4. In the floating capacitance Cadd in this case, the other electrode is formed as the gate signal line 2 and its dielectric film is formed as the anodic oxide film and the gate insulating film (SiN) formed on the surface of the gate signal line 2. .

The surface processed in this way has
A protective film 10 made of a SiN film is formed, and the protective film 1 is formed.
An opening 0 is provided to expose the central portion of the pixel electrode except the peripheral portion.

An embodiment of a method of manufacturing a liquid crystal display substrate having such a structure will be described below in the order of steps with reference to FIGS. In each of the drawings showing the steps, the part to be processed is hatched to clarify the part.

Step 1. (FIG. 6A) An Al / Ta film having a thickness of about 3000 Å is formed on the entire main surface of the transparent substrate 1 by, for example, a sputtering method,
Then, the gate signal line 2 is formed by the selective etching method using the photolithography technique.

In this case, particularly in this embodiment, the disconnection failure countermeasure layer 5 is simultaneously formed of the Al / Ta film along the formation region of the drain signal line 3 which will be formed in a later step.

The disconnection failure countermeasure layer 5 in this case is formed slightly separated from the gate signal line 2, and
The center line is formed so as to substantially coincide with the center line of the drain signal line 3 which will be formed in a later step.

Step 2. (FIG. 6B) Only the gate signal line 2 is anodized, and an Al ₂ O ₃ film is formed on the surface (including the side surface) thereof. The film thickness of this Al ₂ O ₃ film is preferably about 1750Å.

In this case, since a voltage is not applied to the disconnection failure countermeasure layer 5 separated from the gate signal lines 2 by applying a voltage to each gate signal line 2, only the gate signal lines 2 are anodized. It can be carried out.

Step 3. (FIG. 7C) Next, ITO (Indium) is formed on the entire main surface of the transparent substrate 1 thus processed by, for example, a sputtering method.
-Tin-Oxide) film with a thickness of about 1400Å, then
The pixel electrode 4 is formed by the selective etching method using the photolithography technique.

Step 4. (FIG. 7D) Further, the SiN film 7 is formed on the entire main surface of the transparent substrate processed in this way by, for example, a plasma CVD method.
A, a-Si film 7B, and a-Si film 7C doped with a high-concentration n-type impurity are sequentially formed to form the laminated body 7. In this case, the SiN film 7A has about 220
It is preferable that the a-Si film 7B has a film thickness of 0Å, the a-Si film 7B has a film thickness of about 2100Å, and the a-Si film 7C doped with a high concentration of n-type impurity has a film thickness of about 300Å.

Then, by the selective etching method using the photolithography technique, the a-Si film 7B and the high concentration are formed only in the region where the thin film transistor is formed and the intersection with the drain signal line formed after the gate signal line. The laminated body 7 made of only the a-Si film 7C doped with the n-type impurity is left (thus, although not clearly shown in the figure, the SiN film 7A is still formed over the entire surface).

The SiN film 7A of the laminated body 7 in the thin film transistor formation region serves as a gate insulating film aS.
The i film 7B functions as a semiconductor layer, and the a-Si film 7C doped with a high concentration of n-type impurities functions as a contact layer. In addition, the stacked body 7 in the region where the gate signal line 2 intersects with the drain signal line 3 functions as an interlayer insulating film.

In this case, by selective etching of the laminate 7 to a predetermined pattern, as shown in FIG. 9A, for example, a-Si residue α remains on the main surface of the transparent substrate, and the residues are adjacent to each other. This often causes an electrical short circuit between the pixel electrodes 4 and between the pixel electrodes 4. In this case, countermeasures are taken in the steps described below without increasing the number of manufacturing steps.

Step 5. (FIG. 8E) Next, in the transparent substrate 1 processed in this way, a-
Si film 7B, a-Si doped with a high concentration of n-type impurities
The SiN film 7A formed by exposing the stacked body 7 made of only the film 7C is exposed by a selective etching method using a photolithography technique to expose the central portion of the pixel electrode 4 except the peripheral portion thereof. Opening 70
Form A.

At this time, at the same time, an opening 70B exposing the central portion of the already formed disconnection failure countermeasure layer 5 except the peripheral portion is formed.

In this selective etching, even if the residue α of a-Si is left in the previous step, the residue α is divided by the formation of the opening 70B formed in the insulating film 7A. Therefore, at this stage, the defect due to the electric short circuit due to the residue α between the adjacent pixel electrodes 4 is canceled.

Step 6. (FIG. 8F) Further, a Cr film and an a-Si film are sequentially formed on the entire main surface of the transparent substrate 1 thus processed by, for example, a sputtering method. It is preferable to form the Cr film with a thickness of about 600Å and the a-Si film with a thickness of about 3000Å.

Then, the drain signal line 3 is formed by the selective etching method using the photolithography technique. In this case, most of the drain signal line 3 is superposed on the disconnection failure countermeasure layer 5 through the opening of the insulating film 7A, so that the drain signal line 3 is formed even if the disconnection occurs for some reason. The disconnection defect countermeasure layer 5 automatically repairs the defect.

The drain electrode 3A and the source electrode 3B of the thin film transistor and one electrode 3C of the stray capacitance are formed simultaneously.

In the formation area of the thin film transistor TFT, the a-Si film 7C doped with a high concentration of impurities exposed from the drain electrode 3A and the source electrode 3B thereof.
Are removed by etching using the electrodes as masks, so that the a-Si film 7C serving as the contact layer is interposed only between the electrodes and the a-Si layer 7B serving as a semiconductor layer. Become.

Step 7. (FIG. 8G) Next, a SiN film is formed on the entire main surface of the transparent substrate 1 thus processed by, for example, a plasma CVD method, and the protective film 10 is formed by a selective etching method using a photolithography technique. Form.

This protective film 10 is formed with an opening for exposing the central portion excluding the periphery of the pixel electrode 4, and in particular, is formed so as to cover the source electrode 3B and one electrode 3C of the stray capacitance. It is supposed to be done.

The disconnection failure countermeasure layer 5 may be made of the same material as the pixel electrode 4, and can be formed at the same time when the pixel electrode 4 is formed.

Example 2. FIG. 10 is a plan view showing another configuration in the unit pixel area, and elements having the same functions as those in FIG. 1 are designated by the same reference numerals. In Figure 10, XI
A sectional view taken along the line -XI is shown in FIG. 11, and a sectional view taken along the line XII-XII is shown in FIG.

In the configuration different from that of FIG. 1, first, the SiN film 7A formed to cover the disconnection defect countermeasure layer 5 exposes a part of each of both ends along the extending direction of the disconnection defect countermeasure layer 5. The opening 70B is formed in order to make it.

The drain signal line 3 is formed intermittently, and one end of the drain signal line 3 passes through the opening to prevent the disconnection failure countermeasure layer 5.
Is to be connected to.

That is, the drain signal lines 3 are the original drain signal lines 3 formed on the upper layer of the SiN film 7A and the disconnection failure countermeasure layer 5 formed on the lower layer of the SiN film 7A.
It has a structure formed by and.

In the liquid crystal display substrate having such a structure, even if a semiconductor residue remains over the adjacent pixel regions, the residue is formed on the silicon nitride film 7 A overlapping the disconnection failure countermeasure layer 5. The probability increases.

Since the drain signal line 3 is not formed in the region where the residue is present, it is possible to eliminate the harmful effect of disconnecting the drain signal line 3 due to the residue.

An embodiment of a method of manufacturing the liquid crystal display substrate having the above structure will be described below in the order of steps with reference to FIGS.

Step 1. (FIG. 13A) An Al-Ta film is formed on the entire main surface of the transparent substrate by, for example, a sputtering method, and then the gate signal line 2 is formed by a selective etching method using a photolithography technique.

In this case, the disconnection defect countermeasure layer 5 is formed along the formation region of the drain signal line 3 which will be formed in a later step.
It is formed simultaneously with the l-Ta film.

In this case, the disconnection failure countermeasure layer 5 is formed separately from the gate signal line 2.

Step 2. (FIG. 13B) Only the gate signal line 2 is anodized, and an Al ₂ O ₃ film is formed on its surface (including the side surface).

In this case, by applying a voltage to each gate signal line 2, no voltage is applied to the disconnection failure countermeasure layer 5 separated from the gate signal line 2, so that only the gate signal line 2 is anodized. It can be carried out.

Step 3. (FIG. 14C) Next, ITO (Indium) is formed on the entire main surface of the transparent substrate 1 thus processed by, for example, a sputtering method.
-Tin-Oxide) film is formed, and then the pixel electrode 4 is formed by a selective etching method using a photolithography technique.
To form

Step 4. (FIG. 15D) Further, the SiN film 7 is formed on the entire main surface of the transparent substrate processed in this way by, for example, a plasma CVD method.
A, a-Si film 7B, and a-Si film 7C doped with a high-concentration n-type impurity are sequentially formed.

Then, the thin film transistor TFT is formed by the selective etching method using the photolithography technique.
In the region where the gate signal line 2 and the drain signal line 3 that is formed thereafter are intersected only with aS.
The laminated body 7 including the i layer 7B and the SiN film 7C is left. Although not clearly shown in the figure, the SiN film 7A exposed from the laminate 7 is in a state of being formed on the entire surface.

Here, the SiN film 7A of the laminated body 7 in the formation region of the thin film transistor TFT serves as a gate insulating film, the a-Si film 7B serves as a semiconductor layer, and a high concentration n is formed.
The a-Si film 7C doped with the type impurities functions as a contact layer. In addition, the stacked body 7 in the region where the gate signal line 2 intersects with the drain signal line 3 functions as an interlayer insulating film.

In this case, the selective etching of the laminate to a predetermined pattern leaves an a-Si residue on the main surface of the transparent substrate, and when this residue is formed in the formation region of the drain line 3, the drain is formed. It often causes the disconnection of the wire 3. In this case, countermeasures are taken in the steps described later without increasing the number of manufacturing steps.

Step 5. (FIG. 15E) Next, the SiN film 7A is selectively etched using a photolithography technique to form an opening 70A for exposing the central portion of the pixel electrode 4 excluding the peripheral portion.

At the same time, openings 70B for exposing a part of both ends of the already formed disconnection defect countermeasure layer 5 are also formed.

Step 6. (FIG. 15 (f)) Further, the Cr film and a are formed on the entire main surface of the transparent substrate processed in this way by, for example, a sputtering method.
-Si films are sequentially formed, and the drain signal line 3 is formed by a selective etching method using a photolithography technique.

In the case of this embodiment, the drain signal line 3 is particularly formed via the disconnection failure countermeasure layer 5 and is formed intermittently in the y direction in the drawing, and its end portion is formed. It is formed so as to be connected to a part of the disconnection failure countermeasure layer 5 exposed from the opening 70B formed in the SiN film 7A.

By doing so, even if the above-mentioned residue of a-Si remains in the upper layer of the SiN film 7A in the region where the drain signal line 3 is formed, the drain signal line 3 is formed over the residue. It will not happen. Therefore, there is no fear that disconnection of the drain signal line 3 due to the residue of the a-Si will occur.

Further, since the a-Si residue and the drain line are not short-circuited, the pixel electrode 4 is not affected by the signal of the drain.

In this case, the thin film transistor TFT
The drain electrode 3A and the source electrode 3B, and one electrode 3C of the stray capacitance are simultaneously formed.

Step 7. (FIG. 15G) Next, a SiN film is formed on the entire main surface of the transparent substrate processed as described above by, for example, a plasma CVD method, and a protective film 10 is formed by a selective etching method using a photolithography technique. To do.

The protective film 10 also has an opening for exposing the central portion excluding the periphery of the pixel electrode 4, and in particular, is formed so as to cover the source electrode 3B and one electrode 3C of the stray capacitance. It is supposed to be done.

The disconnection failure countermeasure layer 5 may be made of the same material as the pixel electrode 4, and can be formed at the same time when the pixel electrode 4 is formed.

Example 3. FIG. 16 is a plan view showing another configuration in the unit pixel region, and those having the same functions as those in FIG. 1 are denoted by the same reference numerals. XV in Figure 16
A cross-sectional view taken along line II-XVII is shown in FIG.
A sectional view taken along line VIII is shown in FIG.

In the structure different from that of FIG. 1, first, similarly to the second embodiment, the SiN film 7 formed to cover the disconnection failure countermeasure layer 5 is formed.
In A, an opening 70B is formed to expose a part of each of both ends along the extending direction of the disconnection failure countermeasure layer 5.

Unlike the second embodiment, the drain signal line 3 is continuously formed and is connected to the disconnection failure countermeasure layer 5 through the opening.

That is, the drain signal line 3 is the same as the original drain signal line 3 formed on the upper layer of the SiN film 7A.
It is formed by the disconnection failure countermeasure layer 5 formed under the iN film 7A and has a branch path.

In the liquid crystal display substrate thus configured, even if the drain signal line 3 is disconnected for some reason when the original drain signal line 3 is formed, the drain signal protection layer 5 prevents the drain signal line 3 from being disconnected. The effect of having the function of the line 3 comes to be exhibited.

In this case, in the above structure, the laminated body 7 of the a-Si layer 7B and the a-Si layer 7C doped with the high concentration impurity is provided around the opening 70 where the drain signal line 3 is formed. The drain signal line 3 is formed so that the adverse effect caused by the disconnection of the drain signal line 3 formed over the step of the opening 70 can be eliminated.

An embodiment of a method of manufacturing the liquid crystal display substrate having the above structure will be described below in the order of steps with reference to FIGS.

Step 1. (FIG. 19A) An Al-Ta film is formed on the entire main surface of the transparent substrate by, for example, a sputtering method, and then the gate signal line 2 is formed by a selective etching method using a photolithography technique.

In this case, the disconnection failure countermeasure layer 5 is formed along the formation region of the drain signal line 3 which will be formed in a later step.
It is formed simultaneously with the l-Ta film.

In this case, the disconnection failure countermeasure layer 5 is formed separately from the gate signal line 2.

Step 2. (FIG. 19B) Only the gate signal line 2 is anodized, and an Al ₂ O ₃ film is formed on its surface (including side surfaces).

In this case, by applying a voltage to each gate signal line 2, no voltage is applied to the disconnection failure countermeasure layer 5 separated from the gate signal line 2, so that only the gate signal line 2 is anodized. It can be carried out.

Step 3. (FIG. 20 (c)) Next, ITO (Indium-T) is formed on the entire main surface of the transparent substrate thus processed by, for example, a sputtering method.
An in-Oxide) film is formed, and then the pixel electrode 4 is formed by a selective etching method using a photolithography technique.

Step 4. (FIG. 20 (d)) Furthermore, the SiN film 7 is formed on the entire main surface of the transparent substrate processed in this way by, for example, a plasma CVD method.
A, a-Si film 7B, and a-Si film 7C doped with a high-concentration n-type impurity are sequentially formed.

Then, by the selective etching method using the photolithography technique, the a-Si film 7B and the high concentration of the a-Si film 7B are formed in the region where the thin film transistor is formed and the intersection with the drain signal line formed after the gate signal line. The stacked body 7 made up of only the a-Si film 7C doped with the n-type impurity is left (thus, although not clearly shown in the figure, the SiN film 7A is still formed over the entire surface).

The SiN film 7A of the stacked body 7 in the thin film transistor formation region serves as a gate insulating film aS.
The i film 7B functions as a semiconductor layer, and the a-Si film 7C doped with a high concentration of n-type impurities functions as a contact layer. In addition, the stacked body 7 in the region where the gate signal line 2 intersects with the drain signal line 3 functions as an interlayer insulating film.

Then, in this case, in the next step, in the periphery of the opening 70B formed in the SiN film 7A and also in the region where the drain signal line 3 is to be formed, the a-Si layer 7B and the high concentration are formed. The stacked body of the a-Si film 7C doped with impurities is left.

Step 5. (FIG. 21E) Next, an opening 70A for exposing the central portion of the SiN film 7A except the peripheral portion of the pixel electrode 4 is formed by a selective etching method using a photolithography technique.

In this case, the opening 7 for exposing a part of each of both ends of the disconnection failure countermeasure layer 5 already formed.
OB is simultaneously formed by the selective etching.

Step 6. (FIG. 21 (f)) Furthermore, the Cr film and the A
The l-Si film is sequentially formed, and the drain signal line 3 is formed by the selective etching method using the photolithography technique. The drain signal line 3 is connected to a part of each end of the disconnection failure countermeasure layer 5 through the opening 70B of the SiN film 7A, and as a result, two drain signal lines having different layers are formed. Will be done.

Therefore, even if the drain signal line made of the Al--Si film is disconnected for some reason, the disconnection failure countermeasure layer 5
The effect that the function of the drain line can be maintained through the effect is obtained.

In this case, the thin film transistor TFT
The drain electrode 3A and the source electrode 3B, and one electrode 3C of the stray capacitance are simultaneously formed.

Step 7. (FIG. 21G) Next, a SiN film is formed on the entire main surface of the transparent substrate processed in this way by, for example, a plasma CVD method, and a protective film 10 is formed by a selective etching method using a photolithography technique. To do.

This protective film 10 is formed with an opening for exposing the central portion excluding the periphery of the pixel electrode 4, and in particular, is formed so as to cover the source electrode 3B and one electrode 3C of the stray capacitance. It is supposed to be done.

The fault defect countermeasure layer 5 may be made of the same material as the pixel electrode 4, and can be formed at the same time when the pixel electrode 4 is formed.

Embodiment 4 FIG . 22 is a plan view showing another configuration in the unit pixel region, and those having the same functions as those in FIG. 1 are denoted by the same reference numerals. In FIG. 22, XX
A cross-sectional view taken along line III-XXIII is shown in FIG.
A sectional view taken along the line XXVI is shown in FIG.

The structure different from that of FIG. 1 is that the pattern of the SiN film 7A is different. That is, the SiN film 7
A is formed in the same pattern as the laminated body 7 of the a-Si film 7B superposed on the upper layer and the a-Si film 7C doped with the high-concentration layer, and is the region other than that, which is the pixel electrode 4 and the gate signal. The line 2 or the like is not formed in the formation region.

Also in this case, since the drain signal line 2 is formed so as to overlap the disconnection failure countermeasure layer 5, even if the disconnection occurs due to some reason when the drain signal line 2 is formed, the disconnection failure countermeasure layer 5 is formed. The defect countermeasure layer 5 can have the effect of being automatically repaired.

An embodiment of a method of manufacturing the liquid crystal display substrate having the above structure will be described below in the order of steps with reference to FIGS. 25 to 26. In each of the drawings showing the steps, the part to be processed is hatched to clarify the part.

Step 1. (FIG. 25A) An Al / Ta film is formed on the entire main surface of the transparent substrate 1 by, for example, a sputtering method, and then the gate signal line 2 is formed by a selective etching method using a photolithography technique.

In this case, particularly in this embodiment, the disconnection failure countermeasure layer 5 is simultaneously formed of the Al / Ta film along the formation region of the drain signal line 3 which will be formed in a later step.

Step 2. (FIG. 25B) Only the gate signal line 2 is anodized, and an Al ₂ O ₃ film is formed on its surface (including the side surface).

In this case, by applying a voltage to each gate signal line 2, no voltage is applied to the disconnection failure countermeasure layer 5 separated from the gate signal line 2, so that only the gate signal line 2 is anodized. It can be carried out.

Step 3. (FIG. 26C) Next, ITO (Indium) is formed on the entire main surface of the transparent substrate 1 thus processed by, for example, a sputtering method.
-Tin-Oxide) film is formed, and then the pixel electrode 4 is formed by a selective etching method using a photolithography technique.
To form

Step 4. (FIG. 26 (d)) Furthermore, the SiN film 7 is formed on the entire main surface of the transparent substrate processed in this manner, for example, by the plasma CVD method.
A, a-Si film 7B, and a-Si film 7C doped with a high-concentration n-type impurity are sequentially formed to form the laminated body 7.

Then, by the selective etching method using the photolithography technique, the SiN films 7A, aS are formed only in the region where the thin film transistor is formed and the intersection with the drain signal line formed after the gate signal line.
The laminated body 7 consisting only of the i film 7B and the a-Si film 7C doped with a high-concentration n-type impurity is left (for this reason, although not shown in the drawing, unlike the first embodiment, S
The iN film 7A is not formed in a region other than the region where the laminate 7 is formed). This is to reduce the number of manufacturing steps.

The SiN film 7A of the laminated body 7 in the thin film transistor formation region serves as a gate insulating film, and is aS.
The i film 7B functions as a semiconductor layer, and the a-Si film 7C doped with a high concentration of n-type impurities functions as a contact layer. In addition, the stacked body 7 in the region where the gate signal line 2 intersects with the drain signal line 3 functions as an interlayer insulating film.

Step 5. (FIG. 27E) Further, a Cr film and an a-Si film are sequentially formed on the entire main surface of the transparent substrate 1 thus processed by, for example, a sputtering method.

Then, the drain signal line 3 is formed by the selective etching method using the photolithography technique. In this case, since the drain signal line 3 is directly overlapped with the disconnection failure countermeasure layer 5 formed in advance, even if the drain signal line 3 is formed due to some reason, the disconnection failure countermeasure layer 5 is formed. By 5 the repair will be done automatically.

Then, the drain electrode 3A and the source electrode 3B of the thin film transistor and one electrode 3C of the floating capacitance are formed simultaneously.

Step 6. (FIG. 27F) Next, a SiN film is formed on the entire main surface of the transparent substrate 1 thus processed by, for example, a plasma CVD method, and the protective film 10 is formed by a selective etching method using a photolithography technique. Form.

This protective film 10 is formed with an opening for exposing the central portion excluding the periphery of the pixel electrode 4, and particularly formed so as to cover the source electrode 3B and one electrode 3C of the stray capacitance. It is supposed to be done.

The fault defect countermeasure layer 5 may be made of the same material as the pixel electrode 4, and can be formed at the same time when the pixel electrode 4 is formed.

Example 5. FIG. 28 is a plan view showing another configuration in the unit pixel area, and elements having the same functions as those in FIG. 1 are designated by the same reference numerals. In FIG. 28, XX
29 is a sectional view taken along line IX-XXIX, and XXX-XX.
A cross-sectional view taken along the line X is shown in FIG.

Most of this structure is almost the same as the structure shown in Embodiment 2 (see FIGS. 10, 11 and 12), but an ITO (Indium-Tin-Oxide) film is formed on the surface of the disconnection failure countermeasure layer 5. There is a difference in that the second disconnection failure countermeasure layer 5A consisting of is directly laminated.

The second disconnection failure countermeasure layer 5A can automatically repair the disconnection failure countermeasure layer 5 when the disconnection failure countermeasure layer 5 is formed, and by forming the pixel electrode 4 at the same time, the number of manufacturing steps can be increased. The above-mentioned effects can be achieved without bringing about the above.

In this case, the second ITO film is used.
When the connection between the disconnection failure countermeasure layer and the drain signal line 3 is attempted, if the gate signal line 2 is made of Al, the connection is not sufficiently made. Therefore, the drain signal line 3 is interposed with the Cr layer interposed. Is preferred.

Needless to say, the structure in which the ITO film is laminated on the surface of the disconnection failure countermeasure layer 5 is not limited to the structure shown in the second embodiment and can be applied to the other embodiments.

[0135]

As is apparent from the above description,
According to the present invention, it is possible to obtain a liquid crystal display substrate having a configuration in which disconnection of the drain signal line is hard to occur.

Further, it is possible to obtain a liquid crystal display substrate having a structure in which the adverse effects of the presence of residues such as semiconductors are eliminated.

Further, it is possible to obtain a method of manufacturing a liquid crystal display substrate in which disconnection of the drain signal line is hard to occur.

Furthermore, it is possible to obtain a method of manufacturing a liquid crystal display substrate, which eliminates the harmful effects of the presence of residues such as semiconductors.

[Brief description of drawings]

FIG. 1 is a plan view showing an example of a unit pixel region in a liquid crystal display substrate according to the present invention.

FIG. 2 is a plan view showing an example of the configuration of one transparent substrate of the liquid crystal display substrate according to the present invention on the liquid crystal side.

FIG. 3 is a plan view showing an embodiment of an equivalent circuit of a unit pixel area in a liquid crystal display substrate according to the present invention.

FIG. 4 is a sectional view taken along line IV-IV in FIG.

FIG. 5 is a sectional view taken along line VV of FIG. 1;

FIG. 6 is a part of a process chart showing an embodiment of a method for manufacturing a liquid crystal display substrate according to the present invention.

FIG. 7 is a part of a process chart showing an embodiment of a method for manufacturing a liquid crystal display substrate according to the present invention.

FIG. 8 is a part of a process chart showing an embodiment of a method for manufacturing a liquid crystal display substrate according to the present invention.

FIG. 9 is an explanatory diagram showing the effect of the method for manufacturing a liquid crystal display substrate according to the present invention.

FIG. 10 is a plan view showing an example of a unit pixel region in a liquid crystal display substrate according to the present invention.

11 is a sectional view taken along line XI-XI in FIG.

12 is a sectional view taken along line XII-XII in FIG.

FIG. 13 is a part of a process chart showing another embodiment of the method of manufacturing a liquid crystal display substrate according to the present invention.

FIG. 14 is a part of a process chart showing another embodiment of the method for manufacturing a liquid crystal display substrate according to the present invention.

FIG. 15 is a part of a process chart showing another embodiment of the method for manufacturing a liquid crystal display substrate according to the present invention.

FIG. 16 is a plan view showing an example of a unit pixel region in a liquid crystal display substrate according to the present invention.

17 is a sectional view taken along line XVII-XVII in FIG.

18 is a sectional view taken along line XVIII-XVIII in FIG.

FIG. 19 is a part of a process chart showing another embodiment of the method for manufacturing a liquid crystal display substrate according to the present invention.

FIG. 20 is a part of a process chart showing another embodiment of the method of manufacturing a liquid crystal display substrate according to the present invention.

FIG. 21 is a part of a process chart showing another embodiment of the method of manufacturing a liquid crystal display substrate according to the present invention.

FIG. 22 is a plan view showing an example of a unit pixel region in a liquid crystal display substrate according to the present invention.

23 is a sectional view taken along line XXIII-XXIII in FIG.

24 is a cross-sectional view taken along line XXVI-XXVI of FIG.

FIG. 25 is a part of a process chart showing another embodiment of the method of manufacturing a liquid crystal display substrate according to the present invention.

FIG. 26 is a part of a process chart showing another embodiment of the method for manufacturing a liquid crystal display substrate according to the present invention.

FIG. 27 is a part of a process chart showing another embodiment of the method of manufacturing a liquid crystal display substrate according to the present invention.

FIG. 28 is a plan view showing an example of a unit pixel region in a liquid crystal display substrate according to the present invention.

FIG. 29 is a sectional view taken along line XXIX-XXIX in FIG. 22.

FIG. 30 is a sectional view taken along the line XXX-XXX of FIG. 22.

[Explanation of symbols]

2 ... Gate signal line, 3 ... Drain signal line, 4 ... Pixel electrode, 5 ... Layer for preventing disconnection defect, 7 ... Laminated body, 7A ...
... SiN film, 7B ... a-Si layer, 7C ... a-Si layer doped with high concentration impurities, 10 ... protective film, TFT
... thin film transistor, Cadd ... stray capacitance.

Claims (11)

[Claims] 1. A thin film transistor which is turned on by supplying a scanning signal by a gate signal line to each pixel region on the liquid crystal side surface of one of the transparent substrates arranged to face each other with a liquid crystal interposed therebetween, and a thin film transistor which is turned on. In the liquid crystal display substrate in which the pixel signal is supplied from the drain signal line through the thin film transistor, the drain signal line is positioned in a layer above the gate signal line, the drain signal A conductive disconnection defect countermeasure layer is formed under the insulating film in the line formation region, and the disconnection defect countermeasure layer is formed separately from the gate signal line and at least in the central portion except its peripheral portion. Is exposed from the opening formed in the insulating film and is formed so as to overlap with the drain signal line. Board. 2. A step of forming a disconnection failure countermeasure layer together with a gate signal line, a step of forming a pixel electrode, a step of forming an insulating film, a step of forming a semiconductor layer, and the disconnection failure in the insulating film. The method for manufacturing a liquid crystal display substrate according to claim 1, comprising a step of forming an opening exposing the countermeasure layer and a step of forming a drain signal line. 3. A thin film transistor which is turned on by supplying a scanning signal through a gate signal line to each pixel region on the liquid crystal side surface of one of the transparent substrates which are arranged to face each other with a liquid crystal interposed therebetween, and the thin film transistor. In the liquid crystal display substrate in which the pixel signal is supplied from the drain signal line through the thin film transistor, the drain signal line is positioned in a layer above the gate signal line, the drain signal A conductive disconnection defect countermeasure layer is formed under the insulating film in the line formation region, and the disconnection defect countermeasure layer is formed separately from the gate signal line, and both ends thereof are exposed from the insulating film. A liquid crystal display substrate, which constitutes a part of a drain signal line formed on the insulating film through the opening. 4. A step of forming a disconnection failure countermeasure layer together with a gate signal line, a step of forming a pixel electrode, a step of forming an insulating film, a step of forming a semiconductor layer, and the disconnection failure in the insulating film. 4. The method for manufacturing a liquid crystal display substrate according to claim 3, comprising a step of forming an opening exposing the countermeasure layer and a step of forming a drain signal line. 5. A thin film transistor which is turned on by supplying a scanning signal by a gate signal line to each pixel region on the liquid crystal side surface of one of the transparent substrates which are arranged to face each other with a liquid crystal interposed therebetween, and the thin film transistor. In the liquid crystal display substrate in which the pixel signal is supplied from the drain signal line through the thin film transistor, the drain signal line is positioned in a layer above the gate signal line, the drain signal A conductive disconnection defect countermeasure layer is formed under the insulating film in the line formation region, and the disconnection defect countermeasure layer is formed separately from the gate signal line, and both ends thereof are exposed from the insulating film. A liquid crystal display substrate, characterized in that a branch path of a drain signal line formed on the insulating film is constituted through the opening. 6. A step of forming a disconnection failure countermeasure layer together with a gate signal line, a step of forming a pixel electrode, a step of forming an insulating film, a step of forming a semiconductor layer, and the disconnection failure in the insulating film. The method for manufacturing a liquid crystal display substrate according to claim 5, comprising a step of forming an opening exposing the countermeasure layer and a step of forming a drain signal line. 7. A thin film transistor which is turned on by supplying a scanning signal by a gate signal line to each pixel region on the liquid crystal side surface of one of the transparent substrates arranged to face each other with a liquid crystal interposed therebetween, and the thin film transistor. In the liquid crystal display substrate in which the pixel signal is supplied from the drain signal line through the thin film transistor, the drain signal line is positioned in a layer above the gate signal line, the drain signal The line is formed so as to overlap the conductive disconnection failure countermeasure layer, and the disconnection failure countermeasure layer is formed separately from the gate signal line. 8. A step of forming a disconnection failure countermeasure layer together with a gate signal line, a step of forming a pixel electrode, a step of sequentially forming a laminated body of an insulating film and a semiconductor layer, and at least the disconnection failure countermeasure layer. The manufacturing of a liquid crystal display substrate according to claim 7, comprising a step of selectively etching the semiconductor layer and the insulating film of the laminated body in the same pattern so as to expose the whole, and a step of forming a drain signal line. Method. 9. The disconnection failure countermeasure layer is formed of the same material as the gate signal line.
The liquid crystal display substrate according to any one of 3, 5, and 7. 10. The gate signal line is made of Al or its alloy, and an oxide film is formed on its surface by anodization.
5. The liquid crystal display substrate according to any one of 5 and 7. 11. The disconnection defect countermeasure layer has a laminated structure in which the same material layer as the pixel electrode is formed as an upper layer, and the disconnection failure countermeasure layer has a laminated structure. LCD display board.