JPH0922876A - Production of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form a shallow impurity layer with a small parasitic resistance by allowing the peak position of concentration distribution of a first element to exist in an element separation film so that the depth of the first impurity layer may be smaller than that of a second element, by forming an element separation film on a semiconductor substrate prior to irradiation. SOLUTION: A field oxide film 12 is formed on the surface of a silicon substrate 11. A gate oxide film 13, first-layer gate electrode 14a, second-layer gate electrode 14b, and gate upper insulation film 15 are successively formed on the substrate 11, and the laminated layer is etched to form a gate part therein. Then, a shallow p-type source/drain layer 16 is formed by means of a silicon oxide film 13a. The film 13a including C1 is removed to form a drain layer 16 and a gate-side wall insulation film 17 is formed through anisotropic etching. Ions are implanted to the surface of the substrate while the gate part and film 17 are used as a mask, so as to form a p-type source/drain layer 18. Thus an impurity layer with a samll parasitic resistance can be formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device characterized by a method of forming an impurity layer.

[0002]

2. Description of the Related Art In recent years, a large-scale integrated circuit (IC) formed by integrating a large number of transistors, resistors and the like into an important part of a computer or a communication device so as to achieve an electric circuit has been integrated on one chip. LSI) is frequently used. For this reason, the performance of the entire device is greatly related to the performance of the LSI alone.

[0003] The performance of an LSI alone can be improved by increasing the degree of integration, that is, by miniaturizing elements. However, with respect to miniaturization of elements, various process problems are currently occurring.

For example, taking a MOS transistor as an example, there are the following problems. Since the parasitic resistance of the source / drain layers increases with miniaturization, it is necessary to increase the impurity concentration of the source / drain layers. In addition, since the short channel effect becomes remarkable with miniaturization, it is necessary to make the depth of the source / drain layer shallow.

The source / drain layers are usually formed by an ion implantation method. However, in the case of forming by the ion implantation method, it is difficult to form a shallower source / drain layer because there is a limit to lowering the implantation energy.

As an alternative doping method to the ion implantation method, there are, for example, a plasma doping method and an ion shower doping method. According to these doping methods, since the impurity source can be doped with a low acceleration voltage, shallow source / drain layers can be formed.

However, this type of doping method has the following problems. First, since doping is performed without performing mass separation of the impurity source, impurities (different impurities) that do not contribute to the formation of the impurity layer are also doped.

For example, in the case of the plasma doping method, B ₂ H ₆ is used as an impurity source. B ₂ H ₆ is a commonly used impurity source because of its high ionization efficiency. However, since H is an element lighter than B, H
Is doped to a region deeper than B, and H causes many defects to be formed in a deep region. In addition, since H is not removed from the impurity layer by the subsequent heat treatment, H
The effect of will remain until later.

Further, in the case of a doping method such as a plasma doping method or an ion shower doping method, since the semiconductor substrate is exposed to a plasma atmosphere, the substrate surface is damaged by the plasma and ions.

Therefore, by the above doping method,
Even if a shallow source / drain layer is formed by doping impurities such as B at a high concentration, it is difficult to reduce the parasitic resistance due to foreign impurities such as H in the source / drain layers and damage to the substrate surface.

[0011]

As described above, according to the conventional plasma doping method or ion shower doping method, it is possible to form the source / drain layer shallower than the ion implantation method. It was difficult to reduce the parasitic resistance due to foreign impurities inside and damage to the substrate surface.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a method of manufacturing a semiconductor device capable of reducing the parasitic resistance of an impurity layer. A further object of the present invention is to provide a method for manufacturing a semiconductor device, which can form a shallow impurity layer having a small parasitic resistance.

[0013]

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention (claim 1).
Is a substance composed of only a first element having a mass higher than that of hydrogen and a second element having a mass higher than that of hydrogen and a mass lower than that of the first element as an impurity source, Irradiation without separation, when forming an impurity layer on the surface portion of the semiconductor substrate, an element separation film is formed on the semiconductor substrate before the irradiation, and by this element separation film,
The irradiated impurity source is changed to the first element and the second element so that the depth of the impurity layer of the first element formed on the surface portion of the semiconductor substrate is shallower than that of the second element. And the peak position of the concentration distribution of the first element is in the element separation film.

Here, the first element does not mean only one element, but also a plurality of elements composed of a plurality of kinds of elements. Similarly, the second element does not mean only one element, but also a plurality of elements composed of a plurality of kinds of elements.

Another method of manufacturing a semiconductor device according to the present invention (claim 2) is the method of manufacturing a semiconductor device according to claim 1 wherein the semiconductor substrate is a silicon substrate and the impurity source is the first source. Is ClCl or Br, and the second element is B, BCl ₃ or BBr ₃ , and the element isolation film is a silicon oxide film or a silicon nitride film.

Another method of manufacturing a semiconductor device according to the present invention (claim 3) is the same as the method of manufacturing a semiconductor device (claim 1), wherein the element isolation film has a thickness of 1 nm or more and 1 nm or more.
It is characterized by being less than 0 nm.

Another method of manufacturing a semiconductor device according to the present invention (claim 4) is the same as the method of manufacturing a semiconductor device (claim 1), wherein the substance of the impurity source is a plasma doping method or an ion shower doping method. And accelerates the irradiation to irradiate the semiconductor substrate.

Another method of manufacturing a semiconductor device according to the present invention (claim 5) is the same as the method of manufacturing a semiconductor device (claim 4), wherein the acceleration voltage of the impurity source material is 1.
It is characterized by being 5 KeV or less.

[0019]

According to the present invention (Claims 1 to 5), as an impurity source, a first element having a mass higher than that of hydrogen and a mass higher than that of hydrogen and lighter than the first element are used. Since the impurity layer is formed by irradiating the substance consisting of only the second element of the mass, that is, the substance not containing the hydrogen element, it is possible to prevent the parasitic resistance from increasing due to the hydrogen element.

Further, according to the present invention (claims 1 to 5), since the depth of the impurity layer of the first element is shallower than that of the second element, the second element is set to a predetermined amount. When used as an impurity element forming a conductivity type, it is the impurity layer of the second element that forms a junction with the semiconductor substrate. Therefore, a problem (for example, junction leak) due to the junction between the semiconductor substrate and the impurity layer of the first element which does not form a predetermined conductivity type does not occur.

FIG. 3 shows a silicon substrate as a semiconductor substrate,
SiO ₂ film as an element separation film, BBr ₃ as an impurity source
It is a figure which shows the concentration distribution of each element at the time of using. From FIG. 3, the peak position of the Br (first element) concentration distribution is in the SiO ₂ film, and Br is almost absent on the substrate surface portion, and most of it is present in the SiO ₂ film. . On the other hand, it is understood that a large amount of B (second element) is present not only in the SiO ₂ film but also on the substrate surface portion.
Furthermore, B has a higher concentration than Br at any depth,
It is also found that the high concentration exists in the region deeper than Br.

That is, BBr ₃ is separated into Br and B by the SiO ₂ film so that the depth of the impurity layer of Br formed on the surface of the silicon substrate is shallower than that of B, and The peak position of the Br concentration distribution is SiO
It can be seen that it is in _two films.

FIG. 4 shows the experimental results that triggered the creation of the present invention. FIG. 4 is a characteristic showing the relationship between the substrate surface density of each element and the oxide film thickness when BCl ₃ and BBr ₃ are plasma-doped (accelerating voltage 1 keV, 1.5 keV) on a silicon substrate having an oxide film formed on the surface. It is a figure.

From FIG. 4, the substrate areal densities of Cl and Br decrease with an increase in the oxide film thickness, and sharply decrease from 5 nm in the case of 1 keV and 10 nm in the case of 1.5 keV. I understand. On the other hand, it can be seen that the substrate areal density of B does not decrease sharply until the oxide film thickness increases to around 20 nm. That is, it was found that the lighter element has a higher surface areal density regardless of the oxide film thickness.

When the thickness of the element separation film is set as in the present invention (claim 3), most of the first element is trapped in the element separation film without reaching the semiconductor substrate. Therefore, most of the second element can be removed by removing the element separation film in a later step. Furthermore, etching of the surface of the semiconductor substrate by the first element can be effectively prevented.

FIG. 5 shows a silicon substrate as a semiconductor substrate,
SiO ₂ film as element separation film, BBr as impurity source
₃ is a characteristic diagram showing the relationship between the amount of shaving (Si shaving amount) on the surface of a silicon substrate and the film thickness (oxide film thickness) of a SiO ₂ film when BCl ₃ is used.

From FIG. 5, in the case of BBr ₃ and BCl, if the film thickness of the SiO ₂ film is set to 3 nm or more, Si
It can be seen that the amount of abrasion is sufficiently low, and most of Br and Cl are trapped in the SiO ₂ film without reaching the surface of the silicon substrate. The upper limit is 10 nm from a practical viewpoint. Such results were obtained for other sources of impurities.

According to the present invention (claims 4 and 5), since the plasma doping method and the ion shower doping method are used, a shallow impurity layer can be formed. In this case, as described above, there are no problems due to the hydrogen element and no problems such as junction leak, and since the substrate surface is covered with the element separation film, damage due to plasma or ions does not occur. Therefore, a shallow impurity layer having a small parasitic resistance can be formed.

[0029] Figure 6, the BBr _3, B ₂ H ₆ by B concentration 10 ¹⁷ cm ^-3 in the case of forming an impurity layer of B (high concentration) BBr _3, B acceleration voltage of ₂ H ₆ and the impurity layer It is a characteristic view which shows the relationship with depth. A silicon substrate is used as the semiconductor substrate, and a SiO ₂ film is used as the element separation film.

From FIG. 6, when BBr ₃ (the present invention: an impurity source containing no hydrogen) is used, the acceleration voltage is 1.5 k.
It can be seen that a sufficiently thin high-concentration impurity layer can be formed even at eV or less.

On the other hand, when B ₂ H ₆ (conventional: an impurity source containing hydrogen) is used, a high-concentration impurity layer can be formed, but a sufficiently high-concentration impurity layer can be formed even if the accelerating voltage is lowered. It turns out that cannot be formed.

Thus, according to the present invention, 1.5 keV
Since a sufficiently thin high-concentration impurity layer can be formed even with the following low acceleration voltage, the acceleration voltage can be lowered, and thus the damage on the substrate surface can be further reduced as compared with the conventional case.

[0033]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described with reference to the drawings. (First Embodiment) FIGS. 1A to 1D are process sectional views showing a method for forming a MOS transistor according to a first embodiment of the present invention.

First, as shown in FIG. 1A, a field oxide film 12 is formed on the surface of a single crystal silicon substrate 11 by thermal oxidation. Next, as shown in FIG. 1B, a silicon oxide film to be the gate oxide film 13 and a polycrystalline silicon film to be the first-layer gate electrode 14a are formed on the substrate in the element formation region surrounded by the field oxide film 12. , A tungsten film to be the second-layer gate electrode 14b, and a silicon nitride film to be the upper-gate insulating film 15 are sequentially formed, and then these laminated films are etched to form the gate oxide film 13, the first-layer gate electrode 14a, A gate portion composed of the second-layer gate electrode 14b and the gate upper insulating film 15 is formed.

At this time, the silicon oxide film 13a (element isolation film) to be the gate oxide film 13 other than the gate region is left without being removed by etching. Silicon oxide film 1
The film thickness of 3a is 1 nm or more and less than 10 nm.

Next, as shown in FIG. 1C, a p-type impurity is introduced into the surface of the substrate through the remaining silicon oxide film 13a as an element isolation film by plasma doping to obtain 0.15 μm. Shallow p-type source / drain layer 1 below
6 is formed.

Specifically, the plasma doping is
The BCl ₃ gas is introduced at a flow rate = 100 SCCM into the chamber as the doping gas, while controlling the pressure in the chamber to 1 Pa, the BCl ₃ gas 13.5
It is performed by applying a high frequency of 6 kW or more and a power of 0.8 KW. The acceleration voltage is set to 1.5 keV or less.

In this embodiment, in the plasma doping method, a doping gas containing no hydrogen element is used, a silicon oxide film 13a having a predetermined thickness is used as an element separation film, and the acceleration voltage is set to 1.5 keV or less. Therefore, the parasitic resistance and the leak current of the shallow p-type source / drain layer 16 can be sufficiently reduced by the above-described operation.

Next, as shown in FIG. 1D, after removing the silicon oxide film 13a containing Cl that does not contribute to the formation of the p-type source / drain layer 16, a silicon nitride film to be the gate sidewall insulating film 17 is formed. By forming the silicon nitride film on the entire surface by the CVD method and then etching the entire surface of the silicon nitride film by anisotropic etching, for example, reactive ion etching, the silicon nitride film is selectively left on the side wall of the gate portion, thereby insulating the gate side wall. The film 17 is formed.

At this time, a silicon nitride film may be formed on the entire surface while leaving the silicon oxide film 13a, and then the entire surface may be etched. In this case, the gate sidewall insulating film 1
The silicon oxide film 13a remains at the bottom of 7.

Finally, as shown in FIG. 3D, B is ion-implanted into the substrate surface under the conditions of an acceleration voltage of 5 keV and a dose amount of 1 × 10 ¹⁵ cm ^{-2 using} the gate portion and the gate sidewall insulating film 17 as a mask. After that, an annealing process is performed to form the p-type source / drain layer 18 in a self-aligned manner, and the LD
The D structure MOS transistor is completed. (Second Embodiment) FIGS. 2A to 2D are process sectional views showing a method of forming a MOS transistor according to a second embodiment of the present invention.

First, as shown in FIG. 2A, a field oxide film 22 is formed on the surface of a single crystal silicon substrate 21 by thermal oxidation. Next, as shown in FIG. 2B, a silicon oxide film to be the gate oxide film 23 and a polycrystalline silicon film to be the first-layer gate electrode 24a are formed on the substrate in the element formation region surrounded by the field oxide film 22. , A tungsten film to be the second-layer gate electrode 24b, and a silicon nitride film to be the upper-gate insulating film 25 are sequentially formed, and then these laminated films are etched to form the gate oxide film 23, the first-layer gate electrode 24a, A gate portion including the second-layer gate electrode 24b and the gate upper insulating film 25 is formed.

At this time, the silicon oxide film to be the gate oxide film 23 other than the gate region is completely removed by etching so as not to remain. Next, as shown in FIG.
Thin silicon nitride film 2 using CVD method and thermal nitriding method
After 6 (element isolation film) is formed on the entire surface, a silicon nitride film 26 as an element isolation film is formed by a plasma doping method.
P-type impurities are introduced into the substrate surface through 0.15 μm
A shallow p-type source / drain layer 27 of m or less is formed.
The film thickness of the silicon nitride film 26 is 1 nm or more and less than 10 nm.

Specifically, the plasma doping is
The BCl ₃ gas is introduced at a flow rate = 100 SCCM into the chamber as the doping gas, while controlling the pressure in the chamber to 1 Pa, the BCl ₃ gas 13.5
It is performed by applying a high frequency of 6 kW or more and a power of 0.8 KW. The acceleration voltage is set to 1.5 keV or less.

In this embodiment, in the plasma doping method, a doping gas containing no hydrogen element is used, a silicon nitride film 26 having a predetermined film thickness is used as an element separation film, and the acceleration voltage is set to 1.5 keV or less. Therefore, the parasitic resistance of the shallow p-type source / drain layer 27 and the leak current can be sufficiently reduced by the above-described operation.

Next, as shown in FIG. 2D, after removing the silicon nitride film 26 containing Cl that does not contribute to the formation of the p-type source / drain layer 27, a silicon nitride film to be the gate sidewall insulating film 28 is removed. The gate sidewall insulating film is formed by CVD on the entire surface, and then the silicon nitride film is anisotropically etched, for example, by reactive ion etching to leave the silicon nitride film selectively on the sidewalls of the gate portion. 28 is formed.

At this time, the entire surface may be etched after forming the silicon nitride film on the entire surface while leaving the silicon nitride film 26. In this case, the gate sidewall insulating film 28
The silicon nitride film 26 remains under the.

Finally, as shown in FIG. 7D, B is ion-implanted into the substrate surface under the conditions of an acceleration voltage of 5 keV and a dose amount of 1 × 10 ¹⁵ cm ^{-2 using} the gate portion and the gate sidewall insulating film 28 as a mask. After that, an annealing process is performed to form the p-type source / drain layer 29 in a self-aligned manner, and the LD
The D structure MOS transistor is completed.

The present invention is not limited to the above embodiment. For example, in the above embodiment, the case of the MOS transistor has been described, but the present invention can be applied to other elements.

In the above embodiment, the case where the plasma doping method is used has been described, but the present invention can be applied to the ion shower doping method and other doping methods that do not perform mass separation.

[0051] Further, if the doping gas in the case of forming a p-type impurity layer, in addition to BCl _3, for example BBr ₃
Compounds of other Group III elements and halogen elements can be used. Further, in the case of forming the n-type impurity layer, a compound of a V group element and a halogen element can be used. However, the mass relationship of the present invention is only satisfied.

Further, in the above embodiment, the element forming the impurity layer is only one kind, but it may be plural kinds. Similarly, there may be a plurality of elements that do not form impurities. Further, although an oxide film or a nitride film is used as the element isolation film in the above-described embodiment, another insulating film such as a carbide film may be used. Further, a semiconductor film, a metal film, or a metal compound film may be used instead of the insulating film. That is, as long as the impurity source can be separated into the first element and the second element and the impurity layer of the first element and the impurity of the second element can be formed in a predetermined manner, what kind of film is used. Is also good.

Although the element separation film is removed after the doping in the above embodiment, it may be left as it is.
Further, an etching chamber may be used instead of using a dedicated chamber as a chamber for doping.
That is, doping may be performed in the etching chamber by replacing the etching gas in the etching chamber with the doping gas. By doing this,
It becomes possible to continuously perform etching and doping in the same chamber.

In the above description, the number of chambers in the apparatus is assumed to be one, but each chamber may be used for etching and doping even when there are a plurality of chambers in one apparatus. Further, the etching device and the doping device may be separate. Other,
Various modifications can be made without departing from the scope of the present invention.

[0055]

As described above in detail, according to the present invention, when the semiconductor substrate is irradiated with the impurity source without mass separation to form an impurity layer on the surface of the substrate, hydrogen element is not contained as the impurity source. It is possible to form an impurity layer having a small parasitic resistance by using the same and irradiating the semiconductor substrate with the impurity source through the element separation film.

[Brief description of drawings]

FIG. 1 is a process sectional view showing a method for forming a MOS transistor according to a first embodiment of the present invention.

FIG. 2 is a process sectional view showing a method for forming a MOS transistor according to a second embodiment of the present invention.

FIG. 3 shows BBr on a silicon substrate having an oxide film formed on its surface.
_The figure which shows the concentration distribution of B and Br when ₃ is plasma-doped.

FIG. 4 shows BBr on a silicon substrate having an oxide film formed on the surface.
_3, characteristic diagram showing the relationship between the substrate surface density and the oxide film thickness of each element in the case of a BCl ₃ and plasma doping

[FIG. 5] Abraded amount (Si abraded amount) of the silicon substrate surface and S
Characteristic diagram showing the relationship with the film thickness (oxide film thickness) of the iO ₂ film

FIG. 6 is a B concentration of 10 ¹⁷ cm ^{−3 with} BBr ₃ and B ₂ H _6.
6 is a characteristic diagram showing the relationship between the acceleration voltage of each impurity source and the depth of the impurity layer when the B impurity layer of FIG.

[Explanation of symbols]

 11 ... Silicon substrate 12 ... Field oxide film 13 ... Gate oxide film 13a ... Silicon oxide film (element isolation film) 14a ... First layer gate electrode 14b ... Second layer gate electrode 15 ... Gate upper insulating film 16 ... Shallow p Type source / drain layer 17 ... gate sidewall insulating film 18 ... p type source / drain layer 21 ... silicon substrate 22 ... field oxide film 23 ... gate oxide film 24a ... first layer gate electrode 24b ... second layer gate electrode 25 ... Gate upper insulating film 26 ... Silicon nitride film 26 (element isolation film) 27 ... Shallow p-type source / drain layer 28 ... Gate sidewall insulating film 29 ... P-type source / drain layer

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yoshiaki Kitaura No. 1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Incorporated Toshiba Research and Development Center

Claims (5)

[Claims] 1. A semiconductor comprising, as an impurity source, a substance consisting only of a first element having a mass higher than that of hydrogen and a second element having a mass higher than that of hydrogen and a mass lower than that of the first element. When an impurity layer is formed on the surface of the semiconductor substrate by irradiating the substrate without mass separation, an element separation film is formed on the semiconductor substrate before the irradiation, and the element separation film allows the semiconductor If the depth of the impurity layer of the first element formed on the surface of the substrate is the second
Of the irradiated element is separated into a first element and a second element such that the peak position of the concentration distribution of the first element is in the element separation film. A method for manufacturing a semiconductor device, comprising: 2. The semiconductor substrate is a silicon substrate, the impurity source is Cl or Br as the first element, and the second element
2. The method for manufacturing a semiconductor device according to claim 1, wherein the element B is BCl ₃ or BBr ₃ , and the element separation film is a silicon oxide film or a silicon nitride film. 3. The element separation film has a thickness of 1 nm or more and 10 n.
It is less than m, The manufacturing method of the semiconductor device of Claim 1 characterized by the above-mentioned. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the impurity source material is accelerated by plasma doping or ion shower doping to irradiate the semiconductor substrate. 5. The acceleration voltage of the impurity source material is 1.5K.
The method for manufacturing a semiconductor device according to claim 4, wherein the method is eV or less.