JP3866167B2 - Manufacturing method of MIS type semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a MIS (metal-insulating film-semiconductor) type semiconductor device, for example, a MOS type field effect transistor and a manufacturing method thereof. The MIS type semiconductor device according to the present invention is used for various semiconductor integrated circuits.
[0002]
[Prior art]
As the design rules of MIS semiconductor devices have been reduced, the hot carrier injection phenomenon has occurred due to the steepness of the electric field strength between the drain and the channel. Such deterioration of characteristics due to the reduction of the design rule (that is, the shortening of the channel) is generally called a short channel effect. As a method for suppressing such a short channel effect, a MIS field effect transistor having low concentration impurity regions (low concentration drain, LDD) 406 and 407 as shown in FIG. 4 has been developed.
[0003]
In this type of device, the LDDs 406 and 407 having a lower concentration than the source / drain are provided between the source 404 and the channel formation region, or between the drain 405 and the channel formation region. Occurrence could be suppressed.
In the LDD as shown in FIG. 4, first, after forming the gate electrode 401, doping is performed to form a low-concentration impurity region, and then a sidewall 402 is formed of a material such as silicon oxide, and this is used as a mask. A method of forming the source / drain by performing consistent doping was adopted.
[0004]
For this reason, there is no gate electrode on the LDD, and a phenomenon in which hot carriers are trapped in the gate insulating film on the LDD occurs due to further shortening of the channel. Such hot carriers, particularly hot electron traps, reverse the LDD conductivity type, avoiding short channel effects such as threshold fluctuations, increased subthreshold coefficients, and reduced punchthrough breakdown voltage. I can't.
[0005]
In order to solve such problems, an overlap LDD structure (GOLD) structure in which the LDD is covered with a gate electrode has been proposed. By adopting this structure, it is possible to avoid deterioration of characteristics due to trapping of hot carriers in the gate insulating film on the LDD as described above. However, it was not easy to produce GOLD.
An MIS type field effect transistor having a GOLD structure that has been reported so far includes an IT-LDD structure (TY Huang: IEDM Tech. Digest 742 (1986)). An outline of the manufacturing method is shown in FIG.
[0006]
First, a field insulator 302 and a gate insulating film 303 are formed on a semiconductor substrate 301, and then a conductive film 304 such as polycrystalline silicon is formed. (FIG. 3A) Then, the conductive film 304 is appropriately etched to form the gate electrode 306. At this time, it should be noted that the conductive film 304 is not completely etched, but a thin conductive film 307 is left with an appropriate thickness (100 to 1000 mm). For this reason, this etching process is extremely difficult. (305 shown by a dotted line is an original conductive film.)
[0007]
In this manner, LDDs 308 and 309 are formed by through doping through the thin conductive film 307 and the gate insulating film 303. (Fig. 3 (B))
Thereafter, a film 310 is formed on the entire surface with a material such as silicon oxide. (Figure 3 (C))
Then, the sidewall 312 is formed by etching the coating 310 by an anisotropic etching method as in the case of manufacturing the conventional LDD structure. In this etching step, the thin conductive film 307 is also etched. Then, doping is performed in a self-aligning manner using the side wall formed in this manner as a mask to form a source 313 and a drain 314. (Fig. 3 (D))
[0008]
Thereafter, an interlayer insulator 315, a source electrode / wiring 316, and a drain electrode / wiring 317 are formed to complete the MIS field effect transistor. (Figure 3 (E))
As is apparent from the figure, the gate electrode portion is an inverted T-shape (Inverse-T), so it is called IT-LDD. Since a thin portion of the gate electrode exists on the LDD, the carrier density on the surface of the LDD can be controlled to some extent by the gate electrode. As a result, even if the impurity concentration of the LDD is made smaller, the mutual conductance is reduced due to the series resistance of the LDD, and the device characteristics are less likely to vary due to hot carriers injected into the insulating film on the LDD.
[0009]
These advantages are not unique to the IT-LDD structure, but are common to all GOLD structures. Since the LDD impurity concentration can be lowered, the electric field relaxation effect is great, and since the LDD can be shallow, the short channel effect and punch-through can be suppressed.
[0010]
[Problems to be solved by the invention]
However, as a GOLD manufacturing method, there is no effective method other than the IT-LDD structure, and although the IT-LDD structure has many advantages as described above, there is a problem that the manufacturing method is extremely difficult. In particular, it was extremely difficult to control the etching of the conductive film shown in FIG. If there is a variation in the thickness of the thin conductive film 307 between the substrates, the impurity concentration of the source / drain varies, so that the transistor characteristics vary. This invention is made | formed in view of such a problem, and makes it a subject to propose the GOLD structure obtained more simply.
[0011]
[Means for Solving the Problems]
In the present invention, the sidewall is made of a conductive material composed mainly of silicon (made of silicon having a purity of 95% or more), that is, the sidewall is made a part of the gate electrode, thereby forming the GOLD structure. obtain. In order to obtain such a structure, a conductive film made of a material containing silicon as a main component is formed to cover the central portion of the gate electrode, and then halogen fluoride, that is, the chemical formula XF _n (X is It is obtained by performing anisotropic or quasi-anisotropic etching in an atmosphere containing a substance (for example, ClF, ClF ₃ , BrF, BrF ₃ , IF, IF _3, etc.) represented by a halogen other than fluorine, where n is an integer. .
[0012]
In the present invention, the portion corresponding to the gate electrode (401 in FIG. 4) in the conventional LDD structure is the gate electrode, but it is called the central portion of the gate electrode in the sense that it is not all of the gate electrode. Further, in the present invention, the portion corresponding to the sidewall of the conventional LDD structure (402 in FIG. 4) is a part of the gate electrode made of a material mainly composed of silicon. In addition to the nominal name, it is also referred to as the side part of the gate electrode.
[0013]
The manufacturing method of the MIS type semiconductor device of the present invention includes:
(1) a step of forming a gate insulating film on the semiconductor surface, (2) a step of forming a central portion of the gate electrode, and (3) a low concentration impurity region in the semiconductor in a self-aligning manner using the central portion of the gate electrode as a mask. (LDD) forming step (4) forming a conductive film mainly composed of silicon (5) anisotropically or quasi-anisotropically etching the film in an atmosphere containing halogen fluoride to form a gate electrode (6) forming a source / drain in a self-aligning manner using the sidewall as a mask;
[0014]
As a result, the obtained MIS type semiconductor device is
(A) a central portion of the gate electrode formed on the gate insulating film;
A side portion of the gate electrode mainly composed of silicon formed in close contact with the side surface of the central portion of the gate electrode;
The semiconductor below the side of the gate electrode has a feature that it has a drain (or source) and a low concentration impurity region sandwiched between channel forming regions.
[0015]
Here, the central portion of the gate electrode is more preferably made of a material mainly composed of silicon (made of silicon having a purity of 95% or more). Also,
(B) An insulating film containing the same silicon oxide as a main component is formed on the drain, source, channel formation region, and low-concentration impurity region.
[0016]
[Action]
In the conventional LDD structure, it is not practical to simply configure the sidewall with a conductive film mainly composed of silicon. This is because etching when forming the sidewalls is difficult to stop at the gate insulating film containing silicon oxide as a main component, and the substrate may be greatly etched. This is because, in a normal dry etching process, the selectivity with respect to silicon oxide when etching silicon is not sufficiently large, and the thickness of the gate insulating film compared to the thickness of the gate electrode (= side wall). Is about 1/10.
[0017]
The present inventors' research has revealed that such problems can be solved by etching using halogen fluoride. That is, halogen fluoride has a strong action of etching silicon, but a weak action of etching a silicon oxide film.
In the present invention, in the etching for forming the sidewall, the etching selectivity between the sidewall material and the gate insulating film material can be sufficiently increased. As a result, overetching of the semiconductor substrate can only be avoided, or overetching of the gate insulating film is eliminated.
[0018]
However, in normal gas etching using gaseous halogen fluoride, isotropic etching was easy, but anisotropic or quasi-anisotropic etching was difficult. As a result of the examination under various conditions, the present inventor has found that the anisotropy of etching can be improved by using plasma excitation in a weak RIE (reactive ion etching) mode. . This is based on the characteristic that the plasma-damaged part is more easily etched by halogen fluoride, and the etching anisotropy is improved by irradiating plasma ions and electrons perpendicular to the substrate. Can be made. Typically, the vertical etching rate could be 2 to 10 times the horizontal etching rate.
[0019]
For the purpose of this etching, a gas that is advantageous for generating plasma such as argon may be mixed in the atmosphere. Furthermore, it is more preferable to provide a mechanism capable of accelerating / irradiating ions. However, it should be noted that if plasma excitation is excessive, the etching selectivity between silicon and silicon oxide is lowered.
The plasma action in the conventional dry etching is to generate active species such as fluorine ions, but the plasma action in the etching used in the present invention is only to activate the etching surface (make it easy to etch). In addition, the etching itself is characterized by halogen fluoride.
The present invention is characterized in that anisotropic etching is performed using halogen fluoride, and the detailed method of anisotropic etching may be other than the above-described method using plasma.
[0020]
【Example】
Example 1 FIG. 1 shows this example. First, a field insulator 102 having a thickness of 3000 μm to 1 μm was formed on a silicon substrate 101 by a known LOCOS forming method. Further, a silicon oxide film 103 having a thickness of 100 to 500 mm was formed as a gate insulating film by a thermal oxidation method. Further, a polycrystalline silicon film (thickness: 2000 to 5000 mm) whose conductivity was increased by doping phosphorus by a thermal CVD method was deposited, and this was etched to form the central portion 104 of the gate electrode. Then, phosphorus ions were implanted in a self-aligned manner using the central portion 104 of the gate electrode as a mask, and low-concentration N-type impurity regions (= LDD) 105 and 106 were formed. It was preferable that the LDD had a phosphorus concentration of 1 × 10 ¹⁶ to 1 × 10 ¹⁷ atoms / cm ³ and a depth of 300 to 1000 mm. (Fig. 1 (A))
[0021]
Then, a polycrystalline silicon film (thickness: 2000 μm to 1 μm) 107 in which conductivity was increased by doping phosphorus by a thermal CVD method was formed. (Fig. 1 (B))
Thereafter, anisotropic etching with ClF ₃ was performed. Etching was performed as follows. The substrate was placed in an etching chamber (same as that used in normal dry etching), and a mixed gas of argon and ClF ₃ was introduced into the chamber and RF discharge was performed. The flow rate of argon was 100 sccm, the flow rate of ClF3 was 50 sccm, and the pressure was 0.1 torr. A self-bias of −50 to −200 V was applied to the substrate. The etching almost stopped at the gate insulating film, and the following overetching was not observed.
[0022]
As a result, the polycrystalline silicon film 107 was etched (the dotted line 108 in the figure represents the original polycrystalline silicon film), and the side portion (side wall) 109 of the gate electrode was formed on the side surface of the central portion of the gate electrode. Under the conditions of this example, the etching rate in the vertical direction was quasi-anisotropic etching about twice that in the horizontal direction, so the shape of the side portion of the gate electrode was compared with the case of complete anisotropic etching. A little narrower. (Figure 1 (C))
[0023]
Thereafter, doping was performed in a self-aligned manner using the gate electrode as a mask by ion implantation of arsenic to produce the source 110 and the drain 111. The concentration of arsenic was 1 × 10 ^{19 to} 5 × 10 ²⁰ atoms / cm ³ . Then, the LDD and the source / drain were recrystallized by thermal annealing. (Figure 1 (D))
Thereafter, a silicon oxide film 112 having a thickness of 3000 μm to 1 μm was deposited as an interlayer insulator by a thermal CVD method. Then, a contact hole was formed in this, and a source electrode 113 and a drain electrode 114 were formed. In this way, a GOLD type transistor could be manufactured. (Figure 1 (E))
[0024]
Embodiment 2 FIG. 2 shows this embodiment. A field insulator 202 having a thickness of 3000 μm to 1 μm and a gate insulating film (silicon oxide) 203 having a thickness of 100 to 500 μm were formed on a silicon substrate 201 by a thermal oxidation method. Further, a central portion 204 of the gate electrode is formed by a polycrystalline silicon film (thickness: 2000 to 5000 mm) whose conductivity is increased by doping phosphorus, and phosphorus ions are implanted in a self-aligned manner using this as a mask. Low concentration N-type impurity regions (= LDD) 205 and 206 were formed. (Fig. 2 (A))
[0025]
Then, a polycrystalline silicon film (thickness: 2000 μm to 1 μm) 207 whose conductivity was increased by doping phosphorus by thermal CVD was formed. (Fig. 2 (B))
Thereafter, anisotropic etching with ClF ₃ was performed. Etching was performed as follows. The substrate 505 was placed on the cathode 504 of the etching chamber 501 having a structure as shown in FIG. Then, argon was introduced into the chamber, and plasma was generated between the anode 502 and the grid 503 by the RF power source 507. On the other hand, the potential between the cathode 504 and the grid 507 was maintained so that the anode was negative (−100 to −1000 V). As a result, argon ions were accelerated in the cathode direction through the grid and were incident substantially perpendicular to the substrate.
[0026]
On the other hand, ClF ₃ was jetted from the shower-like gas inlet 506 provided between the grid and the cathode toward the cathode. As a result, the substrate-like ion-damaged portion is selectively etched, so that the etching anisotropy can be increased to 10: 1 (2: 1 in Example 1) in this example. .
As a result, the polycrystalline silicon film 207 was etched (the dotted line 208 in the figure represents the original polycrystalline silicon film), and the side portion (side wall) 209 of the gate electrode was formed on the side surface of the central portion of the gate electrode. (Fig. 2 (C))
[0027]
Thereafter, arsenic ions were implanted in a self-aligned manner using the gate electrode as a mask to produce the source 210 and the drain 211, and the LDD and the source / drain were recrystallized by thermal annealing. (Fig. 2 (D))
Further, an interlayer insulator (silicon oxide having a thickness of 3000 μm to 1 μm) 212 was deposited, contact holes were formed therein, and a source electrode 213 and a drain electrode 214 were formed. In this way, a GOLD type transistor could be manufactured. (Figure 2 (E))
[0028]
【The invention's effect】
According to the present invention, a MIS type field effect transistor having a GOLD structure can be manufactured. The advantages of the GOLD type transistor are as described above, and they also apply to the present invention. It will be apparent that the production method of the present invention is suitable for mass production as compared with the method for obtaining the conventional IT-LDD structure shown in FIG.
[0029]
In the above embodiment, the method using plasma is shown as the method of anisotropic etching using halogen fluoride. However, in the present invention, other methods can be used as long as they are anisotropic or quasi-anisotropic etching. However, it is clear that the same effect can be obtained. Moreover, although only the example formed on a semiconductor substrate was described, it is needless to say that the same effect can be obtained even if the present invention is applied to a TFT formed on an insulating substrate. Thus, the present invention is an industrially useful invention.
[Brief description of the drawings]
FIG. 1 shows a manufacturing method of a GOLD type transistor according to Example 1;
2 shows a method for manufacturing a GOLD transistor according to Example 2. FIG.
FIG. 3 shows a method for manufacturing an IT-LDD transistor by a conventional method.
FIG. 4 shows a conventional LDD transistor.
5 shows an outline of an etching apparatus used in Example 2. FIG.
[Explanation of symbols]
101 Semiconductor substrate 102 Field insulator (silicon oxide)
103 Gate insulation film (silicon oxide)
104 Center of gate electrode (polycrystalline silicon)
105, 106 LDD
107 Polycrystalline silicon film 108 Position 109 where the polycrystalline silicon film was present Side wall (side of gate electrode) (polycrystalline silicon)
110, 111 Source / drain 112 Interlayer insulator (silicon oxide)
113, 114 Source / drain electrode

Claims (4)

On the gate insulating film made of silicon oxide formed on the semiconductor substrate , an island-shaped conductive film mainly composed of silicon is formed,
N-type impurity ions are implanted using the island-shaped conductive film as a mask to form an N-type impurity region in the semiconductor substrate,
Forming a conductive film mainly composed of silicon on the gate insulating film and in contact with the island-shaped conductive film ,
In an atmosphere containing argon and halogen fluoride, the conductive film formed on the gate insulating film and in contact with the island-shaped conductive film is anisotropically etched to form the island-shaped conductive film. Forming a sidewall made of a conductive coating, forming a gate electrode made of the island-shaped conductive coating and the sidewall;
N-type impurity ions are implanted using the gate electrode as a mask to form a source region, a drain region and an LDD region in the semiconductor substrate;
The LDD region is a method of manufacturing a MIS type semiconductor device that overlaps the sidewall through the gate insulating film,
In the anisotropic etching,
Using an etching chamber having an anode, a cathode, a grid between the anode and the cathode, and a shower-like gas inlet between the grid and the cathode,
The semiconductor substrate is placed on the cathode, the argon is introduced into the etching chamber, a plasma is generated between the anode and the grid, and the argon is substantially perpendicular to the semiconductor substrate through the grid. While making ions incident,
Etching is performed by injecting the halogen fluoride from the gas introduction port toward the cathode . According to claim 1, wherein the halogen fluoride _{ClF, ClF 3, BrF, BrF} 3, a method for manufacturing a MIS type semiconductor device, characterized in that an IF or IF _3. The method for manufacturing a MIS type semiconductor device according to claim 1 , wherein plasma is generated between the anode and the grid by an RF power source . 4. The thermal annealing process is performed according to claim 1 , wherein N-type impurity ions are implanted using the gate electrode as a mask to form a source region, a drain region, and an LDD region in the semiconductor substrate. A method for manufacturing a MIS type semiconductor device , wherein the source region, the drain region, and the LDD region are recrystallized .

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