JP2003133552A - Method of forming mis semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of easily forming a gate-overlapped LDD structure (GOLD) in which even the LDD is overlapped with a gate electrode. SOLUTION: A central part 104 of the gate electrode is formed on an insulating film 103, which is formed on a semiconductor substrate 101, and low concentration regions 105/106 are formed with a self-aligned manner. An electrically conductive coating film 107 is formed on the insulating film and on the central part of the gate electrode. The surface of the electrically conductive coating film is plasma-treated in an atmosphere containing argon, and the electrically conductive coating film is anisotropically etched in an atmosphere containing halogen fluoride. Gate-electrode side members 109 are formed on the sides of the central part of the gate electrode. Thereafter, a source and a drain are formed by ion implantation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MIS (metal-insulating film-semiconductor) type semiconductor device, for example, a MOS type field effect transistor and a method for manufacturing the same. The MIS type semiconductor device according to the present invention is used in various semiconductor integrated circuits.

[0002]

2. Description of the Related Art As the design rules of MIS type semiconductor devices have been reduced, hot carrier injection phenomenon has occurred due to the steepness of the electric field strength between the drain and channel. The deterioration of the characteristics due to the reduction of the design rule (that is, the shortening of the channel) is generally called the short channel effect. As a method for suppressing such a short channel effect, a MIS type field effect transistor having low concentration impurity regions (low concentration drain, LDD) 406 and 407 as shown in FIG. 4 has been developed.

In this type of device, the LDD 40 having a lower concentration than the source / drain is provided between the source 404 and the channel forming region or between the drain 405 and the channel forming region.
Since Nos. 6 and 407 are provided, the effect of relaxing the electric field is produced, and the generation of hot carriers can be suppressed.
In the LDD as shown in FIG. 4, first, a gate electrode 401 is formed, then doping is performed to form a low concentration impurity region, and then a sidewall 402 is formed of a material such as silicon oxide, which is used as a mask to perform self-deposition. A method of forming a source / drain by consistently doping was adopted.

Therefore, the gate electrode does not exist on the LDD, and due to the further shortening of the channel, hot carriers are trapped in the gate insulating film on the LDD. Then, due to the trapping of such hot carriers, especially hot electrons, the conductivity type of the LDD is reversed, and the short channel effect such as the fluctuation of the threshold value, the increase of the subthreshold coefficient, and the decrease of the punch-through breakdown voltage is avoided. I can no longer.

In order to solve such a problem, an overlapping LDD structure (GOLD) structure has been proposed in which the LDD is also covered with a gate electrode. By adopting this structure, it is possible to avoid the deterioration of characteristics due to the trapping of hot carriers in the gate insulating film on the LDD as described above. However, it was not easy to produce GOLD. GOLD reported so far
As a MIS type field effect transistor having a structure, IT-
LDD structure (TY Huang: IEDM Tec
h. Digest 742 (1986)). The outline of the manufacturing method is shown in FIG.

First, a field insulator 302 and a gate insulating film 303 are formed on a semiconductor substrate 301, and then a conductive film 304 of polycrystalline silicon or the like is formed. (Fig. 3
(A) Then, the conductive film 304 is appropriately etched to form a gate electrode 306. At this time, it should be noted that the conductive film 304 is not completely etched, but the conductive film 304 is left to have an appropriate thickness (100 to 1000 Å) and is left as a thin conductive film 307. Therefore, this etching process is extremely difficult. (305 indicated by a dotted line is the original conductive film.)

In this way, LDDs 308 and 309 are formed by through doping through the thin conductive film 307 and the gate insulating film 303. (FIG. 3B) After that, a coating film 310 is formed on the entire surface with a material such as silicon oxide. (FIG. 3C) Then, the sidewalls 312 are formed by etching the film 310 by an anisotropic etching method as in the case of forming a conventional LDD structure. In this etching process, the thin conductive film 307 is also etched.
Then, using the sidewalls thus formed as a mask, doping is performed in a self-aligned manner to form a source 313 and a drain 314. (Fig. 3 (D))

After that, the interlayer insulator 315, the source electrode,
The wiring 316 and the drain electrode / wiring 317 are formed to form MI.
The S-type field effect transistor is completed. (FIG. 3 (E)) As is clear from the figure, the gate electrode portion has an inverted T-shape (I
It is referred to as IT-LDD. Since the thin portion of the gate electrode exists on the LDD, the carrier density on the LDD surface can be controlled to some extent by the gate electrode. As a result, even if the impurity concentration of the LDD is made smaller, mutual conductance is reduced by the series resistance of the LDD, and device characteristics are less likely to be changed by hot carriers injected into the insulating film on the LDD.

These advantages are not unique to the IT-LDD structure but are common to all GOLD structures. Since the impurity concentration of LDD can be lowered, the electric field relaxation effect is large, and since the LDD can be made shallow, the short channel effect and punch through can be suppressed.

[0010]

[PROBLEMS TO BE SOLVED BY THE INVENTION]
As a method for producing D, there is no effective method other than the IT-LDD structure, and although the IT-LDD structure has many advantages as described above, there is a problem that the production method is extremely difficult. In particular, it was extremely difficult to control the etching of the conductive film shown in FIG. If there is variation in the thickness of the thin conductive film 307 between the substrates or within the substrate, the impurity concentration of the source / drain fluctuates, and thus the characteristics of the transistor vary. The present invention has been made in view of such problems, and an object thereof is to propose a GOLD structure that can be obtained more easily.

[0011]

In the present invention, the sidewall is
The main component is silicon (purity of 95% or more
It is made of a conductive material, i.e.
By using the sidewall as a part of the gate electrode,
To obtain a GOLD structure. To get such a structure
A conductive coating made of a material whose main component is silicon.
After forming a film covering the central part of the gate electrode,
Halogen fluoride, ie chemical formula XF_n (X is fluorine
Other than halogen, n is an integer) (for example,
ClF, ClF₃, BrF, BrF₃, IF, IF₃etc)
Perform anisotropic or quasi-anisotropic etching in an atmosphere containing
Get by breaking.

In the present invention, the portion corresponding to the gate electrode (401 in FIG. 4) in the conventional LDD structure is the gate electrode, but it is called the central portion of the gate electrode in the sense that it is not all of the gate electrode. Also, conventional LDD
The part corresponding to the side wall of the structure (402 in FIG. 4)
In the present invention, since a part of the gate electrode is a conductive material composed of a material containing silicon as a main component, it will be referred to as a side portion of the gate electrode in addition to the name of the sidewall.

A method of manufacturing a MIS type semiconductor device according to the present invention comprises (1) a step of forming a gate insulating film on a semiconductor surface, (2) a step of forming a central portion of a gate electrode, and (3) a central portion of the gate electrode. Of forming a low-concentration impurity region (LDD) in a semiconductor in a self-aligned manner using the mask as a mask (4) Forming a conductive film containing silicon as a main component (5) Atmosphere containing halogen fluoride in the film Anisotropically or quasi-anisotropically etch to form a sidewall containing silicon as a main component on the side surface of the central portion of the gate electrode (6) Self-aligned source / drain formation using the sidewall as a mask There is a step to do.

As a result, the MIS type semiconductor device obtained is (A) a silicon formed in close contact with the central part of the gate electrode formed on the gate insulating film and the side surface of the central part of the gate electrode. A side portion of the gate electrode mainly composed of
The semiconductor below the side of the gate electrode is characterized by having a low-concentration impurity region sandwiched between a drain (or source) and a channel formation region.

It is more preferable that the central portion of the gate electrode is made of a material containing silicon as its main component (made of silicon having a purity of 95% or more). Another feature is that the same insulating film containing silicon oxide as a main component is formed on the drain (B), the source, the channel formation region, and the low-concentration impurity region (B).

[0016]

In the conventional LDD structure, it is not practical to simply form the side wall with a conductive film containing silicon as a main component. This is because it is difficult to stop the etching at the time of forming the sidewalls with the gate insulating film containing silicon oxide as a main component, and there is a possibility that the substrate may be largely etched. This is because in the normal dry etching process, the selection ratio with respect to silicon oxide when etching silicon is not sufficiently large, and the thickness of the gate insulating film is larger than the thickness of the gate electrode (= sidewall). Is because it was as small as about 1/10.

The research conducted by the present inventor has revealed that such a problem can be solved by etching using halogen fluoride. That is, halogen fluoride has a strong effect of etching silicon, but has a weak effect of etching a silicon oxide film. According to the present invention, it is possible to sufficiently increase the etching selection ratio between the sidewall material and the gate insulating film material in the etching for forming the sidewall. As a result, not only overetching of the semiconductor substrate can be avoided, but also overetching of the gate insulating film is eliminated.

However, in normal gas etching using gaseous halogen fluoride, isotropic etching was easy, but anisotropic or quasi-anisotropic etching was difficult. The inventors of the present invention have conducted an examination under various conditions and found that it is possible to improve the anisotropy of etching by using plasma excitation in a weak RIE (reactive ion etching) mode together. . This is based on the characteristic that the portion damaged by plasma is more easily etched by halogen fluoride, and the anisotropy of etching is improved by vertically irradiating the substrate with ions and electrons from plasma. Can be made. Typically, the vertical etch rate is between 2 and 10 times the horizontal etch rate.
Could be doubled.

For the purpose of this etching, it is preferable to mix a gas such as argon, which is advantageous for generating plasma, into the atmosphere. Furthermore, it is more preferable to provide a mechanism capable of accelerating / irradiating ions. However, it should be noted that excessive plasma excitation lowers the etching selectivity between silicon and silicon oxide. The function of plasma in the conventional dry etching is to generate active species such as fluorine ions, but the function of plasma in the etching used in the present invention is to activate the etching surface (make it easy to etch).
Therefore, there is a feature that halogen fluoride is responsible for etching itself. The present invention is characterized by performing anisotropic etching using halogen fluoride, and the detailed method of anisotropic etching may be other than the above-mentioned method using plasma.

[0020]

[Embodiment] [Embodiment 1] FIG. 1 shows the present embodiment. First, a field insulator 1 having a thickness of 3000Å to 1 μm is formed on a silicon substrate 101 by a known LOCOS forming method.
02 was formed. Moreover, as a gate insulating film, a thickness of 10
A silicon oxide film 103 of 0 to 500 Å was formed by a thermal oxidation method. Furthermore, a polycrystalline silicon film (thicknesses 2000 to 5 having a conductivity increased by doping phosphorus by a thermal CVD method) is used.
000Å) was deposited, and this was etched to form the central portion 104 of the gate electrode. Then, phosphorus is ion-implanted in a self-aligning manner by using the central portion 104 of the gate electrode as a mask, and a low concentration N-type impurity region (= LDD) 10 is formed.
5, 106 were formed. The concentration of phosphorus in LDD is 1 × 10 ^16.
~ 1 × 10 ¹⁷ atoms / cm ³ , depth is 300 ~ 1000Å
I liked it. (Fig. 1 (A))

Then, a polycrystalline silicon film (thickness: 2000), which is doped with phosphorus by the thermal CVD method to increase the conductivity,
(1 to 1 μm) 107 was formed into a film. (FIG. 1 (B)) After that, anisotropic etching with ClF ₃ was performed. Etching was performed as follows. Place the substrate in the etching chamber (the same one used for normal dry etching), and place argon and ClF ₃ in the chamber.
The mixed gas of was introduced and RF discharge was performed. The flow rate of argon was 100 sccm, the flow rate of ClF3 was 50 sccm, and the pressure was 0.1 torr. -50 to-
A self-bias of 200 V was applied. The etching almost stopped at the gate insulating film, and the following overetching was not observed.

As a result, the polycrystalline silicon film 107 is etched (the dotted line 108 in the figure shows the original polycrystalline silicon film), and the side portion (sidewall) 109 of the gate electrode is formed on the side surface of the central portion of the gate electrode. Was done. Under the conditions of this embodiment, since the etching rate in the vertical direction was about twice as high as the quasi-anisotropic etching in the horizontal direction, the shape of the side portion of the gate electrode was larger than that in the case of completely anisotropic etching. , The width became narrower. (Fig. 1 (C))

After that, arsenic ion implantation was carried out in a self-aligning manner using the gate electrode as a mask to form a source 110 and a drain 111. The concentration of arsenic was set to 1 × 10 ^{19 to} 5 × 10 ²⁰ atoms / cm ³ . Then, the LDD and the source / drain were recrystallized by thermal annealing. (FIG. 1D) After that, a silicon oxide film 112 having a thickness of 3000 Å to 1 μm was deposited as an interlayer insulator by a thermal CVD method. Then, a contact hole is formed in this, and the source electrode 1
13 and the drain electrode 114 were formed. In this way, a GOLD type transistor could be manufactured.
(Fig. 1 (E))

[Embodiment 2] FIG. 2 shows the present embodiment. A field insulator 202 having a thickness of 3000 Å to 1 μm and a gate insulating film (silicon oxide) 203 having a thickness of 100 to 500 Å are formed on a silicon substrate 201 by a thermal oxidation method. Further, a central portion 204 of the gate electrode is formed of a polycrystalline silicon film (thickness 2000 to 5000 Å) which is doped with phosphorus and has an increased conductivity, and phosphorus is ion-implanted in a self-aligned manner using this as a mask. Low concentration N-type impurity regions (= LDD) 205 and 206 were formed. (Fig. 2
(A))

Then, a polycrystalline silicon film (thickness: 2000), which is doped with phosphorus by the thermal CVD method to increase the conductivity,
Å-1 μm) 207 was deposited. (FIG. 2 (B)) After that, anisotropic etching with ClF ₃ was performed. Etching was performed as follows. Board 505
The etching chamber 501 having the structure shown in FIG.
On the cathode 504. Then, argon was introduced into the chamber, and the RF power supply 507 generated plasma between the anode 502 and the grid 503. On the other hand, the potential between the cathode 504 and the grid 507 was maintained so that the anode was negative (-100 to -1000V). As a result, argon ions were accelerated toward the cathode through the grid, and were made to enter the substrate almost perpendicularly.

On the other hand, ClF ₃ was injected toward the cathode from a shower-like gas introduction port 506 provided between the grid and the cathode. As a result, the portion of the substrate that has received ion damage is selectively etched,
In this example, the etching anisotropy was set to 10: 1 (Example 1).
Then I was able to raise it to 2: 1). As a result, the polycrystalline silicon film 207 is etched (see the dotted line 20 in the figure).
8 indicates the original polycrystalline silicon film), and the side portion (sidewall) 209 of the gate electrode is formed on the side surface of the central portion of the gate electrode.
Was formed. (Fig. 2 (C))

After that, arsenic ion implantation was performed in a self-aligned manner using the gate electrode as a mask to form a source 210 and a drain 211, and thermal annealing was performed to recrystallize the LDD and the source / drain. . (FIG. 2D) Further, an interlayer insulator (thickness of 3000 Å to 1 μm of silicon oxide) 212 was deposited, a contact hole was formed therein, and a source electrode 213 and a drain electrode 214 were formed. In this way, a GOLD type transistor could be manufactured. (Fig. 2 (E))

[0028]

According to the present invention, a MIS having a GOLD structure is provided.
Type field effect transistor could be manufactured. GO
The advantages of the LD type transistor are as described above, and they are also applicable to the present invention. It will be clear that the fabrication method of the present invention is suitable for mass production, as compared with the conventional method of obtaining the IT-LDD structure shown in FIG.

In the above examples, the method using plasma was shown as the anisotropic etching method using halogen fluoride, but in the present invention, as long as anisotropic or quasi-anisotropic etching is performed, It will be apparent that the same effect can be obtained by other methods. Further, although only the example of forming on a semiconductor substrate has been described, it is needless to say that the same effect can be obtained by applying the present invention to a TFT formed on an insulating substrate in addition to this. Thus, the present invention is an industrially useful invention.

[Brief description of drawings]

FIG. 1 shows a method for manufacturing a GOLD type transistor according to a first embodiment.

FIG. 2 shows a method for manufacturing a GOLD type transistor according to a second embodiment.

FIG. 3 shows a method for manufacturing an IT-LDD type transistor by a conventional method.

FIG. 4 shows a transistor having an LDD structure according to a conventional method.

FIG. 5 shows an outline of an etching apparatus used in Example 2.

[Explanation of symbols]

101 Semiconductor Substrate 102 Field Insulator (Silicon Oxide) 103 Gate Insulating Film (Silicon Oxide) 104 Central Part of Gate Electrode (Polycrystalline Silicon) 105, 106 LDD 107 Polycrystalline Silicon Film 108 Position where Polycrystalline Silicon Film was Located 109 Side Wall (side of gate electrode)
(Polycrystalline silicon) 110,111 Source / drain 112 Interlayer insulator (silicon oxide) 113,114 Source / drain electrodes

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 29/49 F term (reference) 4M104 BB01 BB40 CC05 DD04 DD66 FF06 GG09 5F004 AA05 BA04 CA02 CA03 DA00 DA23 DB02 EA12 5F140 AA21 AA23 AA39 AA40 BA01 BE07 BF01 BF04 BF42 BG08 BG15 BG28 BG38 BG52 BG53 BG58 BH15 BH49 BK02 BK13 BK20 BK25 CB01 CC03 CC12

Claims (4)

[Claims] 1. A central part of a gate electrode is formed on an insulating film formed on a semiconductor substrate, a conductive film is formed on the insulating film and in the central part of the gate electrode, and the conductive film is formed in an atmosphere containing argon. Plasma-treating the surface of the conductive film, and anisotropically etching the conductive film in an atmosphere containing halogen fluoride to form a side portion of the gate electrode on a side surface of the central portion of the gate electrode. MI characterized by
A method for manufacturing an S-type semiconductor device. 2. A central portion of a gate electrode is formed on an insulating film formed on a semiconductor substrate, and a low concentration impurity region is formed on the semiconductor substrate using the central portion of the gate electrode as a mask. An electrically conductive coating is formed on the film and in the center of the gate electrode, and plasma treatment is performed on the surface of the electrically conductive coating in an atmosphere containing argon. Etching is performed to form a side portion of the gate electrode on a side surface of a central portion of the gate electrode, and using the central portion of the gate electrode and the side portion of the gate electrode as a mask, a source region and a drain region are formed on the semiconductor substrate. A method of manufacturing a MIS type semiconductor device, comprising: 3. The MIS type device according to claim 1, wherein the central portion of the gate electrode and the side portions of the gate electrode are made of a material containing silicon as a main component and have electrical conductivity. Manufacturing method of semiconductor device. 4. The method of manufacturing a MIS type semiconductor device according to claim 2, wherein a side portion of the gate electrode overlaps the low concentration impurity region.