JPH09219089A - Shift register - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily constitute it using a general purpose IC by alternately writing the data in an address outputted from an address specifying means based on a shift pulse and reading out the data from the address. SOLUTION: The address A1 outputted from a counter 21 and the address A2 outputted from a subtraction circuit 22 are inputted to a selection circuit 23 respectively. The address in read/write of a RAM 3 is specified by the address A1 or the address A2 selected in the circuit 23 by a shift pulse SP. Thus, the RAM 3 becomes a write-in state in the stage that the pulse SP exists, and the input data D1 are written in the address A1 selected in the circuit 23 by the pulse SP. In the stage that the pulse SP doesn't exist, the RAM 3 becomes a read-out state, and the data written in the address A2 selected in the circuit 23 by that she pulse SP doesn't exist are outputted as the output data DO read out from the RAM 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shift register which is used in various digital circuits and delays input data by a predetermined number of stages and outputs the delayed data.

[0002]

2. Description of the Related Art A shift register is a circuit for advancing input data to the next stage and outputting it every clock, and is constituted by connecting a predetermined number of flip-flops to several to ten stages according to the number of stages. . In this shift register, Hi
1-bit input data consisting of gh or Low is obtained, delayed by a predetermined number of stages, and output, and the circuit is integrated into an IC as an MSI (medium scale integrated circuit).

[0003]

However, in the conventional shift register, the flip-flops must be connected according to the number of stages, and there are problems that it is difficult to realize multiple stages and the bit width is small. Also, to take the output from any stage, you need to select the output of each stage,
When the number of stages is large, the selection circuit becomes complicated, and thus the number of stages and the number of bits are greatly limited.

For example, an arbitrary 1 with 100 stages and 8 bits width
When taking out the output from the stage, it is necessary to provide a 100: 1 selection circuit for inputting 100 × 8 = 800 signals. In addition, the shift register itself requires 800 signal terminals, which causes an increase in size and an increase in cost in order to realize an IC.

Further, since the conventional shift register is composed of flip-flops, an increase in the number of stages and an increase in the bit width directly affect the number of flip-flops, and the increase in these causes an increase in the gate scale. I am

[0006]

The present invention is a shift register made to solve the above problems. That is, the present invention is a shift register that delays input data by a predetermined number of stages and outputs, and outputs one address that is added based on a predetermined shift pulse and outputs this one address. An address designating means for outputting another address which is separated from the one address by a value corresponding to a predetermined number of steps based on the same shift pulse as the shift pulse to be generated, and one of the address designating means outputted from the address designating means based on the shift pulse. It is provided with a random access memory that alternately writes data to an address and reads data from another address.

In such a shift register, the target data is written to one address of the random access memory based on the shift pulse, and the other address separated by a value corresponding to a predetermined number of stages based on the shift pulse. Reading data from. That is, by setting a value corresponding to a predetermined number of stages in the address designating means, two addresses separated by that value are output alternately to the random access memory while shifting by one address for each shift pulse. become.

As a result, the data written at one address is output based on the shift pulse generated after the shift pulse at the time of writing by a value corresponding to the predetermined number of stages.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a shift register of the present invention will be described below with reference to the drawings. FIG.
It is a block diagram explaining embodiment of the shift register of this invention. That is, the shift register 1 in the present embodiment
Is for delaying input data (DI) by a predetermined number of stages (L) and outputting it without using a flip-flop, and mainly includes an address specifying unit 2 and a random access memory (hereinafter referred to as RAM) 3. It consists of

The address designating section 2 receives a counter 21 that counts up an address based on a predetermined shift pulse (SP) and an address output from the counter 21 and a value (L) corresponding to the number of delay stages. And a subtraction circuit 22 for subtracting L from the address, and a selection circuit 23 for selecting the address output from the counter 21 and the subtraction value output from the subtraction circuit 22.

That is, in the shift register 1 according to the present embodiment, the input data (DI) is stored in the RAM 3 by designating an address from the address designating section 2 to the RAM 3, and the data is stored in a predetermined number of stages (L). Only after the shift pulse (SP) is output, it is read from the RAM 3 as output data (DO).

Next, a specific operation of the shift register 1 of this embodiment will be described. First, the counter 21 counts up the address by "1" at the rising edge of the shift pulse (SP). The address (A1) output from the counter 21 is input to one of the subtraction circuits 22.

A value (L) corresponding to the number of delay stages is input to the other of the subtraction circuit 22, and L is subtracted from the address (A1) output from the counter 21 to obtain the address (A2 = A
1-L) is output. The address (A1) output from the counter 21 and the address (A2) output from the subtraction circuit 22 are input to the selection circuit 23, respectively.

The selection circuit 23 receives the input address (A
1) and the address (A2) are selected by the shift pulse (SP) and output. That is, the shift pulse (S
While P) is present, the address (A1) output from the counter 21 is selected and output as the address (A) to the RAM 3, and while there is no shift pulse (SP), the subtraction circuit 22
The address (A2) output from is selected and output as the address (A) to the RAM3.

The RAM 3 writes the input data (DI) using the shift pulse (SP) as a read / write control signal,
The output data (DO) is read. That is, the shift pulse (SP) is input to the port (W) for reading and writing control of the RAM 3, the writing of the input data (DI) is completed at the falling edge, and the reading is performed when the shift pulse (SP) is lost. To do.

Further, the designation of the address in the reading and writing of the RAM 3 is performed by the shift pulse (SP) in the selection circuit 2.
Address (A1) or address (A
2). Therefore, when the shift pulse (SP) is present, the RAM 3 is in the write state, and the input data (DI) is written to the address (A1) selected by the selection circuit 23 by the shift pulse (SP). Further, when there is no shift pulse (SP), the RAM 3 is in a read state, and the shift pulse (S
Without P), the data written at the address (A2) selected by the selection circuit 23 is read from the RAM 3 and output as output data (DO).

In the shift register 1 of this embodiment, the input data (DI) is output as it is when writing data to the RAM 3, but the shift pulse (SP) is also sent to the output side. , It becomes possible to indicate whether the data is valid or invalid. Therefore,
In the circuit (not shown) using the output data (DO),
In response to this shift pulse (SP), the shift pulse (S
Data may be invalidated when P) is present and valid when there is no shift pulse (SP).

Further, in this shift register 1, the input data (DI) is transferred to the RA via the tristate buffer 4.
It is input to M3. This tri-state buffer 4
To the port (D) of the RAM3, the shift pulse (SP) is input to the port (D) of the RAM3, and the shift pulse (SP) is enabled. When SP is not present (reading state of RAM3), it is disabled and the output data (DO) is read out from the port (D) of RAM3.

Next, the operation will be described based on the timing chart shown in FIG. Note that reference numerals not shown in FIG. 2 refer to FIG. First, when the shift pulse (SP) is input together with the input data (DI), the counter 21 is incremented by "1" and the counter 21
The address A1 output from is from "x" to "x + 1".

At this time, the subtraction circuit 22 operates and "x + 1-L" is output to its output A2, but the selection circuit 23 has the address (A1 =
x + 1) is selected, and the address (A1) is designated for the RAM3. The RAM 3 is in the writing state by receiving the shift pulse (SP),
Address output from the selection circuit 23 (A1 = x + 1)
Input data (DI) will be written to. This writing is completed when the shift pulse (SP) falls.

Next, at the same time as the shift pulse (SP) falls, the RAM 3 becomes in a read state. At this time, the selection circuit 23 outputs the address (A2 = x +) output from the subtraction circuit 22 because the shift pulse (SP) is lost.
1-L) and select the address (A2) for RAM3
Will be specified. RAM3 is a shift pulse (S
Since P) has disappeared, it is in a read state, and the address (A2 = x + 1−) output from the selection circuit 23.
The data of RAM3 is read from L) and output data (D
O) will be output.

By repeating this operation, the input data (D
I) is RA after the L-time shift pulse (SP) is generated.
It is read from M3 and output, and operates as an L-stage shift register.

FIG. 3 shows the RAM 3 in the case where the counter length is 3 bits (0 to 7 in order) and the designated value (L) of the number of delay stages is 3.
FIG. 6 is a schematic diagram illustrating the shift operation of FIG. That is, FIG.
At the stage shown in (a), R corresponding to the counter value "5"
Data is written to the address of AM3 and "5-
Data is read from the address of the RAM 3 corresponding to the counter value of "L = 5-3 = 2".

At the next stage shown in FIG. 3B, the counter value is incremented by "1" and RA corresponding to "6" is obtained.
Data is written to the address of M3, and "6-L
= 6-3 = 3 ", data is read from the address of the RAM 3 corresponding to the counter value.

Similarly, at the next stage shown in FIG. 3C, data is written to the address of the RAM 3 corresponding to the counter value "7" and RA corresponding to the counter value "4".
Data is read from the address of M3.

Then, at the next stage shown in FIG. 3D, data is written to the address of the RAM 3 corresponding to the counter value "0" and RA corresponding to the counter value "5".
Data is read from the address of M3.

That is, at the stage shown in FIG. 3 (d), which is three stages after the stage shown in FIG. 3 (a), the data input to the counter value “5” is read out, and according to the designated stage number L. The input data is delayed by the number of stages and output.

As described above, the shift register 1 in this embodiment is composed of the simple addressing section 2 and the RAM 3, so that even a very large-scaled one can be made compact. For example, when a shift register having an 8-bit width × 8 k stages is configured using a 16-pin general-purpose IC, four ICs are used as the counter 21, four ICs are used as the subtraction circuit 22, and four ICs are used as the selection circuit 23 in this embodiment. One IC is used for each of the ICs and the tri-state buffer 4, and a 28-pin I is used for the RAM3.
It suffices to use one C. Further, with this configuration, an arbitrary number of shift stages can be obtained.

In the shift register 1 according to this embodiment, the address designating section 2 may be built in the RAM 3 so that the size can be further reduced. Further, in the above-described embodiment, the single port type in which the data input / output is the same as the RAM 3
Separate dual port types may be used. Further, in the shift register 1 of the present embodiment, a large number of shift-out outputs can be obtained even with one shift register 1 by performing a time-division multiplexing process for specifying the number of shift stages (L) at a low shift speed. You will be able to get it.

[0030]

As described above, the shift register of the present invention has the following effects. That is, in the present invention, a general-purpose I
It becomes possible to easily construct by using C. Further, it is possible to easily set the bit width, the depth, and the arbitrary number of shift stages suitable for the applied system.

[Brief description of drawings]

FIG. 1 is a configuration diagram illustrating an embodiment of the present invention.

FIG. 2 is a timing chart of the shift register according to the present embodiment.

FIG. 3 is a schematic diagram illustrating a shift operation.

[Explanation of symbols]

1 shift register 2 address designation unit 3 RAM 4 tristate buffer 21 counter 22 subtraction circuit 23 selection circuit

Claims (3)

[Claims] 1. A shift register which delays input data by a predetermined number of stages and outputs the same, and outputs one address to be added based on a predetermined shift pulse and outputs the one address. Addressing means for outputting another address that is apart from the one address by a value corresponding to the predetermined number of steps based on the same shift pulse as the shift pulse, and output from the addressing means based on the shift pulse. A shift register comprising: a random access memory that alternately writes data to the one address and reads data from the other address. 2. The address designating means obtains a counter which adds the value by the shift pulse and outputs a value which becomes the one address, and a value which is outputted from the counter and becomes the one address, and outputs the value. A subtraction circuit that subtracts a value corresponding to the predetermined number of stages from the output to output a value that becomes the other address, the one address output from the counter, and the other address output from the subtraction circuit. 2. The shift register according to claim 1, further comprising: a selection circuit that selects a value based on the shift pulse and outputs the selected value as a specified address to the random access memory. 3. The random access memory inputs the data through a tri-state buffer in which enable and disenable are selected based on the shift pulse. Shift register.