JPH0921893A - Timer for measurement and count - Google Patents

Abstract

PROBLEM TO BE SOLVED: To measure a pulse width of an external signal by selecting measurement of a positive cycle or a negative cycle of an external signal pulse by control of an edge trigger controller. SOLUTION: A positive edge detecting circuit 20 and a negative edge detecting circuit 30 are composed of a flip-flop, a logic AND gate and a NO gate. A start register 40 is composed of another one RS latch circuit. In addition, a time base latch circuit 12 is a single D type latch circuit, and its input is connected to a single clock signal CLK and a single enable signal EN, and output is transmitted to a counter 13 by outputting a single counter clock signal Q. That is, a pulse width of an external signal EXT is obtained by control of an edge trigger controller 10. A count of the number of external signals is controlled by using a pulse detecting circuit 14, and counting is performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timer for measurement and counting, and more particularly to a timer capable of effectively measuring the time width of an external signal by selecting a signal.

[0002]

2. Description of the Related Art Referring to FIG. 1, the structure of a conventional timer includes a counter, a multiplexer and an edge trigger.
The controller 10 is composed of a multiplexer, and the multiplexer is a system clock SYS or an external signal E by switching the clock signal of the counter.
Select XT. The edge trigger controller 10 selects the trigger edge of the external signal, at which point the counter counts the internal number for the first time. In the above system, the operation method is divided into the following two types: (1) A method of selecting a system clock and dividing the frequency by a set frequency to obtain a fixed time length. Often used when measuring. (2) Select the signal / source at the time the external signal is input and use it to count the number of external signals.

However, as described above, the signal / source of the conventional timer is limited to the processing system clock and the number of external signals, and the target to be measured is not the number of trigger signals, but the time width of the external signal. If so, the system that has been used conventionally cannot be used. Therefore, conventional measurement and counting timers need some improvements in practice.

[0004]

It is an object of the present invention to overcome the drawbacks of previously used systems by utilizing the existing system structure previously used and selecting signals. More specifically, the pulse detection circuit controls the measurement of the number of external signals by selecting the measurement of the positive cycle or the negative cycle of the external signal pulse under the control of the edge trigger controller.

[0005]

[Means for Solving the Problems] The above-mentioned purpose is a counter,
It consists of a multiplexer, an edge trigger controller, a time base latch circuit, and a pulse detection circuit. The input of the multiplexer is the system clock,
The external signal transmitted to the multiplexer is the external trigger signal generated by inputting to the edge trigger controller, and the input of the pulse detection circuit is the sample signal and its external trigger signal, The enable signal at the output of the pulse detection circuit and the clock signal at the output of the multiplexer are both input to the time base latch circuit, and the output of the time base latch circuit is input to the counter before the required output. Is achieved by a timer for measuring and counting.

[0006]

BRIEF DESCRIPTION OF THE DRAWINGS In order that the content, features and functions of the present invention may be better understood, a more detailed description is given below with reference to the accompanying drawings. First, referring to FIG. 3, a digital logic circuit diagram of the multiplexer is shown. A set of selector signals is M1 and M0 , where M1 = 0, M0 = 1
, The clock signal CLK becomes the system clock SYS, which is in timer mode. M1
= 1 and M0 = 0, the clock signal CLK becomes the external signal EXT, which is the counter mode. When M1 = 1 and M0 = 1, the clock / signal CLK is a logical AND of the system clock SYS and the external signal EXT. Because the clock signal CLK is the external signal EXT = 1
The system clock SYS is output only when, and when the external signal EXT = 0, the system clock SYS is output.
This is because S is not output. M1 = 0 and M0 = 0 are inhibits, that is, such combinations of inputs should be avoided. The truth table is as follows: M1 = 0, M0 = 1, CLK = SYS timer mode M1 = 1, M0 = 0, CLK = EXT counter mode M1 = 1, M0 = 1, CLK = SYS AND EXT pulse width Mode M1 = 0, M0 = 0, CLK Inhibit Referring now to FIG. 6, it is a time sequence by the multiplexer of the present invention, the external signal E
By controlling whether or not to invert XT, it is possible to select which of the HIGH / LOW pulse of the signal to be measured is to be measured. For the purpose, edge D2 in FIG.
Change to the trigger controller 10 (see FIG. 4). Moreover, control is performed by adding the control signal CTL, that is, when CTL = 1, EXT1 = EXT, when CTL = 0, EXT1 = EXT. For example, the clock signal CLK is a positive edge signal to the counter 13 connected thereafter. When trigger inversion is used, when the control signal CTL = 1,
The external signal EXT becomes a positive edge trigger for the counter 13. If control
When signal CTL = 0, external signal EX
T becomes a negative edge trigger (see Figure 6). Therefore, the digital logic circuit of the edge trigger controller of the present invention of FIG.
The gate.

FIG. 2 is a block diagram of the circuit of the present invention,
The difference from the conventional timer is that a pulse detection circuit 14 and a time base latch circuit 12 are added. Referring to FIG. 8, it is a diagram showing the operation of the digital logic circuit of the present invention. Among them, the input of the pulse detection circuit 14 is connected to the output of the edge trigger controller 10 and one sample signal SAMP, and the output (of the pulse detection circuit) is connected to one input of the time base latch circuit 12. doing. Referring to FIG. 9, the contents of the digital logic circuit of the pulse detection circuit 14 of the present invention including the positive edge detection circuit 20, the negative edge detection circuit 30, the start register 40, and one RS latch circuit are shown. It is a figure. The positive edge detection circuit 20 detects the positive edge signal of the external trigger signal EXT1. Sample / Signal SA
External trigger signal EXT using MP
When 1 is a positive edge, the time base latch circuit 12 is opened, and the negative edge detection circuit 3
0 detects the negative edge signal of the external trigger signal EXT1. Similarly, using the sample signal SAMP, when the external trigger signal EXT1 is a negative edge, the time base
The latch circuit 12 is closed. Start register 4
0 controls the start of measurement and AND. Its inputs are one start signal START and one stop signal S output by one negative edge detection circuit 30.
One ON / OFF signal ON / O composed of TOP
Transmit FF to RS / latch circuit. The RS / latch circuit locks the signal and outputs one enable signal EN, thereby controlling the time base latch circuit 12 to open or close. A comparative diagram of the time sequence for that is shown in FIG. Further, referring to FIG. 11, the pulse detection circuit 14 in the present invention
FIG. 6 is a diagram showing an operation of the digital logic circuit of FIG.
The positive edge detection circuit 20 and the negative edge detection circuit 30 include a D flip-flop and a logic AND.
It consists of a gate and a NOT gate. The start register 40 is composed of another RS / latch circuit. In addition, the time base latch circuit 12 is one D type latch circuit, the input of which is connected to one clock signal CLK and one enable signal EN, and the output is one counter clock signal Q. Is output to the counter 13. FIG. 7 shows the time base of the present invention.
3 is a digital logic circuit diagram of the latch circuit 12. FIG.

With the above arrangement, the present invention makes it possible to measure the pulse width of the external signal EXT. That is, the edge trigger controller 10
The pulse width of the external signal EXT can be obtained by controlling the. The pulse detection circuit 14 is used to control and count the number of external signals EXT. The two-type operating mode of the conventional timer can still be used.

The above description is only one example of utilizing the present invention, and the scope of the present invention cannot be limited thereby, and any changes or modifications within the scope of the claims of the present invention can be realized by the present invention. It falls within the scope of the claims.

[Brief description of drawings]

FIG. 1 is a diagram showing a conventional timer.

FIG. 2 is a circuit block diagram of the present invention.

FIG. 3 is a digital logic circuit diagram of the multiplexer of the present invention.

FIG. 4 is a digital logic circuit operation diagram of a multiplexer using the edge trigger controller of the present invention.

FIG. 5 is a digital logic circuit diagram of the edge trigger controller of the present invention.

FIG. 6 is a time chart of the multiplexer according to the present invention.
It is a comparison figure of a sequence.

FIG. 7 is a digital logic circuit diagram of the time base latch circuit of the present invention.

FIG. 8 is an operation diagram of the digital logic circuit of the present invention.

FIG. 9 is a digital logic circuit diagram of the pulse detection circuit of the present invention.

FIG. 10 is a comparison diagram of the time sequence of the pulse detection circuit of the present invention.

FIG. 11 is a digital logic circuit operation diagram of the pulse detection circuit of the present invention.

[Explanation of symbols]

10 Edge Trigger Controller 20 Positive Edge Detection Circuit 30 Negative Edge Detection Circuit 40 Start Register SYS System Clock EXT External Signal EXT1 External Trigger Signal SAMP Sample Signal CTL Control Signal CLK Clock Signal START Start・ Signal STOP Stop ・ Signal ON / OFF ON ・ OFF ・ Signal M1 , M0 Select ・ Signal EN Enable ・ Signal Q Count Clock ・ Signal

Claims (5)

[Claims] 1. A counter, a multiplexer, an edge trigger controller, a time base latch circuit, and a pulse detection circuit. The multiplexer input has a system clock and an external signal transmitted to the multiplexer. The external trigger signal generated by inputting to the edge trigger controller, the input of the pulse detection circuit is the sample signal and its external trigger signal, and the enable signal of the output of the pulse detection circuit. A clock for measurement and counting, in which both the clock signal of the output of the multiplexer and the output of the multiplexer are input to the time base latch circuit, and the output of the time base latch circuit is input to the counter to obtain the required output. 2. The pulse detection circuit comprises a positive edge detection circuit, a negative edge detection circuit, a start register, and an RS latch circuit, and the external trigger signal and its sample signal are positive edge detection. Input to the circuit and the negative edge detection circuit, then output and then transmitted to the RS latch circuit, the input of the start register is a start signal and a stop signal, the output is an on-off signal, The stop signal is connected to the output of the negative edge detection circuit and the on / off signal is connected to the RS latch circuit to generate the enable signal.
A timer for the described measurements and counts. 3. The measuring and counting timer according to claim 2, wherein the positive edge detecting circuit and the negative edge detecting circuit are composed of a D flip-flop, a logic AND gate and a NOT gate. 4. A timer for measurement and counting according to claim 2, wherein the start register comprises an RS latch circuit. 5. The timer according to claim 1, wherein the time base latch circuit comprises a D type latch circuit.