KR100280510B1 - Negative delay circuit - Google Patents

Abstract

The present invention relates to a sub-delay circuit, and a conventional sub-delay circuit has no means for bypassing the clock input signal to an output signal when the speed of the clock input signal is slow, so that a user selects a register according to the speed of the clock input signal. There was a problem to adjust. In view of the above problems, the present invention provides a plurality of unit delay units for delaying a clock input signal; A plurality of comparison units configured to compare outputs of adjacent unit delay units among the plurality of unit delay units and output a result of the comparison; A clock buffer unit for buffering and outputting an output signal of a specific unit delay unit applied through a plurality of switches operating according to outputs of the plurality of comparison units; A non-delay circuit including a selector which selects an output signal of the clock input signal or a clock buffer unit and outputs the output signal externally according to a selection signal, wherein whether the output of a specific unit delay unit is all low potential at the rising edge of the clock input signal If it is judged that all of the low potential is not the low frequency of the clock input signal is outputted by selecting the output of the clock buffer portion of the selection signal, and if all of the low potential, the frequency of the clock input signal is recognized as the slow selection signal It further includes a bypass detection unit for outputting by selecting the clock input signal can be easily applied to a system using any frequency, thereby improving the use efficiency.

Description

Negative delay circuit

The present invention relates to a sub delay circuit. In particular, the present invention is suitable for use in a system having a variable operating frequency by detecting a clock input signal at a low speed so that the clock input signal can be output as a clock output signal of the sub delay circuit. It relates to a sub delay circuit.

Generally, a negative delay circuit delays a clock input signal and outputs a clock output signal having the same phase as the clock input signal, and outputs the clock input signal as a clock output signal as it is according to the speed of the clock input signal. A register for deciding whether or not to be provided is described, and this conventional sub delay circuit will be described in detail with reference to the accompanying drawings.

FIG. 1 is a conventional negative delay circuit diagram, which shows a plurality of unit delay units DELAY1 to DELAYn for sequentially delaying and outputting a clock input signal CLK according to an input of a selection signal SEL; A plurality of flip-flops FF1 to FFn for latching and outputting the clock input signal CLK delayed through the unit delay units DELAY1 to DELAYn in synchronization with the clock input signal CLK; A plurality of comparators (COMP1 to COMPN) for comparing signals output from the positive output terminal Q and the sub output terminal QB of the adjacent flip flop among the plurality of flip flops FF1 to FFn and outputting the comparison result. Wow; A plurality of switches SW1 to SWn for selecting and outputting the output signals of the unit delay units DELAY1 to DELAYn according to the output signals of the comparators COMP1 to COMPN; A clock buffer unit 1 for buffering and outputting the clock input signal CLK delayed through a specific unit delay unit selected through the switches SW1 to SWn; A selection unit (2) for selecting and outputting a clock input signal (CLK) or a delayed clock input signal (CLK) buffered through the clock buffer unit (1) according to the selection signal (SEL); The output buffer unit 3 outputs the clock output signal NDC_CLK by buffering the clock input signal CLK or the delayed clock input signal CLK selected by the selection unit 2.

Hereinafter, the operation of the conventional sub delay circuit configured as described above will be described.

First, when the clock input signal CLK has a high speed, the select signal SEL, which is a register, is applied at a high potential to enable the unit delay unit DELAY1 for receiving and delaying the clock input signal CLK. At this time, each unit delay unit DELAY2 to DELAYn receives and delays the delayed clock input signal CLK through the unit delay unit located at the front end and outputs the delayed unit. The output of each unit delay unit DELAY1 to DELAYn having a different delay degree is output. The signals are input to flip-flops FF1 to FFn, respectively.

As described above, the plurality of flip-flops FF1 to FFn receiving the clock input signals CLK delayed to different data input terminals are operated in synchronization with the clock input signals CLK, respectively. The predetermined clock signal is output through the sub output terminal QB. Also, the plurality of comparison units COMP1 to COMPN compare the clock signals output through the sub output terminal QB of the adjacent flip flops among the flip flops FF1 to FFn and the clock signals output through the constant output terminal Q. If it is the same value, a high potential output signal is output. That is, when the delayed clock input signals CLK input to the adjacent flip-flops are opposite in phase to each other, the comparators COMP1 to COMPN output a high potential output signal, and the switches SW1 to SWn applied thereto. When the output signal of the comparators COMP1 to COMPNn has a high potential, the clock input signal CLK delayed through a specific unit delay unit DELAY1 to DELAYn is applied to the clock buffer unit 1, which selects the high potential. It is output as the clock output signal NDC_CLK through the selection unit 2 and the output buffer unit 3 which select the output signal of the clock buffer unit 1 according to the signal SEL. At this time, the clock output signal NDC_CLK is delayed in the same phase as the clock input signal CLK.

When the clock input signal CLK is faster than the set value as described above, the sub delay circuit outputs the delayed clock output signal NDC_CLK in the same phase as the clock input signal CLK, but the clock input signal CLK. Is slower than the set value, the select signal SEL, which is the register, is applied at a low potential to disable the unit delay unit DELAY1 and allow the selector 2 to select the clock input signal CLK. The input signal CLK is output as the clock output signal NDC_CLK without delay.

As described above, the conventional sub delay circuit must set an area in which the sub delay circuit can operate and apply a selection signal according to the information, so that the user must always know the operating frequency and the period of the clock input signal changes. There was a problem that the change of the selection signal should always be checked.

In view of the above problems, the present invention provides a sub delay circuit capable of detecting a frequency of a clock input signal in a sub delay circuit and selectively outputting a delayed clock input signal or a clock input signal according to the value. The purpose is.

1 is a conventional negative delay circuit diagram.

Figure 2 is a side delay circuit diagram of the present invention.

3 is an operational waveform diagram of FIG. 2;

*** Description of the symbols for the main parts of the drawings ***

1: Clock buffer section 2: Selection section

3: Output buffer section 4: Bypass detection section

The above object is a plurality of unit delay unit for delaying the clock input signal; A plurality of comparison units configured to compare outputs of adjacent unit delay units among the plurality of unit delay units and output a result of the comparison; A clock buffer unit for buffering and outputting an output signal of a specific unit delay unit applied through a plurality of switches operating according to outputs of the plurality of comparison units; A non-delay circuit including a selector which selects an output signal of the clock input signal or a clock buffer unit and outputs the output signal externally according to a selection signal, wherein whether the output of a specific unit delay unit is all low potential at the rising edge of the clock input signal If it is judged that all of the low potential is not the low frequency of the clock input signal is outputted by selecting the output of the clock buffer portion of the selection signal, and if all of the low potential, the frequency of the clock input signal is recognized as the slow selection signal It is achieved by further comprising a bypass detection unit for outputting by selecting the clock input signal, described in detail with reference to the accompanying drawings, the present invention as follows.

FIG. 2 is a side delay circuit diagram of the present invention. As shown in FIG. 1, the output signal of the unit delay unit DELAYn is detected in the conventional configuration shown in FIG. 1, the frequencies are compared, and the selection signal SEL according to the comparison result of the frequencies. ) Further includes a bypass detector (4) for outputting to the selector (2) so that the selector (2) selects and outputs the clock input signal (CLK) or the output signal of the clock buffer (1). do.

The bypass detection unit 4 includes a unit delay unit DELAYn + 1 for delaying the output signal of the unit delay unit DELAYn and a unit delay unit DELAYn for delaying the output signal of the unit delay unit DELAYn + 1. +2); Flip-flops FFn + 1 and FFn + 2 for latching and outputting the output signal of the unit delay unit DELAYn + 1 in synchronization with the clock input signal CLK and the inverted clock input signal CLK, respectively. Wow; Flip-flops (FFn + 3) and (FFn + 4) for latching and outputting the output signal of the unit delay unit DELAYn + 2 in synchronization with the clock input signal CLK and the inverted clock input signal CLK, respectively. Wow; An exclusive ogate (XOR1) for outputting an exclusive combination of clock signals outputted through the positive output terminal (Q) of the flip-flops (FFn + 1) and (FFn + 2); An exclusive o-gate (XOR2) for outputting an exclusive oar combination of the clock signals output through the positive output stages of the flip-flops (FFn + 3) and (FFn + 4); And an OR gate OR1 for outputting the selection signal SEL by combining the output signals of the exclusive OR gates XOR1 and XOR2.

Hereinafter, the operation of the sub delay circuit of the present invention configured as described above will be described.

Fig. 3 is an operation waveform diagram of the sub delay circuit of the present invention. In this case, when the frequency of the clock input signal CLK is converted from the fast state to the slow state, the clock input signal CLK is inputted. The clock input signal CLK delayed through the plurality of unit delay units DELAY1 to DELAYn in the fast section is delayed in the unit delay unit DELAYn + 1, and the delayed clock input signal CLK is again a unit delay unit ( Delayed output from DELAYn + 2), and flip-flops (FFn + 1) and (FFn +) for receiving and latching the clock input signal CLK and the signal inverted from the clock input signal CLK, respectively, and outputting them to the clock input terminal. 2) The output signal of 2) is combined and output from the exclusive OR gate XOR1, and a flip-flop which receives and latches a clock input signal CLK and a signal inverted from the clock input signal CLK at the clock input terminal, respectively. The output signals of FFn + 3) and (FFn + 4) are the exclusive or gates (XOR2). The sum is output, the output signals of the two exclusive Iowa gate (XOR1), (XOR2) is combined in Iowa gate (OR1) is output to the selection of the high potential signal (SEL). This is a section in which the output signals of the unit delay units DELAYn + 1 and DELAYn + 2, which delay the frequency of the clock input signal CLK, become low potential at the rising edge of the clock input signal CLK. Because there is no.

The selector 2 receiving the high potential selection signal SEL receives and buffers an output signal of each of the unit delay units DELAY1 to DELAYn applied through the switches SW1 to SWn to output the buffered clock buffer. The output of section 1 is selected and output.

In this state, the frequency of the clock input signal CLK is slowed down, so that the output signals of the unit delay units DELAYn + 1 and DELAYn + 2 are both low at the rising edge of the clock input signal CLK. When a period that becomes a potential occurs, the selection signal SEL, which is an output signal of the OR gate OR1, transitions to a low potential and is output, and the selection unit 1 that receives the low potential selection signal SEL is Select and output the clock input signal CLK.

Through this process, the user can apply a sub delay circuit to a system operating at a certain frequency without considering the speed of the clock input signal CLK, and can solve the inconvenience of setting a register as in the prior art. Will be.

As described above, the sub-delay circuit of the present invention has a bypass detection unit that determines whether the output of the unit delay unit is at low potential at the rising edge of the clock input signal, and delays the clock input according to the detection result. By outputting a signal or a clock input signal, there is an effect of improving the ease of use and an effect of easily applying a sub delay circuit to a system using a frequency of any condition.

Claims (2)

A plurality of unit delay units for delaying a clock input signal; A plurality of comparison units configured to compare outputs of adjacent unit delay units among the plurality of unit delay units and output a result of the comparison; A clock buffer unit for buffering and outputting an output signal of a specific unit delay unit applied through a plurality of switches operating according to outputs of the plurality of comparison units; A non-delay circuit including a selector which selects an output signal of the clock input signal or a clock buffer unit and outputs the output signal externally according to a selection signal, wherein whether the output of a specific unit delay unit is all low potential at the rising edge of the clock input signal If it is judged that all of the low potential is not the low frequency of the clock input signal is outputted by selecting the output of the clock buffer portion of the selection signal, and if all of the low potential, the frequency of the clock input signal is recognized as the slow selection signal And a bypass (BYPASS) detector for outputting a signal by selecting a clock input signal. 2. The display device of claim 1, wherein the bypass detector is further configured to delay a first unit delay unit delaying an output signal of a unit delay unit located at a last stage of the plurality of unit delay units and a second delay unit of an output signal of the first unit delay unit. A unit delay unit; First and second flip-flops for latching and outputting an output signal of the first unit delay unit in synchronization with a clock input signal and an inverted clock input signal, respectively; Third and fourth flip-flops that latch and output an output signal of the second unit delay unit in synchronization with a clock input signal and an inverted clock input signal, respectively; A first exclusive ogate for outputting an exclusive or combination of clock signals outputted through the positive output terminals of the first and second flip-flops; A second exclusive ogate for outputting an exclusive or combination of clock signals outputted through the positive output terminals of the third and fourth flip-flops; And an o-gate configured to output a selection signal by combining the output signals of the first and second exclusive o-gates.