JPH02263247A - Scan path controller - Google Patents

Abstract

PURPOSE:To attain a scanning action even in an enable state of a data fetch grant signal in a scan mode by preparing a load signal control circuit which controls the data load signal in the scan mode. CONSTITUTION:A shift signal control circuit 4 and a load signal control circuit 5 hold the system clock signals K1 and CK2 in a disable state and an enable state respectively and controls in a scan mode a 1st control signal 43, i.3., a data shift signal of an output register 3 and a 3rd control signal 51, i.e., a data load signal of the register 3 respectively. Thus it is possible to obtain a scan path controller which can perform a scan action even though a data fetch grant signal CK2 is kept in an enable state.

Description

DETAILED DESCRIPTION OF THE INVENTION FIELD OF INDUSTRIAL APPLICATION The present invention relates to a scan path control device included in a large-scale logic circuit and for diagnosing the logic circuit.

BACKGROUND OF THE INVENTION A block diagram of an example of a conventional scan path control device of this type is shown in FIG.

1 is a combinational circuit; 2 is the combinational circuit 1;
An n-bit transparent input register that holds input data to CK, which is a two-phase system clock.
I is input. 3 functions as a shift register in which the first input 31, which is the scan path input, is the input and the first output 32, which is the scan path output, is the output in the scan mode, and in normal operation, the second input from the combinational circuit is A two-phase system clock CK2 is input to an output register that functions as an n-bit transparent latch that holds an input 33 and outputs it as a second output 34.

The operation of the conventional scan path control device configured as described above will be explained.

In normal operation, the n-bit data taken into the input register 2 is output to the combinational circuit 1 at the timing of the system clock CKI, and the output register 3 is output from the second input 33 from the combinational circuit 1 at the timing of the system clock GK2. The receiver takes it and outputs it as a second output 34. In that case, the scan clock 42 is kept unchanged.

Next, the operation in scan mode will be explained. A timing diagram in scan mode is shown in FIG. In the scan mode, the output register 3 functions as a shift register, so it keeps the system clock CK1 enabled and the system clock CK2 disabled, and disables the second input 33. After disabling the second input 33, when the scan clock 42 is enabled, the output register 3 takes in data from the first input 31 and is shifted in synchronization with the rising edge of the scan clock 42.
Shift data is output from the first output 32.

Problems to be Solved by the Invention However, in the above configuration, when the system clock CK2, which is the capture permission signal for the second input three colors, is enabled in the scan mode, the first input 31 and the second input in the output register 3 are There is a collision with the input 33, data cannot be shifted, and the output register 3 is transferred from the first output 32 to the output register 3.
The problem is that it is not possible to output the contents of , and it is also not possible to set a value in the output register 3 from the first input 31.

SUMMARY OF THE INVENTION In view of the above, an object of the present invention is to provide a scan path control device that can perform a scan operation even when a data acquisition permission signal is in an enabled state.

Means for Solving the Problems The present invention provides a combinational circuit that inputs data and processes it, and a shift register that uses a scan path input as a first input and a scan path output as a first output in a scan mode. function, and during normal operation not in scan mode, the input from the combinational circuit is used as a second input,
It has an output register that functions as a transparent latch that holds it and then outputs it as a second output, a mode control signal that indicates whether it is in scan mode or normal operation, and a scan clock that is a shift clock in scan mode. a shift signal control circuit that outputs a data shift signal of the output register as a first control signal to the output register; and a mode control signal, a second control signal from the shift signal control circuit, and data acquisition during normal operation. The scan path control device is characterized by comprising a load signal control circuit that receives a permission signal as an input and outputs a third control signal, which is a data load signal of the output register, to the output register.

Operation The present invention has the above-described configuration, so that the system clock CKI
A circuit is provided that maintains the system clock CK2 in a disabled state and the system clock CK2 in an enabled state, and controls a first control signal that is a data shift signal of the output register and a third control signal that is a data load signal of the output register in the scan mode. By providing this, it is possible to perform a scan operation even when the data acquisition permission signal is in the enabled state.

Embodiment FIG. 1 is a block diagram of the apparatus of the present invention. In FIG. 1, 1 is a combinational circuit, and 2 is an n-bit transparent input register for holding input data to the combinational circuit 1, into which a two-phase system clock CK1, which is a data acquisition permission signal, is input.

3, in the scan mode, the first input 31 which is the scan path input is input, and the first input 31 which is the scan path output is input.
functions as a shift register with the output 32 of
During normal operation, the second input 33 from said combinational circuit 1
an output register that functions as an n-bit transparent latch that holds and outputs as a second output 34; A shift signal 4 inputs a mode control signal 41 indicating that the scan mode is in effect and a scan clock 42 which is a shift clock in the scan mode, and outputs a first control signal 43 which is a data shift signal for the output register 3. control circuit. 5 is a two-phase system clock C
This is a load signal control circuit which inputs K2, a mode control signal 41, and a second control signal 44 which is an output from the shift signal control circuit 4, and outputs a third control signal 51 which is a data load signal for the output register 3. .

FIG. 2 shows an example of a circuit realizing the shift signal control circuit 4. In FIG. In FIG. 2, 6 is an AND gate, 7 is an inverter, and 8 is a delay circuit that delays the mode control signal 41 by the scan clock 42.

FIG. 3 is an example of a circuit realizing the load signal control circuit 5. In FIG. In FIG. 3, 6 is an AND gate, 7 is an inverter, and 9. is Philip Flop.

The operation of the scan path control device of this embodiment configured as described above will be described below.

Input register 2 during normal operation without data shifting
Data is fetched using CKI, which is a data fetch permission signal, and its output is input to the combinational circuit 1. At that time, the first control signal 43 is disabled by the mode control signal 41 and the third control signal 51 is enabled. Therefore, the output register 3 receives and holds the second input 33 at the timing of the system clock CK2, and
Output from the second output 34.

Next, the operation in the scan mode in which data is shifted will be explained.

FIG. 4 shows a timing diagram in scan mode.

When the mode control signal 41 is enabled, the mode is switched to scan mode. As a result, shift signal control circuit 4
At this point, the first control signal 43 is enabled. However, if the system clock CKI is kept disabled and the system clock CK2 is kept enabled during the scan mode, a data collision occurs between the first input 31 and the second input 33. Therefore, this can be prevented by controlling the third control signal 51, which is the data load signal of the output register 3. In FIG. 2, when the scan mode is entered, the mode control signal 41 is delayed by the scan clock 42, and a second control signal 44 is generated in which only the first cycle of the first control signal 43 is enabled. Further, in FIG. 3, when the second control signal 44 is enabled, the third control signal 51 is disabled at the rising edge of the second control signal 44, the second input 33 is disabled, and the first input 3
Only 1 is valid. Further, at the falling edge of the mode control signal 41 indicating the end of the scan mode, the third control signal 5 is activated.
1 is enabled again. As a result, in the scan mode, the value of the output register 3 is output from the first output 32 in the timing sequence of the first control signal 43, and the data from the first input 31 is output from the first control signal 43. The data is taken in sequentially at the timing and the value is set in the output register 3.

As described above, according to this embodiment, the circuit that controls the third control signal 51 which is the data load signal of the output register 3;
By providing the load signal control circuit 5, a scan operation can be performed even when the data acquisition permission signal is enabled in the scan mode.

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, by providing a load signal control circuit that controls the third control signal that is the data load signal in the scan mode, the data capture permission signal of the output register is enabled. Scanning can be performed even if the input register's data acquisition permission signal is disabled, so even if a circuit that changes depending on the input register's data acquisition permission signal is connected to the output register, the scan can be performed without changing its state. The operation can be resumed after the scan mode in the same state as before the scan mode, which has a great practical effect.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a scan path control device according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing an example of a shift signal control circuit in the same embodiment, and FIG. FIG. 4 is a circuit diagram showing an example of a signal control circuit, FIG. 4 is a timing diagram explaining the operation of the same embodiment, FIG. 5 is a block diagram showing the structure of a conventional scan path control device, and FIG.
The figure is a timing diagram explaining this operation. 1...Combination circuit, 2...Input register, 3...
Output register, 4...Shift signal control circuit, 5...
Load signal control circuit, 31...first input, 32...
- First output, 33... Second input, 34... Second output, 41... Mode control signal, 42... Scan clock, 43... First control signal, 44 ... second control signal, 51 ... third control signal, 8 ... AND gate,
7... Inverter, 8... Delay circuit, 9... Philip

Claims (1)

[Claims] A combinational circuit that inputs data and processes it, functions as a shift register with the scan path input as the first input in scan mode and the scan path output as the first output, and in normal operation not in scan mode. an output register that functions as a transparent latch that takes the input from the combinational circuit as a second input, holds it and then outputs it as a second output; and a mode control signal that indicates whether it is in scan mode or normal operation. and a shift signal control circuit that receives a scan clock that is a shift clock in a scan mode and outputs a data shift signal of the output register as a first control signal to the output register, and the mode control signal and the shift signal control circuit. The present invention further includes a load signal control circuit that receives a second control signal from the circuit and a data acquisition permission signal during normal operation and outputs a third control signal, which is a data load signal of the output register, to the output register. Characteristic scan path control device.