JPH09214477A - Clock recovery device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce jitter produced when the synchronous residual time stamp (SRTS) method is replaced with the adaptive clock method in the clock recovery system in combination of the SRTS method and the adaptive clock method. SOLUTION: A clock of the SRTS method is recovered by an output of a 1st control voltage by synchronous time stamp residual information of an SRTS method control voltage generating section 2. A 2nd selector 21 selects an output close to a 1st control voltage of an intermediate voltage generating section 20 and smoothed and outputted by a filter 3. When an information amount of a buffer 1 reaches an upper limit 13 or over and when the adaptive clock method using a 2nd control voltage is selected, the 2nd selector 21 selects a used amount signal 12 from the buffer 1 is selected and outputted to the filter 3. The output of the filter 3 is changed from the output of the intermediate voltage generating section 20 into the signal 12, a voltage difference between the 1st control voltage and th 2nd control voltage is reduced. Voltage fluctuation caused at switching is reduced and jitter caused in a clock outputted from a voltage controlled oscillator 6 is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a case where a fixed speed information is transferred by using an ATM (asynchronous transfer mode) system, the frequency of a clock on the transmitting side is set to SR on the receiving side.
The present invention relates to a clock reproducing device for reproducing by a method in which a TS (Synchronous Residual Time Stamp) method and an adaptive clock method are combined.

[0002]

2. Description of the Related Art The SRTS method and the adaptive clock method are
-T Recommendation I. This is the clock reproduction method specified in 363. SRTS method, adaptive clock method, SRTS
A method combining the method and the adaptive clock method will be described.

First, the SRTS method is a method that can be used when a common clock can be referred to on the transmitting side and the receiving side for communication. On the transmission side, a common clock is measured at intervals of fixed speed information for every N bits, and only the part of the measured value that changes due to frequency fluctuations of the transmission clock is inserted into the cell as synchronization time stamp residual information. Send. The receiving side reproduces the interval of N-bit fixed speed information from the transmitted synchronous time stamp residual information and the common clock, and reproduces the clock of the transmitting side based on this interval.

The adaptive clock method is a method in which the fixed speed information stored in the cell received on the receiving side is stored in a buffer and the read clock of the buffer is controlled so that the amount of the stored information holds a reference value. Yes, this read clock becomes the reproduced clock of the transmitting side.

Comparing the SRTS method with the adaptive clock method, the SRTS method is superior in the jitter / wander characteristics of the reproduced clock. But SRT
The S method requires that the transmitting side and the receiving side can refer to a common clock.

Next, in the system combining the SRTS method and the adaptive clock method, even if the common clock cannot be referred to on the transmitting side and the receiving side, the SRTS method is used as much as possible to reproduce the jitter / wander of the recovered clock. This is a method to improve the characteristics. However, when the SRTS method is used when a common clock cannot be referred to, buffer overflow / underflow may occur. For this reason, the method combining the SRTS method and the adaptive clock method, depending on the amount of information stored in the buffer,
The SRTS method and the adaptive clock method are switched and used.

In the system in which the SRTS method and the adaptive clock method are combined, the clock is reproduced by the SRTS method after the amount of information stored in the buffer reaches a preset reference value. After that, when the amount of information stored in the buffer reaches a preset upper limit value or lower limit value, the clock is reproduced by the adaptive clock method, and the information amount in the buffer is returned to the reference value. After the amount of information in the buffer returns to the standard value, SRT is performed again
The clock is reproduced by the S method. Therefore, even if the common clock cannot be referenced on the communication side and the receiving side, buffer overflow / underflow does not occur,
Clock recovery by the SRTS method can be used.

FIG. 7 is a block diagram showing the configuration of a clock reproducing apparatus combining the conventional SRTS method and adaptive clock method. In FIG. 7, 1 is a buffer for storing the information stored in the received cell, 2 is the synchronous time stamp residual information stored in the received cell,
An SRTS method control voltage generating unit 3 for generating a first control voltage for reproducing a clock by the SRTS method smooths the usage amount signal output from the buffer 1 and reproduces a clock by the adaptive clock method. A filter 4 for generating a control voltage of 2 outputs a selection signal for switching the SRTS method and the adaptive clock method according to the amount of information stored in the buffer 1.
According to the selection signal from the clock regeneration method switching unit 4,
A first selector that selects either the first control voltage output from the SRTS method control voltage generator 2 or the second control voltage output from the filter 3, and 6 is a clock that outputs according to the input control voltage. It is a voltage controlled oscillator that can change the frequency of.

Further, 11 is a preset reference value indicating a threshold value serving as a reference for the amount of information stored in the buffer 1, 12 is a usage amount signal indicating that the information amount is 11 or more, and 13 is a buffer. 1 is a preset upper limit value indicating the upper limit of the amount of information stored, 14 is an upper limit signal indicating that the amount of information is 13 or more, 15 is a lower limit indicating the lower limit of the amount of information stored in the buffer 1 The set lower limit value, 16 is a lower limit signal indicating that the amount of information is less than or equal to the lower limit value 15, CLK is the clock reproduced by the voltage controlled oscillator 6, and the information stored in the buffer 1 by the input of the clock. Is a clock terminal to which is output.

FIG. 8 is a diagram showing the timing of each signal waveform for explaining the operation of the conventional clock recovery device. In FIG. 8, a is a waveform of the usage amount that changes depending on the amount of information stored in the buffer 1, b is a waveform of the first control voltage output from the SRTS method control voltage generation unit 2, and c is a usage amount of the buffer 1. The waveform of the signal 12, d is the waveform of the second control voltage output from the filter 3, and e is the waveform output from the first selector 5.

The operation of the clock reproducing apparatus of the system configured by combining the SRTS method and the adaptive clock method configured as described above will be described with reference to FIGS. SRT
In the method combining the S method and the adaptive clock method, after the amount of information stored in the buffer 1 exceeds the reference value 11
Clock reproduction is started by the TS method. In the state where the reference value is 11 or less (the period A shown in FIG. 8), even if the reproduced clock is input to the buffer 1, the information stored in the buffer 1 is not output.

Next, after the amount of information stored in the buffer 1 exceeds the reference value 11 (period B in FIG. 8), the SRTS
The operation while the clock is being reproduced by the method will be described. The received cell information is stored in the buffer 1 and also input to the SRTS method control voltage generator 2. SRT
The S method control voltage generation unit 2 generates and outputs a first control voltage for reproducing a clock by the SRTS method based on the synchronization time stamp residual information stored in the cell (see FIG. 8). Waveform b) shown.

Further, the filter 3 smoothes the usage amount signal 12 (waveform c shown in FIG. 8) from the buffer 1 and generates and outputs a second control voltage for reproducing the clock by the adaptive clock method. (Waveform d shown in FIG. 8). The clock recovery method switching unit 4 outputs a selection signal for selecting the output of the SRTS method control voltage generation unit 2. The first selector 5 selects the output of the SRTS method control voltage generator 2 according to the instruction of the selection signal (period B shown in FIG. 8) and inputs it to the voltage controlled oscillator 6. The voltage controlled oscillator 6 outputs a clock having a frequency corresponding to the voltage output from the first selector 5. As described above, while the clock based on the SRTS method is being reproduced, the clock is reproduced based on the output of the SRTS method control voltage generator 2.

Next, after the amount of information stored in the buffer 1 becomes a preset upper limit value 13 or more or a lower limit value 15 or less (the period C shown in FIG. 8; the upper limit value 13 or more in this conventional example). The operation will be described while the clock is being reproduced by the adaptive clock method. In this case, the clock recovery method switching unit 4 outputs a selection signal for selecting the second control voltage output by the filter 3 in order to recover the clock by the adaptive clock method. The first selector 5 selects the output of the filter 3 according to the instruction of the selection signal (period C in FIG. 8) and inputs it to the voltage controlled oscillator 6. The voltage controlled oscillator 6 outputs a clock having a frequency corresponding to the voltage output from the first selector 5. In the adaptive clock method, the amount of information stored in the buffer 1 is returned to the reference value 11, and after the amount of information stored in the buffer 1 is returned to the reference value 11, the clock is reproduced again by the SRTS method.

As described above, in the above-mentioned conventional example, by switching the SRTS method and the adaptive clock method based on the amount of information stored in the buffer 1, SR / underflow of the buffer does not occur and SR
Clock reproduction can be performed by a method that combines the TS method and the adaptive clock method.

[0016]

However, in the clock regenerator using the combination of the SRTS method and the adaptive clock method having such a configuration, the information stored in the buffer while the clock is being regenerated by the SRTS method. Since the amount is always larger (or smaller) than the reference value, the second control voltage output from the filter for reproducing the clock by the adaptive clock method reduces the amount of information stored in the buffer. High level to do
(Or low level to increase) is output.

For this reason, when the clock reproduction method is switched from the SRTS method to the adaptive clock method (position D in FIG. 8), the control voltage input to the voltage controlled oscillator changes greatly and is output from the voltage controlled oscillator. There is a problem that a large jitter is generated in the clock.

The present invention solves the above-mentioned problems of the prior art, and provides a clock recovery device that reduces the jitter generated in the recovered clock when the clock recovery method is switched from the SRTS method to the adaptive clock method. The purpose is to

[0019]

In order to achieve this object, a clock recovery device according to the present invention stores information stored in a received cell and the amount of the information is equal to or more than a preset threshold value. SRTS for generating a first control voltage for clock recovery by the SRTS method using a storage means for outputting a usage amount signal indicating that there is and a synchronous time stamp residual information indicating frequency information of a transmitting side clock.
Either a first control voltage or a second control voltage, a filter control voltage generating means, a filter means for smoothing an input signal and generating a second control voltage for reproducing the clock by the adaptive clock method. Selecting means for selecting the SR, and SR
Clock recovery method switching means for outputting a selection signal for switching the clock recovery method between the TS method and the adaptive clock method,
Voltage-controlled oscillation means for changing the frequency of the clock output according to the control voltage selected by the first selection means;
An intermediate voltage generating means for outputting a voltage close to the control voltage of
The second selection means is provided for selecting either the output of the intermediate voltage generation means or the usage amount signal and inputting it to the filter means.

Further, in the clock reproducing device of the present invention, the threshold value for changing the threshold value of the storing means is changed to the first control voltage and the second control voltage in place of the intermediate voltage generating means and the second selecting means. A control means is provided.

Further, in the clock regenerator of the present invention, the first control voltage is inputted instead of the output of the intermediate voltage generating means except the intermediate voltage generating means, and the filter means is selected by selecting the use amount signal. The second selection means for inputting to is configured.

According to the above construction, while the first control voltage is being selected by the first selecting means, the second selecting means selects the output of the intermediate voltage generating means and inputs the output to the filter means. The second control voltage is selected by the selecting means, the second selecting means selects the usage amount signal, and the second control voltage is the output value of the intermediate voltage generating means even if the second control voltage changes. Therefore, the voltage fluctuation that occurs when the first control voltage is switched to the second control voltage can be reduced.

Further, the threshold value control means controls the threshold value of the storage means so that the first control voltage and the second control voltage match, and when the first control voltage is switched to the second control voltage. The generated voltage fluctuation can be reduced.

In the second selecting means, the first control voltage is selected and input to the filter means, and the second control voltage is made equal to the first control voltage. If the second control voltage is selected and the second selection means selects the usage amount signal and the second control voltage changes, the second control voltage changes from the value of the first control voltage. First
The voltage fluctuation that occurs when the control voltage is switched to the second control voltage can be reduced.

[0025]

Embodiments of the present invention will be described below in detail with reference to the drawings. 1 is a block diagram showing a configuration of a clock recovery device according to a first embodiment of the present invention. In each of the following drawings, the same reference numerals are given to those having the same operational effects as the constituent elements that have appeared in the description of the conventional example with reference to FIG.

In FIG. 1, 1 is a buffer which is a storage means, 2 is an SRTS method control voltage generator which outputs a first control voltage, 3 is a filter which outputs a second control voltage, and 4 is a first later-mentioned. , A clock recovery method switching section for outputting a selection signal to a second selector, 5 is a first selector which is a first selecting means, 6 is a voltage controlled oscillator, and 20 is close to the output of the SRTS method control voltage generation section 2. The intermediate voltage generation unit 21 for outputting a voltage selects the usage signal from the buffer 1 or the output of the intermediate voltage generation unit 20, which is the second selection means, and outputs it to the filter 3. It is a selector. Further, 11 is a reference value, 12 is a usage amount signal, 13 is an upper limit value, 14 is an upper limit signal, 15 is a lower limit value, 16 is a lower limit signal, and CLK is a clock terminal.

FIG. 2 is a diagram showing the timing of each signal waveform for explaining the operation of the clock recovery device of the first embodiment. In FIG. 2, a is a waveform of the usage amount that changes depending on the amount of information stored in the buffer 1, b is a waveform of the first control voltage output from the SRTS method control voltage generation unit 2,
c is the waveform of the usage amount signal 12 of the buffer 1, d is the waveform output from the intermediate voltage generator 20, and e is the waveform output from the first selector 5.

The clock regenerating apparatus of the first embodiment having the above-mentioned configuration has the intermediate voltage generating section 20 and the second selector 21 in addition to the configuration of the conventional example. First, centering on the operations of the intermediate voltage generator 20 and the second selector 21, while the amount of information stored in the buffer 1 becomes the reference value 11 or more, the clock is reproduced by the SRTS method.
The operation of (period B shown in FIG. 2) will be described.

In the SRTS method control voltage generator 2, S is based on the synchronization time stamp residual information stored in the cell.
A first control voltage for reproducing a clock by the RTS method is generated and output (waveform b shown in FIG. 2). This first control voltage is selected by the first selector 5 and input to the voltage controlled oscillator 6 to regenerate the clock by the SRTS method. At this time, the second selector 21 selects the output (waveform d shown in FIG. 2) from the intermediate voltage generator 20 and inputs it to the filter 3. In the filter 3, the second selector 21
Output a second control voltage for smoothing the output of the clock signal and reproducing the clock by the adaptive clock method (B shown in FIG. 2).
Period).

The maximum amount of information stored in the buffer 1 is 13
Above (or below the lower limit value 15), the upper limit signal 14 (or lower limit signal 16) is output from the buffer 1. The clock reproduction method switching unit 4 receives the upper limit signal 14 (or the lower limit signal 16) and outputs a selection signal to the first selector 5. The selection signal switches the SRTS method to the adaptive clock method, and the first selector 5 selects the second control voltage from the first control voltage. After switching to the adaptive clock method (Fig. 2
2), the second selector 21 selects the usage signal 12 (waveform c shown in FIG. 2) from the buffer 1 and outputs it to the filter 3.

From the above, when the amount of information stored in the buffer 1 reaches the upper limit value 13 or more (or the lower limit value 15 or less), the first selector 5 switches to the adaptive clock method.
Even if the input of the filter 3 is switched to (position D in FIG. 2), its output changes from the output value of the intermediate voltage generation unit 20 to the value of the usage amount signal 12, so the clock is reproduced by the SRTS method. Therefore, the voltage difference between the first control voltage and the second control voltage for reproducing the clock by the adaptive clock method can be reduced. Therefore, the voltage fluctuation caused when switching from the SRTS method to the adaptive clock method is reduced, and the amount of jitter generated in the clock output from the voltage controlled oscillator 6 can be reduced.

FIG. 3 is a block diagram showing the configuration of the clock recovery device according to the second embodiment of the present invention. In FIG. 3, 1 is a buffer, 2 is a SRTS method control voltage generator,
3 is a filter, 4 is a clock regeneration method switching unit, 5 is a first selector, 6 is a voltage controlled oscillator, 22 is a first for reproducing a clock by the SRTS method output from the SRTS method control voltage generation unit 2. A threshold control unit that compares the control voltage with a second control voltage that reproduces a clock by the adaptive clock method output from the filter 3 and changes the reference value 11 set in the buffer 1 so that both control voltages match. . Further, 11 is a reference value, 12 is a usage amount signal, 13 is an upper limit value, 14 is an upper limit signal, 15 is a lower limit value, 16 is a lower limit signal, and CLK is a clock terminal.

FIG. 4 is a diagram showing the timing of each signal waveform in order to explain the operation of the clock recovery device of the second embodiment. In FIG. 4, a is a waveform of the usage amount that changes depending on the amount of information stored in the buffer 1, b is a waveform of the first control voltage output from the SRTS method control voltage generation unit 2, and c
Is a waveform of the usage amount signal 12 of the buffer 1, d is a waveform of the second control voltage output from the filter 3, and e is a waveform output from the first selector 5.

The clock regenerating device of the second embodiment having the above-mentioned configuration has the same structure as the conventional example, but the threshold control unit 22 is provided.
Is provided. Buffer 1, SRTS method control voltage generator 2, filter 3, clock recovery method switching unit 4, first
Since the operations of the selector 5 and the voltage-controlled oscillator 6 of FIG. , SRTS method while the clock is being reproduced (B period shown in FIG. 4) will be described.

The SRTS method control voltage generator 2 determines the SR based on the synchronization time stamp residual information stored in the cell.
A first control voltage for reproducing the clock by the TS method is generated and output (waveform b shown in FIG. 4). The filter 3 smoothes the usage amount signal 12 (waveform c shown in FIG. 4) output from the buffer 1 to generate and output a second control voltage for reproducing the clock by the adaptive clock method. (Waveform d shown in FIG. 4). At this time, the threshold control unit 22
Compares the first control voltage with the second control voltage, changes the reference value 11 of the threshold value set in the buffer 1, and controls so that the control voltages match.

Further, after the amount of information stored in the buffer 1 becomes a preset upper limit value 13 or more (or a lower limit value 15 or less) and after switching to the adaptive clock method (period C in FIG. 4), the threshold value is set. In the control unit 22, the reference value 11 given to the buffer 1
To the initial value.

From the above, when the amount of information stored in the buffer 1 exceeds the upper limit value 13 (or lower limit value 15), the first selector 5 switches to the adaptive clock method.
Since the threshold value control unit 22 changes the reference value 11 of the buffer 1 to (the position of D shown in FIG. 4) so that the control voltages of the first control voltage and the second control voltage match. , SRTS
There is almost no voltage fluctuation that occurs when the method is switched to the adaptive clock method (waveform e shown in FIG. 4), and the amount of jitter that occurs in the clock output from the voltage controlled oscillator 6 can be greatly reduced.

FIG. 5 is a block diagram showing the structure of the clock reproducing apparatus according to the third embodiment of the present invention. here,
The same reference numerals are given to those having the same operation and effect described in FIG. 1 of the first embodiment. In FIG. 5, 1 is a buffer,
Reference numeral 2 is an SRTS method control voltage generation unit, 3 is a filter, 4 is a clock recovery method switching unit, 5 is a first selector, 6 is a voltage controlled oscillator, and 21 is a first control voltage and a usage signal. 2 selectors. Further, 11 is a reference value, 12 is a usage amount signal, 13 is an upper limit value, 14 is an upper limit signal, 15 is a lower limit value, 16 is a lower limit signal, and CLK is a clock terminal.

FIG. 6 is a diagram showing the timing of each signal waveform in order to explain the operation of the clock recovery device of the third embodiment. In FIG. 6, a is a waveform of the usage amount that changes depending on the amount of information stored in the buffer 1, b is a waveform of the first control voltage output from the SRTS method control voltage generation unit 2, and c is a waveform.
Is a waveform of the usage amount signal 12 of the buffer 1, d is a waveform of the second control voltage output from the filter 3, and e is a waveform output from the first selector 5.

In the clock regenerating apparatus of the third embodiment having the above-described configuration, the SRTS is replaced with the output of the intermediate voltage generating section 20 input to the second selector 21 in the configuration of the first embodiment. The first control voltage, which is the output of the normal control voltage generator 2, is input. First, buffer 1
SRT after the amount of information stored in
The operation while the clock is being reproduced by the S method (the period B shown in FIG. 6) will be described.

In the SRTS method control voltage generator 2, S is based on the synchronization time stamp residual information stored in the cell.
The first control voltage for reproducing the clock by the RTS method is generated and output (waveform b shown in FIG. 4). At this time,
The second selector 21 selects the first control voltage and outputs it to the filter 3. The filter 3 smoothes the first control voltage output from the second selector 21 and outputs it as the second control voltage (waveform d shown in FIG. 6).

The upper limit of the amount of information stored in the buffer 1 is 13
After the above (or the lower limit value 15 or less) and switching to the adaptive clock method (period C in FIG. 6), the second selector 21
Then, the usage signal 12 from the buffer 1 (waveform c shown in FIG. 6)
To output to the filter.

From the above, when the amount of information stored in the buffer 1 exceeds the upper limit value 13 (or lower limit value 15), the first selector 5 switches to the adaptive clock method.
Even if the first control voltage input to the filter 3 is switched to the usage amount signal 12 (position D in FIG. 6), the output second control voltage changes from the value of the first control voltage. Therefore, there is almost no voltage fluctuation that occurs when switching from the SRTS method to the adaptive clock method (waveform e shown in FIG. 6), and the amount of jitter that occurs in the clock output from the voltage controlled oscillator 6 can be greatly reduced.

The configuration of the third embodiment is similar to SRTS.
Since the output of the legal control voltage generator 2 is selected by the second selector 21 and input to the filter 3, the clock regenerator can be realized with a smaller circuit configuration than the configuration of the first embodiment.

[0045]

As described above, according to the present invention,
After the amount of information stored in the buffer becomes equal to or higher than the upper limit (or lower than the lower limit), when the SRTS method is switched to the adaptive clock method by the first selector, even if the filter input is switched, its output is intermediate. Since the output value of the voltage generator changes to the value of the usage signal, the first control voltage and the second control voltage
The voltage difference between the control voltages can be reduced, the voltage fluctuation caused when switching is reduced, and the amount of jitter generated in the clock output from the voltage controlled oscillator can be reduced.

Further, at the time of clock reproduction of the SRTS method, the threshold value control unit changes the reference value and controls so that the respective control voltages of the first control voltage and the second control voltage match.
The voltage fluctuation that occurs when switching from the SRTS method to the adaptive clock method is almost eliminated, and the amount of jitter that occurs in the clock output from the voltage controlled oscillator can be greatly reduced.

After the amount of information stored in the buffer becomes equal to or higher than the upper limit value (or equal to or lower than the lower limit value), when switching from the SRTS method to the adaptive clock method by the first selector 5, the first input to the filter is performed. Even if the control voltage is changed from the control voltage to the usage signal, the second control voltage, which is the output, changes from the value of the first control voltage. Therefore, almost no voltage fluctuation occurs when switching from the SRTS method to the adaptive clock method. Therefore, the amount of jitter generated in the clock output from the voltage controlled oscillator can be significantly reduced, and the output of the SRTS method control voltage generator is selected by the second selector and input to the filter. There is an effect that can be realized with a smaller circuit configuration.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a clock recovery device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing the timing of each signal waveform for explaining the operation of the clock recovery device according to the first embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a clock recovery device according to a second embodiment of the present invention.

FIG. 4 is a diagram showing the timing of each signal waveform for explaining the operation of the clock recovery device according to the second embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a clock recovery device according to a third embodiment of the present invention.

FIG. 6 is a diagram showing the timing of each signal waveform for explaining the operation of the clock recovery device according to the third embodiment of the present invention.

FIG. 7 is a block diagram showing a configuration of a clock recovery device that combines a conventional SRTS method and an adaptive clock method.

FIG. 8 is a diagram showing the timing of each signal waveform for explaining the operation of the conventional clock recovery device.

[Explanation of symbols]

1 ... Buffer, 2 ... SRTS method control voltage generator, 3
... filter, 4 ... clock recovery method switching section, 5 ... first
Selector, 6 ... Voltage controlled oscillator, 11 ... Reference value,
12 ... Usage signal, 13 ... Upper limit value, 14 ... Upper limit signal, 15
… Lower limit value, 16… Lower limit signal, 20… Intermediate voltage generator,
21 ... 2nd selector, 22 ... Threshold control part.

Claims (3)

[Claims] 1. Storage means for storing information stored in a received cell and outputting a usage signal indicating that the amount of the information is equal to or more than a preset threshold value, and frequency information of a clock on the transmission side. The first for reproducing the clock by the SRTS method using the synchronous time stamp residual information that represents
SRTS method control voltage generating means for generating the control voltage of
Filter means for generating a second control voltage for smoothing the input signal and reproducing the clock by the adaptive clock method, and first for selecting either the first control voltage or the second control voltage. Selection means, intermediate voltage generation means for outputting a voltage close to the first control voltage, and either the output of the intermediate voltage generation means or the usage amount signal output by the storage means to select the filter. Second selection means for inputting to the means, and clock reproduction method switching means for outputting a selection signal for switching the clock reproduction method of the SRTS method and the adaptive clock method to the first selection means and the second selection means. A voltage control oscillation means for changing the frequency of a clock output according to the control voltage selected by the first selection means, wherein the first control voltage is selected by the first selection means. While the second selecting means selects the output of the intermediate voltage generating means and inputs the output to the filter means, the second selecting voltage is selected by the first selecting means. The selection means of 2 selects the use amount signal,
Even if the second control voltage changes, the second control voltage changes from the output value of the intermediate voltage generating means, so when the first control voltage is switched to the second control voltage. A clock regenerator characterized in that fluctuations in voltage that occur are reduced and the amount of jitter that occurs in the clock output from the voltage controlled oscillator is reduced. 2. Storage means for storing the information stored in the received cell and outputting a usage amount signal indicating that the amount of the information is equal to or more than a preset threshold value, and frequency information of the transmitting side clock. The first for reproducing the clock by the SRTS method using the synchronous time stamp residual information that represents
SRTS method control voltage generating means for generating the control voltage of
Filter means for smoothing the usage amount signal to generate a second control voltage for reproducing a clock by the adaptive clock method, and selecting either the first control voltage or the second control voltage. First selection means, clock reproduction method switching means for outputting to the first selection means a selection signal for switching the clock reproduction method of the SRTS method and the adaptive clock method, and the control selected by the first selection means Voltage control oscillation means for changing the frequency of the clock to be output according to the voltage, and threshold control means for changing the threshold of the storage means so that the first control voltage and the second control voltage match. While the first control voltage is being selected by the first selection means, the threshold control means sets the threshold value of the storage means so that the first control voltage and the second control voltage match. The changing control reduces the voltage fluctuation that occurs when the first control voltage is switched to the second control voltage, and reduces the amount of jitter that occurs in the clock output from the voltage controlled oscillator. Clock reproduction device. 3. Storage means for storing the information stored in the received cell and outputting a usage signal indicating that the amount of the information is equal to or greater than a preset threshold value, and frequency information of the clock on the transmission side. The first for reproducing the clock by the SRTS method using the synchronous time stamp residual information that represents
SRTS method control voltage generating means for generating the control voltage of
Filter means for generating a second control voltage for smoothing the input signal and reproducing the clock by the adaptive clock method, and first for selecting either the first control voltage or the second control voltage. Selecting means, second selecting means for selecting one of the first control voltage and the usage amount signal output from the storing means and inputting it to the filter means, the first selecting means, and the first selecting means. SRT as the second selection means
Clock regeneration method switching means for outputting a selection signal for switching the clock regeneration method between the S method and the adaptive clock method, and voltage control for changing the frequency of the clock output according to the control voltage selected by the first selection means. Oscillating means, while the first control voltage is being selected by the first selecting means, the second selecting means selects the first control voltage and inputs it to the filter means, By making the second control voltage equal to the first control voltage, the second selection means selects the usage amount signal when the second control voltage is selected by the first selection means. do it,
Even if the second control voltage changes, the second control voltage changes from the value of the first control voltage. Therefore, when switching from the first control voltage to the second control voltage. A clock regenerator characterized in that fluctuations in voltage that occur are reduced and the amount of jitter that occurs in the clock output from the voltage controlled oscillator is reduced.