JPH09213904A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the electric characteristics, without deteriorating electrode parts by forming a second metal film on a first metal film made of a boride selected among transition metal elements and upper electrode formed on a ferroelectric film formed on the second metal film. SOLUTION: On a low-resistance Si substrate 1, a TiB2 layer 2 is deposited by the r-f sputtering method, Pt layer 3 is deposited on this layer 2 by the d-c sputtering method, lead zirconate titanate layer 4 is formed on the Pt layer by the sol-gel method and upper Au electrode 5 is formed with a metal mask to complete a capacitor. TiB2 is used here as a boride but other borate may be used. Instead of the Pt layer, Pd, Ir, Rh, Re or RUO2 may be used. Thus, the increase of the contact resistance and growth of a series parasitic capacitance are suppressed, no deterioration of the electrode parts occurs and fine workability is excellent enough to make good electric characteristics.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitor using a ferroelectric material, a memory using the same, a semiconductor device for wireless communication, and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, along with the miniaturization and high performance of electronic equipment, for example, dynamic random access memory (DR
A high-capacity capacitor is required for a cell capacitor of AM) and a bypass capacitor of a communication IC. For this reason, attempts have recently been made to use a material exhibiting ferroelectricity at a temperature below the Curie point (hereinafter referred to as a ferroelectric material) as a dielectric material of a capacitor. Known ferroelectric materials include, for example, perovskite-based materials and tungsten bronze-based dielectric materials. Specific examples of perovskite compounds include strontium titanate (S
rTiO ₃ ), barium titanate (BaTiO ₃ ), lead zirconate titanate (Pb (Zr, Ti) O ₃ ) and the like. These ferroelectric materials have a relative dielectric constant of 100.
The above is the feature that it is larger than the conventional SiO ₂ and Si ₃ N ₄ .

Japanese Unexamined Patent Publication (Kokai) No. 4-181766 describes that a capacitor using the above ferroelectric substance often uses a two-layer structure of Pt and TiN for an electrode provided in contact with the ferroelectric substance. Using Pt for the first layer is P
This is because t is excellent in oxidation resistance and does not easily react with the above-mentioned high dielectric substance or ferroelectric substance, and the TiN of the second layer has a function of suppressing the reaction between Pt and the underlying semiconductor or metal.

In Japanese Patent Laid-Open No. 7-78727, Ti is used.
It is described that a boride such as B is used for the electrode.

Further, Japanese Patent Application Laid-Open No. 62-207784 describes forming a titanium carbide layer on a titanate-based ceramics.

[0006]

[Problems to be Solved by the Invention] Pt and TiN
When forming a capacitor having a layered electrode, oxygen penetrates the Pt layer during deposition of a ferroelectric thin film or during heat treatment in an oxygen atmosphere necessary for crystallization, and TiN of the lower layer is formed.
Reaching the layer and TiO ₂ is formed at the interface between the Pt layer and the TiN layer. Therefore, the contact resistance between Pt / TiN increases and series parasitic capacitance is generated. In order to avoid this problem, it is necessary to make the thickness of the Pt layer sufficiently thick.
About m is required. However, the Pt layer cannot be processed by a fine processing technique such as a reactive ion etching method, and a method unsuitable for the fine processing such as an ion milling method must be used. Very difficult.

When a boride such as TiB is used for an electrode, it is generally said that the boride is excellent in oxidation resistance. However, when the ferroelectric layer is directly formed, the ferroelectric layer and the boride layer are combined with each other. The interface is oxidized and a transition metal oxide is formed to form a series parasitic capacitance, so that the capacitance of the entire capacitor is reduced. Similarly, even if TiC is used for the electrode, T
Although not as large as iB, the intervening surface between the ferroelectric layer and the carbide layer is oxidized and the capacitance of the entire capacitor is reduced. In addition, since the crystallinity of the boride thin film is inferior to that of Pt, when the ferroelectric thin film is formed on the boride layer, the crystallinity of the ferroelectric is also insufficient, and the film such as the dielectric constant and the coercive electric field is formed. Characteristics deteriorate.

An object of the present invention is to provide a semiconductor device in which the electrode portion of a capacitor using a ferroelectric thin film is not deteriorated, fine processability is excellent, and the electric characteristics of the ferroelectric are good.

[0009]

[Means for Solving the Problems] The above objects are 4a group, 5
a first metal layer made of at least one kind of boride selected from the group a, 6a, 7a, and 8 transition metal elements; and Pt, Pd, Ir, Rh on the first metal layer. R
This is achieved by providing a second metal layer of either e or RuO _2, a ferroelectric film on the second metal layer, and an upper electrode on the ferroelectric film. Pt, Pd, Ir,
The thickness of the metal layer of any one of Rh, Re and RuO ₂ is preferably set to 10 nm or more and 100 nm or less.

Further, the above-mentioned objects are 4a group, 5a group, 6a
A first metal layer made of at least one kind of carbide selected from group 7a group 7 transition metal elements, and Pt, Pd, Ir, Rh, Re, RuO ₂ on the first metal layer. This is achieved by providing a second metal layer made of any one, a ferroelectric film on the second metal layer, and an upper electrode on the ferroelectric film. Pt, Pd, Ir, Rh, R
The thickness of the metal layer of either e or RuO ₂ is 10
It is preferable that the thickness is set to be 100 nm or more and 100 nm or less.

Hereinafter, Pt, Pd, Ir, Rh, Re, R
An example will be described in which Pt is used as one of the metals of uO ₂ .

Examples of the above boride include TiB ₂ ,
_{ZrB 2, WB 2, MoB 2} , ReB 2, RuBx and the like. The oxidation resistance of these metals is superior to nitrides.
Therefore, there is little reaction with oxygen that diffuses inside the Pt layer during deposition of the ferroelectric thin film or during heat treatment in an oxygen atmosphere necessary for crystallization, and a high resistance layer is formed at the interface with the Pt layer. Hateful. Moreover, it hardly reacts with Pt, and acts as a good diffusion barrier against Pt. Therefore, even if the Pt layer is thinned, a good capacitor having a small contact resistance and series parasitic capacitance can be obtained. Further, since the ferroelectric layer and the boride layer are not in direct contact with each other, there is no fear of forming an oxide layer at the interface. Further, since the Pt layer is superior in crystallinity to the boride layer, the ferroelectric characteristic of the ferroelectric layer formed thereon is also good. The thickness of the Pt layer is preferably 10 nm or more in order to suppress the oxidation of the boride layer surface and to secure the characteristics of the ferroelectric layer to be deposited on the Pt layer. Is desirable.

Examples of the above-mentioned carbides include TiC and Zr.
C, WC, MoC, TaC, etc. are mentioned. The electric resistance of these metals is equal to or smaller than that of conventional nitrides such as TiN, and the oxidation resistance is superior to that of borides as well as nitrides. Therefore, when a metal layer such as Pt is inserted between the carbide layer and the ferroelectric layer, the oxidation of the carbide surface is further suppressed.

Examples of the ferroelectric layer in the capacitor according to the present invention include perovskite compounds and tungsten bronze compounds. Specific examples of perovskite compounds include strontium titanate (SrTi
O ₃ ), barium titanate (BaTiO ₃ ), lead zirconate titanate (Pb (Zr, Ti) O ₃ ), and the like.

Further, even if C contained in the carbide layer diffuses in Si, it is electrically inactive and does not serve as a donor or an acceptor. Therefore, when the base material is Si, there is an advantage that the electrical characteristics are hardly deteriorated even when the carbide layer reacts with the base Si.

It should be noted that another material may be used for the reason of improving the adhesion between the ferroelectric thin film layer and the Pt layer, the Pt layer and the boride layer, the Pt layer and the carbide layer, and the ferroelectric layer and the carbide layer. It may be inserted.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION

Example 1 An example of a capacitor using TiB ₂ as a boride layer and Pt as a metal layer formed thereon will be described. FIG. 1 is a diagram showing a layered structure of the produced capacitor. A TiB ₂ layer 2 having a thickness of 100 nanometers is formed on a low resistance silicon substrate 1, Ar is used as an atmosphere gas, and a gas pressure is set to 2
Pa was used, the applied RF power was 300 W, and the sintered body was deposited by the RF sputtering method using the target material. On this TiB ₂ layer 2, a Pt layer 3 having a thickness of 100 nanometers is formed.
By a DC sputtering method using Ar as an atmosphere gas,
The gas pressure was 2 Pa, the input power was 400 W, and the substrate temperature was 500 ° C. for deposition. A lead zirconate titanate layer 4 having a thickness of 100 nanometers was formed on the Pt layer by a sol-gel method. The sol used was a reaction product of lead acetate, titanium isopropoxide, and zirconium isopropoxide in methoxyethanol. 650 in oxygen atmosphere
Crystallization was performed by rapid thermal annealing at 2 ° C for 2 minutes. Further, the Au upper electrode 5 was formed using a metal mask to complete the capacitor.

The results of examining the dielectric characteristics by applying a voltage between the Au upper electrode and the substrate of the capacitor obtained above are shown in FIG.
Shown in As can be seen from FIG. 2, a good hysteresis curve is obtained. This indicates that the power supply from the substrate is good, and that the influence of the oxidation at the interface between the TiB ₂ layer and the Pt layer and the reaction between the TiB ₂ layer and the underlying Si layer can be ignored in terms of electrical characteristics. There is.

Further, although the case where the Pt electrode is formed by the sputtering method has been described in the present embodiment, similar results were obtained also for the Pt electrode formed by the vacuum evaporation method.

In this embodiment, TiB ₂ was used as the boride, but other boride may be used. The same applies when Pd, Ir, Rh, Re or RuO ₂ is used instead of the Pt layer formed on the boride layer.

Although the Pt layer is formed on the TiB ₂ layer in this embodiment, it may be formed on the TiC layer. As a method of forming the TiC film, for example, an RF sputtering method using a sintered body as a target material may be used.

<Embodiment 2> FIGS. 3 to 7 show an embodiment of a memory cell using the present invention. In this embodiment, a flat memory cell structure in which the storage capacitor portion is provided above the transistor is used.

First, as shown in FIG. 3, a switch transistor is formed by a conventional MOSFET forming process. Here, 21 is a p-type semiconductor substrate, 22 is an element isolation insulating film, 23 is a gate oxide film, 24 is a word line to be a gate electrode, 25 and 26 are n-type impurity diffusion layers (phosphorus), 27.
Is an interlayer insulating film. Using a known CVD method on the entire surface, SiO ₂ 28 having a thickness of 50 nm and S having a thickness of 600 nm are formed.
i ₃ N ₄ 29 was deposited respectively, and Si ₃ N ₄ of the film thickness was etched to fill the insulating film between the word lines. The SiO ₂ 28 serves as a base for processing the bit line in the next step, and has a function of preventing the substrate surface from being exposed and the inter-element isolation insulating film from being scraped.

Next, as shown in FIG. 4, a portion 25 where the bit line is in contact with the n-type diffusion layer on the substrate surface and a portion 26 where the storage electrode is in contact with the n-type diffusion layer on the substrate surface are known photolithography methods. Then, an opening was formed by using a dry etching method. Polycrystalline silicon containing n-type impurities having a thickness of 600 nm is deposited by using the CVD method, and then etching is performed by the film thickness, so that the polycrystalline silicon 31 inside the hole formed by the above-described etching, I embedded 32.

Next, as shown in FIG. 5, an insulating film 41 is deposited on the entire surface by a known CVD method, and an upper portion of the polycrystalline silicon 31 is electrically connected to electrically connect the bit line to the diffusion layer 25 of the substrate. The insulating film 41 was opened by using the known photolithography method and dry etching method. Next, a stacked film of a metal silicide, which is a bit line material, and polycrystalline silicon is deposited, and SiO ₂ 43 having a thickness of 200 nm is deposited thereon, and the SiO ₂ 43 and the bit line 42 are formed by a known photolithography method. It was processed by using the dry etching method to form the bit line 42 having a desired pattern. Next, Si ₃ N ₄ having a film thickness of 150 nm is deposited by a CVD method and etched by a dry etching method to form a sidewall spacer 44 of Si ₃ N _{4 on} the side wall portion of the bit line to insulate the bit line. . The insulating film 41 above the polycrystalline silicon 32 is opened by using the known photolithography method and dry etching method.

Next, as shown in FIG. 6, a silicon oxide film type insulating film 51 such as BPSG was deposited and flattened. The insulating film 51 needs to have a film thickness sufficient to flatten the substrate surface. In this embodiment, the insulating film 51 has a thickness of 500 nm. S on the substrate surface by the CVD method
A method of depositing iO ₂ and flattening it by an etch back method may be used. Then, a contact hole is formed by using a known photolithography method and dry etching method. Next, the phosphorus-doped amorphous silicon film 52 for embedding is C
After depositing 200 nm by the VD method, the contact hole was filled by etching back by the dry etching method.

Next, as shown in FIG. 7, the thickness is 100 nm.
A TiB ₂ film 61 was formed. In this embodiment, the first embodiment
RF using TiB ₂ sintered body as a target as shown in
It was deposited by the sputtering method. Furthermore, P with a thickness of 100 nm
The t base electrode 62 was formed by the DC sputtering method. DC
A TiN film was deposited to a thickness of 50 nm by a sputtering method, a pattern was transferred to TiN by a dry etching method using SF ₆ using a photoresist as a mask, and a Pt base electrode 62 was patterned by a sputter etching method using this TiN as a mask. . Next, after removing TiN used for the mask by a wet etching method, a ferroelectric thin film 63 was formed. In this embodiment, the lead zirconate titanate (Pb (Zr
After forming a _0.5 Ti _0.5 ) O ₃ ) thin film, it was crystallized by performing a heat treatment at 650 ° C. for 120 seconds in an oxygen atmosphere. Then, a plate electrode is deposited and patterned to complete the capacitor of the memory cell. However, in FIG. 7, the plate electrode is not shown because the drawing is complicated.

The dielectric characteristics of this capacitor were measured in the same manner as that shown in FIG. The area of the capacitor is 0.2 ~
When the samples that were changed to 100 μm ² were examined, it was possible to feed power from the substrate, and good hysteresis curves were obtained in all cases.

Lead zirconate titanate (Pb (Zr _0.5 T
As a method for forming the i _0.5 ) O ₃ ) thin film, a high frequency magnetron sputtering method may be used. High frequency power 200
When W, Ar 90% and O ₂ 10% were used as the sputtering gas, and a film was formed at a high frequency power of 200 W, a gas pressure of 10 Pa and a substrate temperature of 650 ° C., almost the same characteristics were obtained.
Therefore, if the lower electrode is formed by the method shown in the present invention, the diffusion preventing film and the Pt film can be formed by either the method of crystallizing an amorphous ferroelectric by post annealing or the method of directly forming a crystallized film. There is no risk of oxidation at the interface. Therefore, the reactive vapor deposition method or the CVD method may be used.

In this embodiment, lead zirconate titanate (when Pb (Ti _x Zr _1-x ) O ₃ , x = 0.5) is shown as an example of the ferroelectric substance. Lead zirconate and barium strontium titanate ((Ba _x
A memory cell can be similarly formed by using Sr _1-x ) TiO ₃ (x is 0 or more and 1 or less)), lead barium zirconate titanate, or a bismuth-based layered ferroelectric.

[0031]

According to the present invention, it is possible to suppress an increase in contact resistance and the occurrence of series parasitic capacitance in a capacitor using a ferroelectric thin film, without deterioration of an electrode portion, excellent in fine workability, and A semiconductor device having favorable electric characteristics can be obtained.

[Brief description of drawings]

FIG. 1 is a diagram showing a layer structure of a capacitor shown in Example 1 of the present invention.

FIG. 2 is a diagram showing dielectric characteristics of the capacitor shown in FIG.

FIG. 3 is a cross-sectional view showing a manufacturing process of a memory cell using the present invention.

FIG. 4 is a cross-sectional view showing a manufacturing process of a memory cell using the present invention.

FIG. 5 is a cross-sectional view showing a manufacturing process of a memory cell using the present invention.

FIG. 6 is a cross-sectional view showing a manufacturing process of a memory cell using the present invention.

FIG. 7 is a cross-sectional view showing a manufacturing process of a memory cell using the present invention.

[Explanation of symbols]

1 ... Low resistance Si substrate, 2 ... TiB2 layer, 3 ... Pt layer, 4
... Lead zirconate titanate layer, 5 ... Au upper electrode, 21 ...
Semiconductor substrate, 22 ... Element isolation oxide film, 23 ... Gate oxide film, 24 ... Word line, 25 ... Impurity diffusion layer (portion where bit line contacts n-type diffusion layer on substrate surface), 26 ... Impurity diffusion layer ( Portion where the storage electrode contacts the n-type diffusion layer on the substrate surface), 27, 28 ... Interlayer insulating film, 29 ... Si3N4
Films, 31, 32 ... Polycrystalline silicon (contact pads), 41 ... Interlayer insulating film, 42 ... Bit line, 43 ... Interlayer insulating film, 44 ... Si3N4 film, 51 ... Interlayer insulating film, 5
2 ... Polycrystalline silicon (contact pad), 61 ... T
iB2 layer, 62 ... Pt base electrode layer, 63 ... Ferroelectric thin film, 64 ... Plate electrode.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁶ Identification number Internal reference number FI Technical indication location H01L 21/8247 29/788 29/792 (72) Inventor Masahiko Hiraya 1-280, Higashi Koikeku, Kokubunji, Tokyo Address: Central Research Laboratory, Hitachi, Ltd. (72) Hiroshi Miki, 1-280, Higashi Koikeku, Kokubunji, Tokyo Metropolitan Research Institute, Hitachi, Ltd. (72): Yuichi Matsui, 1-280, Higashi Koikeku, Kokubunji, Tokyo Hitachi, Ltd. Central Research Laboratory

Claims (9)

[Claims] 1. A first metal film comprising at least one boride selected from the group 4a, 5a, 6a, 7a, and 8 transition metal elements, and the first metal film on the first metal film. A second metal film formed of any one of Pt, Pd, Ir, Rh, Re, and RuO ₂ , a ferroelectric film provided on the second metal film, and a ferroelectric film on the ferroelectric film. A capacitor having an upper electrode provided on the capacitor. 2. The capacitor according to claim 1, wherein the thickness of the second metal film is 10 nm or more and 100 nm or less. 3. A first metal film made of at least one kind of carbide selected from the group 4a, 5a, 6a, 7a, and 8 transition metal elements, and provided on the first metal film. A second metal film made of any one of Pt, Pd, Ir, Rh, Re, and RuO ₂ , the ferroelectric film provided on the second metal film, and the ferroelectric film on the ferroelectric film. A capacitor having an upper electrode provided. 4. The capacitor according to claim 3, wherein the thickness of the second metal film is 10 nm or more and 100 nm or less. 5. A group 4a provided on the polycrystalline silicon film,
A first metal film made of at least one kind of carbide selected from the group 5a, 6a, 7a, and 8 transition metal elements, and Pt, Pd, and I provided on the first metal film.
A second metal film made of any one of r, Rh, Re, and RuO ₂ , a ferroelectric film provided on the second metal film, and an upper electrode provided on the ferroelectric film. A semiconductor device comprising: 6. A MIS transistor having a source and a drain, and a group 4a and 5a connected to the drain.
A first metal film made of at least one kind of boride selected from the group 6a group 7a group 8a transition metal elements,
Pt, Pd, Ir, R provided on the first metal layer
a second metal film of any one of h, Re and RuO ₂ , a ferroelectric film formed on the second metal film, and an upper electrode formed on the ferroelectric film. A semiconductor device characterized by: 7. A group of 4a, 5a, 6a and 7a on a substrate.
Forming a first metal film made of at least one kind of boride selected from Group 1 and Group 8 transition metal elements; and Pt, Pd, Ir, Rh, Re, R on the first metal film.
a step of forming a second metal film of any one of uO ₂ , a step of forming a ferroelectric film on the second metal film, and a step of forming an upper electrode on the ferroelectric film. A method of manufacturing a semiconductor device, comprising: 8. A group of 4a, 5a, 6a and 7a on a substrate.
A step of forming a first metal film made of at least one kind of carbide selected from group 8 transition metal elements, and Pt, Pd, Ir, Rh, Re, Ru on the first metal film.
A step of forming a second metal film made of any one of O ₂ , a step of forming a ferroelectric film on the second metal film, and a step of forming an upper electrode on the ferroelectric film. A method of manufacturing a semiconductor device, comprising: 9. A step of forming a MIS type transistor having a source and a drain, and at least one kind selected from the group 4a, 5a, 6a, 7a and 8 transition metal elements connected to the drain. No. 1 consisting of boride
The step of forming a metal film of P, and P on the first metal layer.
a step of forming a second metal film of any one of t, Pd, Ir, Rh, Re and RuO ₂ , a step of forming a ferroelectric film on the second metal film, and the ferroelectric film And a step of forming an upper electrode thereon.