JPH09213074A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a high speed operation with a small power consumption by restricting leakage currents by a current limiting device while making a third logic gate group NAND and a fourth logic gate group INV non-selections when a first logic gate group NAND and a second logic group INV are selected. SOLUTION: When a hierarchical feeder system constituted of two stages of an NAND circuit and the CMOS logic circuit of an inverter is applied to a decoder, hierarchical feeders are used in both sides of a power source voltage VCC and a grounding voltage VSS. All of these NAND circuits output the VCC at the time of a stand-by and small number of the circuits output 0V at the time of an operation. Since a through current is determined by the NMOS transistor TR of the VSS side, the hierarchical feeder is used on the VSS side. Conversely, all of inverters output 0V at the time of the stand-by and a small number of invertes outputs the VCC at the time of the operation. Since the through current is determined by the PMOS transistor TR of the VCC side, the hierarchical feeder is used on the VCC side. Thus, through currents are reduced without making operations unstable by using hierarchical feeders on both sides of the VCC and the VSS.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit composed of fine MOS transistors, and more particularly to a circuit suitable for high speed / low power operation.

[0002]

[Prior Art] 1989 International Symposium OMBLS Technology, Systems and Applications, Proceedings of Technical Papers (198
May 9) pp. 188 to 192 (1989 In)
international Symposium on
VLSI Technology, Systems
and Applications, Proceed
ings of Technical Papers,
pp. As described in 188-192 (May 1989)), the breakdown voltage of a MOS transistor decreases as it is miniaturized, so the operating voltage must be lowered.

In this case, in order to maintain high-speed operation, it is necessary to reduce the threshold voltage (VT) of the MOS transistor in proportion to the decrease in operating voltage. This is because the operating speed is controlled by the effective gate voltage of the MOS transistor, that is, the value obtained by subtracting VT from the operating voltage, and the higher this value, the higher the speed.

For example, in a 16 gigabit DRAM which is expected to have an effective channel length of 0.15 μm or less, a standard operating voltage inside the chip of 1 V, and a boosted word line voltage of about 1.75 V, the VT (channel Width μ
m, drain current of 10 nA, standard condition of junction temperature of 25 ° C., and VT of PMOS transistor is shown by inverting the sign for simplicity) is also −0.04V.

However, the operating voltage becomes about 2 V or less,
Phenomenon in which if the VT is forced to be about 0.4 V or less, the sub-threshold characteristic (tailing characteristic) of the MOS transistor makes it impossible to completely turn off the transistor, and a direct current flows. Occurs.

The conventional CMOS inverter shown in FIG. 6 will be described. Ideally, when the input signal IN is at low level (= VSS), the N-channel MOS transistor MN
Is off and IN is at a high level (= VCC), the P-channel MOS transistor MP is off, and in any case, no current flows when the output voltage is fixed.
However, when the VT of the MOS transistor becomes low, the subthreshold characteristic cannot be ignored.

As shown in FIG. 7, the drain current IDS in the subthreshold region is proportional to the exponential function of the gate-source voltage VGS and is expressed by the following equation.

[0008]

[Equation 1]

Here, W is the channel width of the MOS transistor, I0 and W0 are the current value and channel width when defining VT, and S is the tailing coefficient (VGS-log ID).
It is the reciprocal of the slope of the S characteristic. Therefore, VGS = 0
But subthreshold current

[0010]

[Equation 2]

[0011] flows. Since the transistor in the off state in the CMOS inverter of FIG. 6 has VGS = 0, the above current IL flows from the high power supply voltage VCC toward the low power supply voltage VSS, which is the ground potential, when not operating.

This subthreshold current increases exponentially from IL to IL 'when the threshold voltage is lowered from VT to VT', as shown in FIG.

As is apparent from the above equation of equation (2), in order to reduce the subthreshold current, VT should be increased or S should be decreased. However, the former causes a decrease in speed due to a decrease in effective gate voltage. In particular, from the viewpoint of breakdown voltage, if the operating voltage is lowered along with the miniaturization, the speed decrease becomes remarkable, and the advantage of miniaturization cannot be utilized, which is not preferable. In addition, the latter is difficult for the following reasons as long as it is assumed to operate at room temperature.

The tailing coefficient S is expressed as follows by the capacitance COX of the gate insulating film and the capacitance CD of the depletion layer under the gate.

[0015]

(Equation 3)

Here, k is the Boltzmann constant, T is the absolute temperature, and q is the elementary charge. As is clear from the above equation, CO
S ≧ kT ln 10 regardless of whether X or CD
/ Q, and it is difficult to set it to 60 mV or less at room temperature.

[0017]

Due to the above-mentioned phenomenon, the substantial direct current of the semiconductor integrated circuit composed of a large number of MOS transistors is remarkably increased. In particular, at the time of high temperature operation, since VT is low and S is large, this problem becomes more serious. This increase in subthreshold current is an essential problem in the downsizing era of computers and the like where low voltage operation and low power consumption are important, or in the era of battery operation that is essential for portable devices. .

This problem will be further described using a memory which is a typical semiconductor integrated circuit. Memory LSI, such as dynamic random access memory (DRA)
In M), as shown in FIG. 8, in order to select an arbitrary memory cell MC in the memory array MA, a row line (word line W
X decoder (XDEC) for selecting and driving L), word driver (WD), sense amplifier (SA) for amplifying signals of column line (data line D), and sense amplifier drive circuit (SAD) for driving sense amplifier ) And a Y decoder (YDEC) for selecting a column line. Further, a peripheral circuit (PR) for controlling these circuits is incorporated. The main part of these circuits has a circuit configuration based on the above-described CMOS logic circuit in order to reduce power consumption during operation, standby, battery backup, and the like. However, the threshold voltage V of the transistor
T (Hereinafter, for simplicity, PMOS transistor and NMO
It is assumed that the S transistors have the same absolute value and VT. )
As the value decreases, the shoot-through current increases sharply for the above reason. This becomes particularly noticeable in the decoder and driver or the peripheral circuit section. This is because the number of circuits that make up these is overwhelmingly large and has a special function.

For example, regarding a decoder and a driver, a small number of specific circuits are selected and driven from a large number of circuits of the same type by an address signal. If VT is sufficiently large, many non-selection circuits are completely cut off, that is, while the shoot-through current is substantially zero, this selection / driving is performed. Generally, as the storage capacity of the memory increases, the number of decoders and drivers increases, but unless the through current flows through the non-selection circuit, the total current does not increase even if the storage capacity increases. However, this is possible only when VT is large, and when it is low as described above, the shoot-through current increases drastically. Similarly, when the entire chip is unselected (standby state), most circuits in the chip could be turned off in the past to minimize the power supply current, but this is no longer possible. This problem is not limited to the memory LSI, but is common to all semiconductor integrated circuits based on a CMOS logic circuit containing a memory.

Therefore, the object of the present invention is to provide MO
It is to provide a high-speed and low-power semiconductor integrated circuit device even if the S-transistor is miniaturized, and particularly to reduce a through current of a word driver, a decoder, or the like which is a problem in a memory or a semiconductor integrated circuit device including the memory. .

Patent applications relating to the through current include JP-A-60-167523 and JP-A-5-1081.
94, JP-A-5-210976, and JP-A-6-298.
34, JP-A-5-268065, and JP-A-5-291.
929, JP-A-5-347550, and JP-A-6-53.
496, JP-A-6-120439, JP-A-6-203
There are 558 etc.

[0022]

In order to achieve the above object, a large number of circuits of the same kind are configured, and only a small number of circuits operate selectively in a desired time zone, and the rest are in a non-selected state. In such a semiconductor integrated circuit, the above-mentioned many circuits are made into at least one block, a feeder line is provided corresponding to the block, and a desired operating voltage is selectively applied to the feeder line. The selection function is realized by an address signal, a signal designating an operation mode such as activation and standby, a signal designating a specific time zone within the activation time zone, or a combination signal thereof.

[0023]

Even if the threshold voltage of the transistor is low, the through current flowing in the non-selection circuit can be minimized.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, an example in which the present invention is applied to a word driver (WD in FIG. 8) of DRAM will be described. Taking the state after the word line is selected and the required word voltage VCH is applied to the word line as an example, in the conventional configuration shown in FIG. 9, as long as VT is sufficiently high, all CMOS
No through current flows through the driver. However, VT is 0.
When the voltage becomes lower than about 4V, a through current flows through the word driver, the capacity is increased, the number of word drivers (r) increases, and this size cannot be ignored. The total IA of this through current is

[0025]

(Equation 4)

Can be expressed as Here, as shown in FIG.
Is a threshold voltage defined by the current value I0, and S is a tailing coefficient. Since the word driver power supply VCH is normally supplied by boosting the external power supply inside the chip, the current drive capacity is limited and cannot be processed when IA increases.

As a method of solving this, (1) a method of applying a required voltage to a power supply line of a word driver for a desired period, (2) a word driver group is divided into a large number of blocks composed of a plurality of drivers, There are a method of applying a required voltage only to a specific block desired to be selected, and a method of (3) combining both.

FIG. 10 shows an embodiment in which the required voltage is applied to the power supply line of the word driver for a desired period of time to limit the time during which the subthreshold current flows. The feature is that the required word voltage is supplied to the common power supply line of the block after the logic input of the driver is established. According to the operation timing shown in FIG. 11, the PMO forming the word driver
The operation will be described by focusing on the voltage relationship of the S transistor. In the case of a well-known DRAM memory cell including an NMOS transistor and a capacitor (storage capacity), the voltage of all word lines in the non-selected state must be VSS (0V), so that all word drivers including the word driver to be selected are selected. The gate voltage of the PMOS transistor in the word driver is VCH. Next, when the selection operation starts, the gate N of the PMOS transistor of the selection driver (# 1)
Only X1 becomes 0V. At this time, the VCHs of the other word drivers (# 2 to #r) remain as they are, and thus the gate voltages of the PMOS transistors of all the word drivers are determined. Now, the voltage of the common power supply line PB to which the source of the PMOS transistor is connected is
Until the gate voltage of the transistor is fixed, the PM
The subthreshold current of the OS transistor is set to a certain voltage lower than VCH so that the subthreshold current can be ignored, and 0 V in an extreme case. Here, a certain voltage is PM
VCH- (0.4V
-VT). This is because the effective gate voltage obtained by subtracting VT from the gate-source voltage is required to be about 0.4 V in order to reduce the subthreshold current of the PMOS transistor to a negligible level. For example, in a 16 gigabit DRAM, VCH = 1.75V, VT = -0.04V as described above.
Therefore, the certain voltage referred to here is about 1.31V. When the common power supply line PB is raised to VCH after the gate voltage is fixed, the voltage of VCH is applied to the selected word line from the corresponding PMOS transistor. After applying for a desired period of time, when the gate voltage of the PMOS transistor is set to VCH in all word drivers, the selected word line is discharged to 0V by the corresponding NMOS transistor. After that, the voltage of the common power supply line PB is again lowered to a certain voltage or less. With such a driving method, there is a problem that the subthreshold current still continues to flow through the PMOS transistor of the non-selected word driver during the period when the VCH is applied to the common driving line, but in the other time zones. No external current flows. Even if the logic input of the driver is established after the required word voltage is applied to the common power supply line, a normal voltage can be obtained on the word line. In this case, the subthreshold current flows unnecessarily in all the word drivers during the period from the application of the word voltage to the power supply line to the establishment of the logical input of the driver. On the other hand, in the method in which the word voltage is applied to the common power supply line after the logic input is determined, the wasted current during this period can be reduced. However, the operation will be slightly slower. This is because the large parasitic capacitance of the common power supply line requires a long rise time in this portion, and the access time is delayed accordingly.

FIG. 12 and FIG. 13 are conceptual embodiments for solving the above-mentioned problems. The word driver group is divided into a large number of blocks composed of a plurality of drivers, and the subthreshold current is limited to only the selected block. There is a feature in doing it. That is, the current can be reduced in inverse proportion to the number of divisions. In FIG. 12, m blocks consisting of n word drivers are arranged one-dimensionally (where m · n =
In r), the subthreshold current can be reduced by 1 / m as compared with the embodiment shown in FIG. FIG. 13 shows a block consisting of l (lowercase L) word drivers as k.
Only (not the Boltzmann constant below) in the row direction,
Also, only j pieces are arranged two-dimensionally (matrix) in the column direction (where j · k · l = r). In this configuration,
The subthreshold current can be reduced by 1 / (j · k) as compared with the embodiment shown in FIG. The one-dimensional arrangement shown in FIG. 12 will be apparent from the description of the two-dimensional arrangement shown in FIG. 13. Therefore, the two-dimensional arrangement will be described in detail below with reference to some embodiments.

FIG. 14 shows an embodiment of a typical selection method of two-dimensional arrangement, and FIG. 15 is an operation timing chart thereof. The row line (PS) corresponding to the block to be selected, for example, B1,1
A required word voltage VCH is applied to 1), and 0V is applied to the corresponding column line (ΦB1). Block selection PMOS
The transistor Q1,1 is turned on, and the power supply line (P1,1) belonging to B1,1 is charged to VCH. Since the gate voltage of the PMOS transistor forming the word driver belonging to B1,1 has already been determined, VCH is applied to the word line selected accordingly. Of course, as described above, the word line can be normally driven even if the above-mentioned gate voltage is fixed after VCH is applied to P1,1. After being applied for the desired period of time, P11 is discharged to 0V with the NMOS transistor connected to it. The power supply line belonging to the non-selected block remains 0V. Here, for simplification, consider a case where the VT of the block selection PMOS transistor and the power supply line discharging NMOS transistor is selected sufficiently high (about 0.4 V). Since the power supply line of the non-selected block is always 0V, no subthreshold current flows in the word driver in the non-selected block. Therefore, the entire shoot-through current can be significantly reduced to a shoot-through current of only 1 word driver in the selected block.
Further, since the power supply line is divided and the divided power supply line having a small parasitic capacitance may be driven, it is possible to operate at a higher speed than in the embodiment shown in FIG.

FIG. 1 shows another embodiment of the two-dimensional arrangement selection method. Similar to the embodiment shown in FIG. 14, only the block at the intersection of the power supply line in the row (for example, PS1) and the control line in the column (for example, ΦB1) is selected. Differences from the embodiment shown in FIG. 4 are as follows. In FIG. 4, the voltage of the power supply line of each block in the unselected state is 0V, and all the power supply lines of the non-selected blocks are 0V even after the block selecting operation is started. When any one of the blocks is selected, the voltage of the power supply line has to be charged from 0 V to VCH, which has a drawback that the transient current is large at a low speed. To solve this, when a certain block changes from the non-selected state to the selected state, the voltage change of its power supply line is as small as possible, and the subthreshold current of other non-selected blocks is suppressed to a negligible level. Is desirable.

The embodiment shown in FIG. 1 realizes this, and has the following two features.

(1) Hierarchical power supply line in which drivers are divided into blocks: jk blocks each including 1 word driver are provided and arranged in a matrix. Divide them into k sectors to make j sectors. The power supply lines PB1 to PBk of each block are connected to the block selection transistor Q.
A power supply line (for example, PS
Connect to 1). In addition, the power supply lines PS1 to PS of each sector
j is connected to the power supply line P via the sector selection transistors QS1 to QSj. Further, P is connected to the power supply line of the word voltage VCH via the transistor Q which selects the operation mode and the standby mode.

(2) Hierarchical gate width setting: The gate width (d.multidot.W) of the block selection transistor is set to the total gate width (l.multidot.l) of the word driver transistors in the block.
Select sufficiently smaller than W) (d << l). In addition, the gate width (e.multidot.W) of the sector selection transistor is equal to the total gate width (k.multidot.k) of the block selection transistors in the sector.
Select sufficiently smaller than (d · W) (e << k · d).
Further, the gate width (f · W) of Q is selected sufficiently smaller than the total gate width (j · e · W) of all sector selection transistors (f << j · e).

In operation, Q, QS1 and QB1 are turned on, and block B including the selected word driver (# 1) is turned on.
The VCH is supplied to the power supply lines PB1 and PS1 corresponding to the sector S1 including 1 and B1. Here, the VT of all transistors is assumed to be the same low value.

With this configuration, unselected sectors (S2 to S
The total through current of each j) is equal to the subthreshold current of one corresponding sector selection transistor (QS2 to QSj). The through current of each of the non-selected blocks (B2 to Bk) in the selected sector (S1) is determined by the corresponding block selection transistor (QB2 to QBk) 1.
Is equal to the sub-threshold current. Because
Since the subthreshold current is proportional to the gate width of the transistor, for example, suppose that l.
This is because, even if the current of i attempts to flow, the overall through current is eventually limited to the subthreshold current (d · i) of the block selection transistor. Therefore, as shown in Table 1, the total through current IA is approximately (l + k · d +
j · e) i. In order to reduce IA, it is preferable to set l and (k · d) and (j · e) to the same value. Here, if d, e, and f are set to about 4, the influence on the speed of the series transistors (Q, QS1, QB1) and the chip area can be reduced.

For example, during standby, all of Q and Q1 to Qk are turned off. Overall through current IS is Q
Is equal to the subthreshold current of
It can be reduced by / j · k · l. The voltage of the power supply line of the block is lowered from VCH by ΔV determined by the ratio of j · k · l · W and f · W and the tailing coefficient, as shown in FIG.

Table 1 shows 16 Gbit D as a numerical example.
The current value obtained assuming the RAM is also shown. The parameter used therefor is that the threshold voltage VT defined by the voltage at which a current of 10 nA flows with a gate width of 5 μm is −0.12.
V, tailing coefficient S is 97 mV / dec. , The junction temperature T is 75 ° C., the effective gate length Leff is 0.15 μm, the gate oxide film thickness TOX is 4 nm, and the word voltage VCH is 1.
75V, power supply voltage VCC is 1V. According to the invention,
The subthreshold current is about 700mA from the conventional value, about 1/350 to about 2mA during operation, and about 3mA during standby.
It can be reduced to about 20 μA, which is 1/3000.

[0039]

[Table 1]

FIG. 3 is a schematic diagram of operation waveforms. During standby (Φ, ΦS1 to ΦSj, ΦB1 to ΦBk: VCH), P is a voltage VC lower than VCH because Q and QS1 to QSj and QB1 to QBk are almost off.
H-ΔV ″, PS1 to PSj have a lower voltage VCH-ΔV ′, and PB1 to PBk have a lower voltage VCH-ΔV. All word lines have PB1 to PBk. It is fixed to VSS irrespective of the voltage.When the external clock signal / RAS (here, "/" indicates a bar signal) is turned on, Q is first turned on by Φ, and the parasitic capacitance C of P is t1 time. Charge to VCH.
Next, QS1 is turned on at ΦS1, and the parasitic capacitance CS1 of PS1 is charged to VCH for t2 hours. Also, QB1 is turned on at ΦB1, and the parasitic capacitance CB1 of PB1 is charged to VCH for t3 hours. At this time, QS2 to QSj and QB2 to QBk remain almost off. afterwards,
The word driver # 1 is selected by the X decoder output signal X1 to drive the word line. When / RAS turns off, Q, QS1 and QB1 turn off. P, PS1,
After a long time has passed, PB1 is VCH-Δ
V ″, VCH−ΔV ′, VCH−ΔV. Here,
The feed line (P, P1) can be charged to VCH without impairing the access time. Because even if C is large, ΔV ”
Is as small as several hundred mV, and moreover, the charging time (t1) of P can be sufficiently obtained immediately after / RAS is turned on.
Also, since it is divided into sectors and blocks, CS1,
This is because the charging time (t2, t3) of PS1 and PB1 can be shortened because CB1 is relatively small.

In the above description, the connection of the transistor substrate (substrate) was not mentioned, but it is desirable to connect all the substrate of the PMOS transistor to VCH. In that case, the charge required for charging the power supply line is smaller and the charging time is shorter than when the substrate is also connected to the power supply line connecting the drain. As described above, when the power supply line of the non-selected block drops from VCH by ΔV,
This is because the substrate bias effect increases the threshold voltage of the PMOS transistor in the non-selected block. Since the voltage of the source is lower than that of the gate and the threshold voltage is higher, the same current reduction effect can be obtained with a smaller ΔV as compared with the case where the substrate has the same voltage as the drain.

The word voltage VCH is the power supply voltage VCC.
Since the voltage is boosted from, the voltage having a larger amplitude than the other circuits is input to the gate of the MOS transistor of the word driver. Therefore, the VT can be increased by that amount to further reduce the current. However, there is a drawback that the operation speed is slightly slow.

This drawback is mitigated by lowering the threshold voltage of the transistor in the word driver and raising the threshold voltage of the transistor used as a switch higher than that. For example, by setting the threshold voltages of Q and QS1 to QSj and QB1 to QBk in FIG. 1 to be higher than the transistors in the word driver and setting d, e, and f to be large, the operating speed is deteriorated due to the ON resistance of the switch. It is possible to further reduce the through current while preventing this. This is because the off-threshold current is affected exponentially, whereas the on-resistance is affected only by a linear function. Even if the gate capacitance increases with the gate width, if the charging times t1, t2, t3 in FIG. 3 can be secured, there is no problem in terms of operating speed. Therefore, the shoot-through current can be further reduced without deteriorating the operating speed. In terms of layout area, there is no problem because the number is relatively small. In some cases, using a transistor having a high threshold voltage only for Q is effective in reducing the standby current.

In this embodiment, one PM is used as a switch.
Although an OS transistor is used, other various elements or circuits are conceivable within a range satisfying the following two conditions. (1) When a switch is selected: When it is assumed that the switch is short-circuited, the operating current (subthreshold current and selected current) that flows in the load of the switch (eg, 1 word driver in the block selection switch) The current driving capability of the switch is larger than the charge current of the word line). (2) When the switch is not selected: The current supply capability of the switch is smaller than the standby current (subthreshold current) that flows in the load when the switch is assumed to be short-circuited. It suffices if the impedance can be made variable to be small and large at the time of selection and at the time of non-selection so as to satisfy these two conditions.

In the operation shown in FIG. 3, during the active period when / RAS is 0V, Φ, ΦS1 and ΦB1 are kept low and Q, QS1 and QB1 are kept on.
This is because Φ is controlled by the signal generated by / RAS that specifies the operating mode at the time of activation and standby, and ΦS1 and ΦB1 are controlled by the combined signal of the signal and the address signal.
It is realized by controlling. Further, after the word line is driven, Φ, ΦS1, and ΦS1, using a signal that specifies the period from the fall of / RAS to the end of driving the word line.
It is also possible to set ΦB1 to VCH and turn off Q, QS1, and QB1. As a result, the through current after driving the word line can be reduced to the same level as the standby current IS even during activation. This effect is greater as the active period in which / RAS is 0V is longer. However, in this case, in order to rewrite the memory cell, a certain period from the rise of / RAS,
It is necessary to lower Φ, ΦS1, ΦB1 and turn on Q, QS1, QB1.

FIG. 4 shows an example in which 512 word drivers are divided into 4 blocks. 512 per data line pair
5 memory cells (MC1 to MC512) are provided.
It is selected by 12 word lines. In order to arrange the memory cells at a high density, the line width and spacing of the word lines are about the same as the minimum processing size. Therefore, the word drivers cannot be laid out at the same pitch as the word lines, and are generally laid out in four stages. Each stage on the layout is used as it is as a block of the word driver (B1 to B
4) is shown in FIG. 4, and the layout area is not increased by separating the feed line of each block. Thus, the value of l can be made smaller than the number of memory cells per data line. On the contrary, it is obvious that it can be increased, and the degree of freedom of the value of l is large. Therefore, l and (k · d) and (j · e) can be set so that the through current IA during operation becomes the smallest.

Although the embodiment in which the present invention is applied to the word driver has been described above, the present invention is applied to the word driver.
It is not limited to this. The following modifications are possible.

FIG. 5 shows an example in which the hierarchical feed line system of FIG. 1 is applied to a decoder. C of NAND circuit and inverter
This is an example of an AND circuit composed of two stages of MOS logic circuits, and is characterized by using hierarchical feed lines on both sides of VCC and VSS. All NAND circuits are V
CC is output, and a small number outputs 0V during operation. The through current is determined by the NMOS transistor on the VSS side, so V
A hierarchical feed line is used on the SS side. On the other hand, the inverter outputs 0V during standby, and a small number of
Output CC. Since the through current is determined by the PMOS transistor, a hierarchical power supply line is used on the VCC side. As described above, by using the hierarchical feed lines on both sides of VCC and VSS, it is possible to reduce the shoot-through current without destabilizing the operation even in a multi-stage logic circuit. Note that any of the methods shown in FIGS. 10 to 15 can be similarly applied to a multistage circuit such as a decoder.

VCC / 2 like a sense amplifier drive circuit
Even in a circuit that operates mainly on the basis of the above, by applying the present invention to both sides of VCC and VSS, the through current can be reduced.
The present invention can be applied to any circuit group that outputs the same voltage during standby and operates a small number during operation. At that time, it is not necessary that all the circuits have the same transistor size, and the configurations may be different. Further, the number of circuits in a block and the number of blocks in a sector may be different.

When a plurality of circuits operate simultaneously, a plurality of circuits may be operated within one block, or a plurality of blocks may be selected at the same time. Further, the transistor which operates as a switch may be divided into a plurality of parts and arranged. In that case, you can reduce the effect of wiring resistance by shortening the power supply line,
The power supply line of the selected block can be charged in a short time.

The present invention can be applied not only to a DRAM but also to a memory such as a static random access memory (SRAM), a read only memory (ROM) or a flash memory, and a logic LSI having a built-in memory. It can also be applied to logic circuits other than CMOS, such as NMOS logic circuits. The present invention is more effective as the threshold voltage becomes smaller, and the LS having a threshold voltage of about 0.4 V or less, in which the through current becomes dominant in the operating current.
In I, the effect is remarkable. In particular, if the operating voltage is about 2 V or less, a threshold voltage of about 0.2 V is required from the viewpoint of operating speed, or if the gate length is about 0.2 μm or less, the threshold voltage is about 0.2 V due to the scaling rule.
Such an LSI is very effective, and battery operation is possible for the first time.

[0052]

As is apparent from the embodiments described above,
According to the present invention, a through current can be reduced without impairing the operation speed, and a semiconductor device that operates at high speed with low power consumption can be realized.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment applied to a word driver.

FIG. 2 is a diagram showing operating points of PMOS transistors of a word driver.

3 is an operation timing chart of the embodiment shown in FIG.

FIG. 4 is a diagram showing an example in which 512 word drivers are divided into 4 blocks.

FIG. 5 is an embodiment applied to a decoder.

FIG. 6 is a circuit diagram of a conventional CMOS inverter.

FIG. 7 is a diagram showing a subthreshold characteristic of a transistor.

FIG. 8 is a block diagram of a memory.

FIG. 9 is a diagram showing a conventional power supply line of a word driver.

FIG. 10 is a diagram showing an example in which the time during which a subthreshold current flows is limited.

FIG. 11 is a control timing chart of the embodiment shown in FIG.

FIG. 12 is a diagram showing an embodiment in which blocks are one-dimensionally arranged.

FIG. 13 is a diagram showing an embodiment in which blocks are arranged two-dimensionally.

FIG. 14 is an example of a typical selection method for a two-dimensional arrangement.

15 is a control timing diagram of the embodiment shown in FIG.

[Explanation of symbols]

WD ... Word driver, WL ... Word line, XDEC ... X
Decoder, D ... Data line, SA ... Sense amplifier, YDE
C ... Y decoder, SAD ... Sense amplifier drive circuit, MC
... memory cell, MA ... memory array, PR ... peripheral circuit,
VCH ... Word voltage, VCC ... Power supply voltage, VSS ... Ground voltage (0V), S1 to Sj ... Sectors, B1 to Bk ... Blocks, j ... Number of sectors, k ... Number of blocks per sector, l ... One block Number of circuits per unit, P ... Power supply line, Q
... Transistor for selecting operating mode and standby mode, P
S1 to PSk ... Sector power supply lines, QS1 to QSj ... Sector selection transistors, PB1 to PBk ... Block power supply lines, QB1 to QBk ... Block selection transistors.

Claims (17)

[Claims] 1. A plurality of row lines, a plurality of column lines intersecting the plurality of row lines, and a plurality of memory cells arranged at desired intersections of the plurality of row lines and the plurality of column lines. In a semiconductor integrated device having a selection circuit for selecting the memory cell, the selection circuit is supplied with first and second nodes to which a first operating voltage is supplied and a second operating voltage. Third and fourth nodes, a first logic gate group connected between the first node and the third node, and between the second node and the fourth node A second logic gate group connected, a third logic gate group connected between the first node and the third node, a second node and the fourth node A fourth logic gate group connected between the first logic gate group and the first logic gate group; A first current limiting means connected between the second logic gate group and the fourth node, and a third current limiting means connected between the second logic gate group and the fourth node. And a third current limiting means connected between the first logic node and the first node, and a fourth current limiting means connected between the fourth logic gate group and the fourth node. Each output of the first logic gate group is connected to each input of the second logic gate group, and each output of the third logic gate group is connected to each input of the fourth logic gate group. In the first state, at least one logic gate of the first logic gate group is connected to the first node through the first current limiting means between its output and the first node. A path is formed and at least one logic gate of the second logic gate group is formed. The gate forms a second current path between its output and the fourth node via the second current limiting means, and in the second state, each logic of the first logic gate group. The gate forms a third current path between its output and the third node and each logic gate of the second logic gate group has a fourth current path between its output and the second node. A current path is formed, and the first current limiting means makes the current allowable amount of the current flowing between the first node and the first logic gate group smaller than that in the first state. The second current limiting means limits the current allowable amount of the current flowing between the fourth node and the second logic gate group to be smaller than that in the first state. In the state of, at least one logic gate of the third logic gate group is A fifth current path is formed between the output and the first node via the third current limiting means, and at least one logic gate of the fourth logic gate group has its output and the A sixth current path is formed between the third logic gate group and the fourth node through the fourth current limiting means, and in the fourth state, each logic gate of the third logic gate group outputs its output and the third logic gate. Forming a seventh current path with the node and the logic gate of the fourth logic gate group forms an eighth current path between its output and the second node, and The third current limiting means limits the current allowable amount of the current flowing between the first node and the third logic gate group to be smaller than that in the third state, and the fourth current limiting means. The limiting means is located above the fourth node as compared with the third state. The current allowable amount of the current flowing between the third logic gate group and the fourth logic gate group is limited to a small value, and when the first and second logic gate groups are in the first state, the third and fourth logic gate groups are A semiconductor integrated circuit which is in the fourth state. 2. The semiconductor integrated circuit according to claim 1, wherein the first operating voltage is supplied to the first node.
A power supply line and a second power supply for supplying the second operating voltage to the first node
A power supply line; a first main current limiting means provided between the first power supply line and the first node; a second main power supply line provided between the second power supply line and the fourth node; 2 main current limiting means, and in the first state or the third state, the first operating voltage is supplied to the first node through the first main current limiting means. The semiconductor integrated circuit is characterized in that the second operating voltage is supplied to the fourth node through the second main current limiting means. 3. The semiconductor integrated circuit according to claim 2, wherein the fifth and sixth nodes are supplied with the first operating voltage, and the seventh and eighth nodes are supplied with the second operating voltage. Node, a fifth logic gate group connected between the fifth node and the seventh node, and a sixth logic gate group connected between the sixth node and the eighth node. Between the fifth logic gate group, the fifth current gate means connected between the fifth logic gate group and the fifth node, and between the sixth logic gate group and the eighth node. A sixth current limiting means connected to the first power supply line, a third main current limiting means provided between the first power supply line and the fifth node, the second power supply line and the eighth power supply line. A semiconductor integrated circuit further comprising a fourth main current limiting unit provided between the nodes. 4. The semiconductor integrated circuit according to claim 1, wherein the first current limiting means has a source connected to the first node and a drain connected to the first logic gate group. And a second MOS transistor whose source is connected to the fourth node and whose drain is connected to the second logic gate group. And a semiconductor integrated circuit. 5. The semiconductor integrated circuit according to claim 4, wherein the absolute value of the threshold voltage of the first MOS transistor and the absolute value of the threshold voltage of the second MOS transistor are the same as those of the first integrated circuit. And larger than the absolute value of the threshold voltage of the MOS transistor included in each of the second logic gate group, where the threshold voltage is when the ratio of the gate width to the effective gate length is 5 / 0.15. A semiconductor integrated circuit having a constant current threshold voltage defined by a gate-source voltage at which a drain current of 10 nA flows. 6. The semiconductor integrated circuit according to claim 4 or 5, wherein the first MOS transistor and the second MOS transistor have complementary polarities. . 7. The semiconductor integrated circuit according to claim 1, wherein each of the first and second logic gates is composed of a CMOS logic gate. 8. The semiconductor integrated circuit according to claim 7, wherein the first logic gate has multiple inputs and one output. 9. The semiconductor integrated circuit according to claim 8, wherein the first logic gate is a NAND gate. 10. The semiconductor integrated circuit according to claim 7, wherein the second logic gate is an inverter. 11. The semiconductor integrated circuit according to claim 1, wherein the number of the plurality of memory cells is 16 giga. 12. The semiconductor integrated circuit according to claim 1, wherein each of the first logic gate and the second logic gate has a gate voltage from a first voltage to a second voltage. , The drain current becomes larger when the gate voltage is the second voltage than when the gate voltage is the first voltage, and the gate voltage is the first voltage. A semiconductor integrated circuit including a MOS transistor in which a through current substantially flows between a drain and a source at any time. 13. The semiconductor integrated circuit according to claim 12, wherein a threshold voltage of each of the MOS transistors of the first logic gate and the second logic gate is 0.2.
The threshold voltage is equal to or lower than V, and the threshold voltage is a threshold voltage defined by a gate-source voltage at which a drain current of 10 nA flows when the ratio of the gate width to the effective gate length is 5 / 0.15. A semiconductor integrated circuit characterized by the above. 14. The semiconductor integrated circuit according to claim 12, wherein a gate oxide film thickness of each of the MOS transistors of the first logic gate and the second logic gate is 4n.
A semiconductor integrated circuit characterized by being m. 15. The semiconductor integrated circuit according to claim 12, wherein a gate length of each of the MOS transistors of the first logic gate and the second logic gate is 0.2 μm.
A semiconductor integrated circuit characterized by the following: 16. The semiconductor integrated circuit according to claim 1, wherein an absolute value of a power supply voltage applied from outside is 2 volts or less. 17. The semiconductor integrated circuit according to claim 1, wherein a voltage difference between the first voltage and the second voltage is 2 volts or less.