JPH09205178A - Semiconductor device and its manufacture - Google Patents
Semiconductor device and its manufactureInfo
- Publication number
- JPH09205178A JPH09205178A JP1168796A JP1168796A JPH09205178A JP H09205178 A JPH09205178 A JP H09205178A JP 1168796 A JP1168796 A JP 1168796A JP 1168796 A JP1168796 A JP 1168796A JP H09205178 A JPH09205178 A JP H09205178A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- upper layer
- spiral inductor
- polyimide resin
- lower layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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- Semiconductor Integrated Circuits (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体装置、特にＧ
ａＡｓ基板を用いたモノリシックマイクロ波集積回路の
半導体装置とその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, particularly G
The present invention relates to a semiconductor device of a monolithic microwave integrated circuit using an aAs substrate and a manufacturing method thereof.
【０００２】[0002]
【従来の技術】従来例としてメタル・インシュレータ・
メタルキャパシタ（以下、ＭＩＭキャパシタと記す。）
上にスパイラルインダクタを積層する構造が、特開平６
−１６９０６４号公報に示されている。同公報に記載の
半導体装置を図７に示す。従来の半導体装置は、半絶縁
性のＧａＡｓ基板表面に下層電極、キャパシタ絶縁膜、
上層電極からなるＭＩＭキャパシタを形成し、その上に
絶縁膜を積層し、その絶縁膜上にスパイラルインダクタ
を形成している。図中に示すバイアホールは、基板表面
のＭＩＭキャパシタと裏面メタルとを接続する役割を果
たす。又、半導体抵抗、金属抵抗は、整合回路やＦＥＴ
間結合回路として用いている。2. Description of the Related Art As a conventional example, a metal insulator
Metal capacitor (hereinafter referred to as MIM capacitor)
A structure in which a spiral inductor is laminated on top is disclosed in Japanese Patent Laid-Open No.
No. 1669064. FIG. 7 shows the semiconductor device described in the publication. Conventional semiconductor devices consist of a semi-insulating GaAs substrate surface with a lower electrode, a capacitor insulating film,
An MIM capacitor composed of an upper layer electrode is formed, an insulating film is laminated on the MIM capacitor, and a spiral inductor is formed on the insulating film. The via hole shown in the figure plays a role of connecting the MIM capacitor on the front surface of the substrate to the back surface metal. Also, semiconductor resistors and metal resistors are used for matching circuits and FETs.
It is used as an inter-coupling circuit.
【０００３】[0003]
【発明が解決しようとする課題】従来の半導体装置で
は、ＭＩＭキャパシタとスパイラルインダクタの間の絶
縁膜の厚さは、通常１μｍ程度であり、ＭＩＭキャパシ
タの上部電極とスパイラルインダクタとの距離が狭く、
スパイラルインダクタは十分なインダクタンスを得るこ
とが難しい。十分なインダクタンスを得るために絶縁膜
を厚くすると、絶縁膜が剥離し易い、あるいは絶縁膜に
クラックが入り易い等の問題が生じ、実用的ではない。In the conventional semiconductor device, the thickness of the insulating film between the MIM capacitor and the spiral inductor is usually about 1 μm, and the distance between the upper electrode of the MIM capacitor and the spiral inductor is narrow,
It is difficult for a spiral inductor to obtain sufficient inductance. If the insulating film is thickened to obtain a sufficient inductance, problems such as easy peeling of the insulating film and easy cracking of the insulating film occur, which are not practical.
【０００４】更に、スパイラルインダクタ配線間の底部
に存在する絶縁膜が容量成分となり、スパイラルインダ
クタ配線間の電磁気結合が強くなり、十分なインダクタ
ンスを得ることが難しい。Furthermore, the insulating film existing at the bottom between the spiral inductor wires serves as a capacitance component, the electromagnetic coupling between the spiral inductor wires is strengthened, and it is difficult to obtain a sufficient inductance.
【０００５】インダクタンスが十分に得られないこと
は、共振周波数が低くなり、マイクロ波帯の周波数領域
での使用が難しくなるという問題があった。If the inductance is not sufficiently obtained, there is a problem that the resonance frequency becomes low and it becomes difficult to use in the microwave frequency range.
【０００６】また、上部層の素子がスパイラルインダク
タの時に限らず、上部層の素子と下部層の素子が近いこ
とはクロストークの作用が働き、素子の特性を悪化させ
るという問題もあった。Further, not only when the element of the upper layer is a spiral inductor, but when the element of the upper layer and the element of the lower layer are close to each other, there is a problem that the action of crosstalk works and the characteristics of the element are deteriorated.
【０００７】本発明の目的は、上記問題点を解決する半
導体装置とその製造方法を提供することである。An object of the present invention is to provide a semiconductor device and a method of manufacturing the same which solve the above problems.
【０００８】[0008]
【課題を解決するための手段】本発明に係る半導体装置
は、能動素子及び受動素子を備え、前記能動素子及び受
動素子から任意のものを複数個組み合わせて、これらを
積層するマイクロ波集積回路の半導体装置において、能
動素子あるいは受動素子が形成された下部層を有し、
受動素子が形成された上部層を有し、該上部層を支持す
る支持部材を前記下部層の上に有し、前記下部層と前記
上部層の間に中空を有することを特徴とする。A semiconductor device according to the present invention is provided with an active element and a passive element, and a plurality of arbitrary active elements and passive elements are combined and laminated in a microwave integrated circuit. In a semiconductor device, having a lower layer on which an active element or a passive element is formed,
It is characterized in that it has an upper layer on which a passive element is formed, a support member for supporting the upper layer is provided on the lower layer, and a hollow is provided between the lower layer and the upper layer.
【０００９】本発明に係る半導体装置は上部層の上に、
更に別の上部層を支持するための支持部材を有し、受動
素子が形成された前記別の上部層を有し、該別の上部層
と前記上部層との間に中空領域を有する多層構造を特徴
とする。The semiconductor device according to the present invention comprises:
A multi-layer structure having a support member for supporting another upper layer, having the other upper layer on which a passive element is formed, and having a hollow region between the other upper layer and the upper layer. Is characterized by.
【００１０】本発明に係る請求項１〜３の半導体装置の
製造方法は、能動素子あるいは受動素子が形成された下
部層の上に、支持部材を形成する工程と、該支持部材の
高さまで樹脂にて埋め込む工程と、前記支持部材及び前
記樹脂の上に受動素子が形成された上部層を作製する工
程と、前記樹脂を除去し、前記支持部材を残存させる工
程とを有することを特徴とする。The method for manufacturing a semiconductor device according to claims 1 to 3 according to the present invention comprises a step of forming a support member on a lower layer on which an active element or a passive element is formed, and a resin up to the height of the support member. And a step of forming an upper layer in which a passive element is formed on the support member and the resin, and a step of removing the resin and leaving the support member. .
【００１１】[0011]
（実施の形態１）本発明の実施の形態１として、半絶縁
性ＧａＡｓ基板表面に形成されたＭＥＳＦＥＴ（Ｍｅｔ
ａｌ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ Ｆｉｅｌｄ Ｅｆ
ｆｅｃｔＴｒａｎｓｉｓｉｔｏｒ）上にスパイラルイン
ダクタを積層した例を図１に示す。(Embodiment 1) As Embodiment 1 of the present invention, a MESFET (Met) formed on the surface of a semi-insulating GaAs substrate.
al Semiconductor Field Ef
FIG. 1 shows an example in which a spiral inductor is stacked on the (FactTransistor).
【００１２】まず、通常のＧａＡｓ系ＭＥＳＦＥＴのプ
ロセスにて半絶縁性ＧａＡｓ基板１にＭＥＳＦＥＴ２を
形成する。ここで、３はソース、ドレイン及びチャネル
の不純物層、４ａはソース電極、４ｂはドレイン電極、
５はゲート電極、６は表面保護用の絶縁膜である。この
構造の表面に絶縁膜としてポリイミド樹脂７を回転塗布
法により均一に５μｍ程度積層する。以上の工程終了後
の半導体装置の断面図を図１（ａ）に示す。First, the MESFET 2 is formed on the semi-insulating GaAs substrate 1 by a normal GaAs MESFET process. Here, 3 is a source, drain and channel impurity layer, 4a is a source electrode, 4b is a drain electrode,
Reference numeral 5 is a gate electrode, and 6 is an insulating film for surface protection. Polyimide resin 7 is uniformly laminated on the surface of this structure as an insulating film by a spin coating method to a thickness of about 5 μm. A cross-sectional view of the semiconductor device after the above steps are shown in FIG.
【００１３】次に、通常のフォトリソグラフィ法によっ
て、ポリイミド樹脂７の上にフォトレジストパターン８
を形成する。以上の工程終了後の半導体装置の断面図を
図１（ｂ）に示す。Next, a photoresist pattern 8 is formed on the polyimide resin 7 by a normal photolithography method.
To form A cross-sectional view of the semiconductor device after the above steps are shown in FIG.
【００１４】次に、フォトレジストパターン８をマスク
としてポリイミド樹脂７を反応性イオンエッチング法
（以下、ＲＩＥ法と記す）によって異方性エッチングを
行い、支持部材として複数のポリイミド樹脂の柱７ａを
形成する。ここで、ポリイミド樹脂の柱７ａの間隔は５
０μｍとした。以上の工程終了後の半導体装置の断面図
を図１（ｃ）に示す。異方性エッチングが行えるエッチ
ング方法であれば、他の電子サイクロトロンエッチング
法等でも構わない。Next, using the photoresist pattern 8 as a mask, the polyimide resin 7 is anisotropically etched by a reactive ion etching method (hereinafter referred to as RIE method) to form a plurality of polyimide resin columns 7a as supporting members. To do. Here, the distance between the pillars 7a of polyimide resin is 5
It was set to 0 μm. A cross-sectional view of the semiconductor device after the above steps are shown in FIG. Other electron cyclotron etching methods or the like may be used as long as they are anisotropic etching methods.
【００１５】図１（ｃ）に示される構造の表面全面にフ
ォトレジスト９を回転塗布法により、均一に塗布を行
い、ポリイミド樹脂の柱７ａを完全に埋めこんで平坦化
する。以上の工程終了後の半導体装置の断面図を図１
（ｄ）に示す。Photoresist 9 is uniformly applied to the entire surface of the structure shown in FIG. 1 (c) by a spin coating method, and the pillars 7a of polyimide resin are completely embedded and planarized. FIG. 1 is a sectional view of the semiconductor device after the above steps are completed.
It shows in (d).
【００１６】次に、埋め込み平坦化に用いたフォトレジ
スト９をＲＩＥ法によってエッチバックを行い、ポリイ
ミド樹脂の柱７ａの表面が露出するまで、エッチングを
行う。以上の工程終了後の半導体装置の断面図を図１
（ｅ）に示す。Next, the photoresist 9 used for the buried flattening is etched back by the RIE method, and is etched until the surface of the pillar 7a of the polyimide resin is exposed. FIG. 1 is a sectional view of the semiconductor device after the above steps are completed.
(E).
【００１７】次に、スパイラルインダクタの配線用のフ
ォトレジストパターン１０を形成する。以上の工程終了
後の半導体装置の断面図を図１（ｆ）に示す。尚、図示
はしていないがＭＥＳＦＥＴとスパイラルインダクタを
接続する方法は、この工程においてフォトレジスト９と
保護膜６にコンタクトホールをあけることで行う。Next, a photoresist pattern 10 for wiring the spiral inductor is formed. A cross-sectional view of the semiconductor device after the above steps are shown in FIG. Although not shown, the method of connecting the MESFET and the spiral inductor is performed by making contact holes in the photoresist 9 and the protective film 6 in this step.
【００１８】次に、スパイラルインダクタの配線用の金
属膜１１を蒸着法により全面に約２μｍ成膜する。以上
の工程終了後の半導体装置の断面図を図１（ｇ）に示
す。Next, a metal film 11 for wiring the spiral inductor is formed on the entire surface by vapor deposition to a thickness of about 2 μm. A cross-sectional view of the semiconductor device after the above steps are shown in FIG.
【００１９】最後に、埋め込み平坦化に使用したフォト
レジスト９と配線用のフォトレジストパターン１０を有
機溶剤で溶解し、ポリイミド樹脂の柱７ａを残存させ、
フォトレジストパターン１０上の金属膜をリフトオフす
ることで、ポリイミド樹脂の柱７ａの支柱の上にスパイ
ラルインダクタの金属配線１１ａを形成する。以上の工
程終了後の半導体装置の断面図を図１（ｈ）に示す。ま
た、この半導体装置のの斜視図を図１（ｉ）に示す。Finally, the photoresist 9 used for the filling and planarization and the photoresist pattern 10 for wiring are dissolved with an organic solvent to leave the pillars 7a of polyimide resin.
By lifting off the metal film on the photoresist pattern 10, the metal wiring 11a of the spiral inductor is formed on the pillar of the polyimide resin pillar 7a. A sectional view of the semiconductor device after the above steps are shown in FIG. A perspective view of this semiconductor device is shown in FIG.
【００２０】本発明の半導体装置の構造では、ＭＥＳＦ
ＥＴとスパイラルインダクタとの間に中空を有するので
高い放熱効果が得られる。In the structure of the semiconductor device of the present invention, the MESF
Since there is a hollow between the ET and the spiral inductor, a high heat dissipation effect can be obtained.
【００２１】また、スパイラルインダクタの下は中空と
なっており、誘電率が低いので、十分なインダクタンス
を得ることができる。また、ポリイミドの樹脂の柱の高
さを変えるだけで、上部層の素子と下部層の素子との距
離を長くすることができ、スパイラルインダクタは十分
なインダクタンスを得ることができる。Further, since the spiral inductor is hollow below and has a low dielectric constant, a sufficient inductance can be obtained. In addition, the distance between the upper layer element and the lower layer element can be lengthened only by changing the height of the polyimide resin column, and the spiral inductor can obtain a sufficient inductance.
【００２２】（実施の形態２）本発明の実施の形態２と
して、半絶縁性ＧａＡｓ基板表面に形成されたＭＥＳＦ
ＥＴ上にスパイラルインダクタを２層積層した例を図２
に示す。(Embodiment 2) As Embodiment 2 of the present invention, MESF formed on the surface of a semi-insulating GaAs substrate.
An example of stacking two layers of spiral inductors on ET Fig. 2
Shown in
【００２３】まず、図１（ｈ）の工程まで実施例１と同
様に作製し、この構造の表面全面にフォトレジスト９を
回転塗布法により均一に塗布を行い、実施の形態１に記
載の半導体装置を完全に埋めこんで平坦化する。以上の
工程終了後の半導体装置の断面図を図２（ａ）に示す。First, the process up to the step of FIG. 1 (h) was prepared in the same manner as in Example 1, and the photoresist 9 was uniformly applied to the entire surface of this structure by the spin coating method, and the semiconductor described in Embodiment 1 was used. Fully embed the device and planarize. A cross-sectional view of the semiconductor device after the above steps are shown in FIG.
【００２４】次に、埋め込み平坦化に用いたフォトレジ
スト９をＲＩＥによってエッチバックを行い、第１のス
パイラルインダクタの金属配線１１ａの表面が露出する
まで、エッチングを行う。以上の工程終了後の半導体装
置の断面図を図２（ｂ）に示す。Next, the photoresist 9 used for the buried flattening is etched back by RIE, and is etched until the surface of the metal wiring 11a of the first spiral inductor is exposed. A cross-sectional view of the semiconductor device after the above steps are shown in FIG.
【００２５】これ以降、実施の形態１の図１（ａ）〜
（ｈ）と同様の製造方法にて、第２のスパイラルインダ
クタを絶縁体の柱上に作製する。これらの工程の半導体
装置の断面図を図２（ｃ）〜（ｈ）に示す。After this, FIG. 1A of the first embodiment will be described.
The second spiral inductor is manufactured on the pillar of the insulator by the same manufacturing method as in (h). 2C to 2H are sectional views of the semiconductor device in these steps.
【００２６】以上の工程にて、半絶縁性ＧａＡｓ基板表
面に形成されたＭＥＳＦＥＴ上にスパイラルインダクタ
を２層積層した半導体装置を作製できる。また、この半
導体装置の斜視図を図２（ｉ）に示す。Through the above steps, a semiconductor device in which two layers of spiral inductors are laminated on the MESFET formed on the surface of the semi-insulating GaAs substrate can be manufactured. A perspective view of this semiconductor device is shown in FIG.
【００２７】本実施の形態のように、本発明の製造方法
で多層に積層することができる。As in the present embodiment, it can be laminated in multiple layers by the manufacturing method of the present invention.
【００２８】また、第２のスパイラルインダクタは、実
施の形態１と同様にコンタクトホールをあけることでＭ
ＥＳＦＥＴや第１のスパイラルインダクタと接続を行
う。Further, the second spiral inductor is formed by forming a contact hole as in the first embodiment.
Connect with ESFET and the first spiral inductor.
【００２９】（実施の形態３）本発明の実施の形態３と
して、半絶縁性ＧａＡｓ基板表面に形成されたＭＥＳＦ
ＥＴ上にＭＩＭキャパシタを積層した例を図３に示す。(Embodiment 3) As Embodiment 3 of the present invention, MESF formed on the surface of a semi-insulating GaAs substrate.
An example of stacking the MIM capacitor on the ET is shown in FIG.
【００３０】まず、実施の形態１の図１（ａ）〜図１
（ｈ）の工程と同様に作製する。ただし、図１（ｆ）に
示される配線用のフォトレジストパターン１０の代わり
にＭＩＭキャパシタの下層電極形成用のフォトレジスト
パターンとし、スパイラルインダクタとしての金属膜１
１の代わりにＭＩＭキャパシタの下層電極用の金属膜１
２とする。以上の工程終了後の半導体装置の断面図を図
３（ａ）に示す。First, FIG. 1A to FIG. 1 of the first embodiment.
It is produced in the same manner as the step (h). However, instead of the photoresist pattern 10 for wiring shown in FIG. 1F, a photoresist pattern for forming the lower layer electrode of the MIM capacitor is used, and the metal film 1 as the spiral inductor is used.
Metal film 1 for lower electrode of MIM capacitor instead of 1
Let it be 2. A cross-sectional view of the semiconductor device after the above steps are shown in FIG.
【００３１】次に、この構造の表面全面にＭＩＭキャパ
シタの誘電膜としてＳＩＮ膜１３をプラズマＣＶＤによ
って成膜する。以上の工程終了後の半導体装置の断面図
を図３（ｂ）に示す。Next, a SIN film 13 is formed as a dielectric film of the MIM capacitor on the entire surface of this structure by plasma CVD. A cross-sectional view of the semiconductor device after the above steps are shown in FIG.
【００３２】次に、この構造を形成した側の表面全面に
フォトレジスト９を回転塗布法により均一に塗布を行
い、この工程までに作製された半導体装置を完全に埋め
込んで平坦化する。以上の工程終了後の半導体装置の断
面図を図３（ｃ）に示す。Next, a photoresist 9 is uniformly applied to the entire surface on the side where this structure is formed by a spin coating method, and the semiconductor device manufactured up to this step is completely embedded and planarized. A cross-sectional view of the semiconductor device after the above steps are shown in FIG.
【００３３】次に、埋め込み平坦化に用いたフォトレジ
スト９をＲＩＥによってエッチバックを行い、ＭＩＭキ
ャパシタの絶縁膜としてＳＩＮ膜１３の表面が露出する
まで、エッチングを行う。以上の工程終了後の半導体装
置の断面図を図３（ｄ）に示す。Next, the photoresist 9 used for the buried flattening is etched back by RIE, and is etched until the surface of the SIN film 13 is exposed as an insulating film of the MIM capacitor. A cross-sectional view of the semiconductor device after the above steps are shown in FIG.
【００３４】次に、ＭＩＭキャパシタの上部電極形成用
のフォトレジストパターン１４を形成する。以上の工程
終了後の半導体装置の断面図を図３（ｅ）に示す。Next, a photoresist pattern 14 for forming the upper electrode of the MIM capacitor is formed. A cross-sectional view of the semiconductor device after completion of the above steps is shown in FIG.
【００３５】次に、ＭＩＭキャパシタの上部電極用の金
属膜１５を蒸着法により全面に成膜する。以上の工程終
了後の半導体装置の断面図を図３（ｆ）に示す。Next, a metal film 15 for the upper electrode of the MIM capacitor is formed on the entire surface by vapor deposition. A cross-sectional view of the semiconductor device after the above steps are shown in FIG.
【００３６】最後に、埋め込み平坦化に使用したフォト
レジスト９とＭＩＭキャパシタの上部電極用のフォトレ
ジストパターン１４を有機溶剤で溶解し、ポリイミド樹
脂の柱７ａを残存させ、ＭＩＭキャパシタの上部電極用
のフォトレジストパターン１４上の金属膜１５をリフト
オフすることで、ＭＩＭキャパシタの上部電極の金属膜
１５ａが形成できる。以上の工程を経て、ポリイミド樹
脂の柱７ａを支柱としてＭＩＭキャパシタを積層した半
導体装置を作製した。実施の形態３で作製した半導体装
置の断面図を図３（ｇ）に示す。また、この半導体装置
の斜視図を図３（ｈ）に示す。Finally, the photoresist 9 used for the filling and planarization and the photoresist pattern 14 for the upper electrode of the MIM capacitor are dissolved with an organic solvent to leave the pillars 7a of the polyimide resin, and the upper electrode for the MIM capacitor is left. By lifting off the metal film 15 on the photoresist pattern 14, the metal film 15a of the upper electrode of the MIM capacitor can be formed. Through the above steps, a semiconductor device in which MIM capacitors are stacked using the polyimide resin pillars 7a as pillars is manufactured. A cross-sectional view of the semiconductor device manufactured in Embodiment Mode 3 is shown in FIG. A perspective view of this semiconductor device is shown in FIG.
【００３７】図示しないがＭＩＭキャパシタとＭＥＳＦ
ＥＴは、実施の形態１と同様にコンタクトホールをあけ
ることで接続を行う。Although not shown, MIM capacitor and MESF
The ET is connected by opening a contact hole as in the first embodiment.
【００３８】（実施の形態４）本発明の実施の形態４と
して、半絶縁性ＧａＡｓ基板表面に形成されたＭＥＳＦ
ＥＴ上にＭＩＭキャパシタを２層積層した例を図４、図
５に示す。(Embodiment 4) As Embodiment 4 of the present invention, MESF formed on the surface of a semi-insulating GaAs substrate.
An example in which two layers of MIM capacitors are laminated on the ET is shown in FIGS.
【００３９】まず、実施の形態３の図３（ｈ）までの工
程と同様に作製する。以上の工程終了後の半導体装置の
断面図を図４（ａ）に示す。First, the steps similar to those of the third embodiment up to FIG. A cross-sectional view of the semiconductor device after the above steps are shown in FIG.
【００４０】次に、実施の形態２の図２（ａ）〜（ｈ）
と同様な方法で作製する。ただし、実施の形態２でのス
パイラルインダクタの代わりに、実施の形態３に記載の
作製方法でＭＩＭキャパシタを作製する。それらの工程
における断面図を図４（ｂ）〜（ｊ）、図５（ｋ）〜
（ｍ）に示す。Next, FIGS. 2A to 2H of the second embodiment will be described.
It is manufactured by the same method as. However, instead of the spiral inductor in the second embodiment, the MIM capacitor is manufactured by the manufacturing method described in the third embodiment. Cross-sectional views in those steps are shown in FIGS.
It shows in (m).
【００４１】以上の工程終了後、半絶縁性ＧａＡｓ基板
表面に形成されたＭＥＳＦＥＴ上にＭＩＭキャパシタを
２層積層した半導体装置を作製できる。また、この半導
体装置の斜視図を図５（ｎ）に示す。After the above steps are completed, a semiconductor device in which two layers of MIM capacitors are laminated on the MESFET formed on the surface of the semi-insulating GaAs substrate can be manufactured. A perspective view of this semiconductor device is shown in FIG.
【００４２】（実施の形態５）本発明の実施の形態５と
して、半絶縁性ＧａＡｓ基板表面に形成されたＭＥＳＦ
ＥＴ上にＭＩＭキャパシタを積層し、更にその上にスパ
イラルインダクタを積層した例を図６に示す。(Embodiment 5) As Embodiment 5 of the present invention, a MESF formed on the surface of a semi-insulating GaAs substrate.
FIG. 6 shows an example in which the MIM capacitor is laminated on the ET and the spiral inductor is further laminated thereon.
【００４３】本実施の形態５の製造方法は、実施の形態
３の図３（ｈ）の工程までと同様に作製し、ＭＩＭキャ
パシタを積層した後、図２（ａ）〜（ｈ）と同様な方法
でＭＩＭキャパシタの上にスパイラルインダクタを形成
する。実施の形態５の半導体装置の製造工程の断面図は
図６（ａ）〜図６（ｊ）に示し、この半導体装置の斜視
図を図６（ｋ）に示す。The manufacturing method of the fifth embodiment is the same as the manufacturing method of the third embodiment up to the step of FIG. 3H, and after stacking the MIM capacitors, the same as the steps of FIGS. 2A to 2H. Forming a spiral inductor on the MIM capacitor by various methods. 6A to 6J are cross-sectional views of the manufacturing process of the semiconductor device according to the fifth embodiment, and FIG. 6K is a perspective view of the semiconductor device.
【００４４】本実施の形態では絶縁体の柱としてポリイ
ミド樹脂を用いたが、比較的低温で成膜できて、埋め込
み平坦化に使用するフォトレジスト９と配線用のフォト
レジスト１０、更にこれらの溶解させる有機溶剤に対し
て、耐溶解性を有する膜を選択するのであれば、例えば
ＳｉＮ膜、ＳｉＯ2膜、ＳｉＯＮ膜、ＰＳＧ膜、ＢＰＳ
Ｇ膜等を使用しても構わない。更に、整合回路として必
要なインダクタンスを得るために絶縁体の柱の誘電率は
低い方が望ましい。In this embodiment, the polyimide resin is used as the pillar of the insulator, but it is possible to form a film at a relatively low temperature. If a film having dissolution resistance is selected for the organic solvent to be used, for example, SiN film, SiO 2 film, SiON film, PSG film, BPS
A G film or the like may be used. Furthermore, in order to obtain the inductance required for the matching circuit, it is desirable that the dielectric pillar has a low dielectric constant.
【００４５】また、本実施例では、能動素子としてＭＥ
ＳＦＥＴを使用したが他のＨＥＭＴ（Ｈｉｇｈ Ｅｌｅ
ｃｔｒｏｎ Ｍｏｂｉｌｉｔｙ Ｔｒａｎｓｉｓｉｔｏ
ｒ）やＨＢＴ（Ｈｅｔｅｒｏ Ｂｉｐｏｌａｒ Ｔｒａ
ｎｓｉｓｉｔｏｒ）でも本発明の方法が適用できる。本
実施の形態では上部層に受動素子を形成し、一番下の下
部層にＭＥＳＦＥＴを形成した層を用いたが、下部層も
上部層も受動素子を形成した層でもかまわない。In this embodiment, the ME is used as the active element.
Although SFET was used, other HEMT (High Ele
ctron Mobility Transisito
r) and HBT (Hetero Bipolar Tra)
The method of the present invention can also be applied to the above. In this embodiment, a passive element is formed on the upper layer and a MESFET is formed on the lowermost layer, but the lower layer and the upper layer may be layers on which passive elements are formed.
【００４６】また、本実施の形態の積層構造ではＭＥＳ
ＦＥＴを形成した層の上に２層まで積層したが、本発明
の方法のくり返しによって更に３層、４層と重ねること
も可能である。そのため、３次元的にマイクロ波集積回
路が構成できるので回路構成の自由度が高くなる。In the laminated structure of this embodiment, the MES
Although up to two layers are stacked on the layer on which the FET is formed, it is possible to stack three or four layers by repeating the method of the present invention. Therefore, since the microwave integrated circuit can be configured three-dimensionally, the degree of freedom in circuit configuration is increased.
【００４７】[0047]
【発明の効果】本発明によれば、素子を形成した上部層
と下部層との間が中空であることからクロストークの影
響が少なく、良好な素子特性のまま立体的に積層するこ
とができる。そのため、半導体装置の小型化に寄与す
る。According to the present invention, since the space between the upper layer and the lower layer on which the element is formed is hollow, the influence of crosstalk is small, and it is possible to stack three-dimensionally with good element characteristics. . Therefore, it contributes to downsizing of the semiconductor device.
【００４８】特に、スパイラルインダクタを積層する際
には、十分なインダクタンスを得ることができる。In particular, a sufficient inductance can be obtained when stacking spiral inductors.
【００４９】また、素子を形成した上部層と下部層との
間に中空を有することは、放熱効果を高めることができ
る利点を有している。Further, having a hollow between the upper layer and the lower layer on which the element is formed has an advantage that the heat radiation effect can be enhanced.
【図１】本発明に係るＭＥＳＦＥＴの上にスパイラルイ
ンダクタを積層する半導体装置の製造工程を示す図であ
る。FIG. 1 is a diagram showing a manufacturing process of a semiconductor device in which a spiral inductor is stacked on a MESFET according to the present invention.
【図２】本発明に係るＭＥＳＦＥＴの上にスパイラルイ
ンダクタを２層積層する半導体装置の製造工程を示す図
である。FIG. 2 is a diagram showing a manufacturing process of a semiconductor device in which two layers of spiral inductors are laminated on a MESFET according to the present invention.
【図３】本発明に係るＭＥＳＦＥＴの上にＭＩＭキャパ
シタを積層する半導体装置の製造工程を示す図である。FIG. 3 is a diagram showing a manufacturing process of a semiconductor device in which an MIM capacitor is stacked on a MESFET according to the present invention.
【図４】本発明に係るＭＥＳＦＥＴの上にＭＩＭキャパ
シタを２層積層する半導体装置の製造工程を示す図であ
る。FIG. 4 is a diagram showing a manufacturing process of a semiconductor device in which two layers of MIM capacitors are laminated on a MESFET according to the present invention.
【図５】本発明に係るＭＥＳＦＥＴの上にＭＩＭキャパ
シタを２層積層する半導体装置の図４に示す工程から続
く製造工程を示す図である。FIG. 5 is a diagram showing a manufacturing process subsequent to the process shown in FIG. 4 of the semiconductor device in which two layers of MIM capacitors are laminated on the MESFET according to the present invention.
【図６】本発明に係るＭＥＳＦＥＴの上にＭＩＭキャパ
シタを積層し、その上にスパイラルインダクタを積層す
る半導体装置の製造工程を示す図である。FIG. 6 is a diagram showing a manufacturing process of a semiconductor device in which an MIM capacitor is laminated on a MESFET according to the present invention, and a spiral inductor is laminated thereon.
【図７】従来の半導体装置を示す図である。FIG. 7 is a diagram showing a conventional semiconductor device.
１ 半絶縁性のＧａＡｓ基板 ２ ＭＥＳＦＥＴ ３ ソース・ドレイン及びチャネルの不純物拡散層 ４ａ ソース電極 ４ｂ ドレイン電極 ５ ゲート電極 ６ 表面保護ための絶縁膜 ７ ポリイミド樹脂 ７ａ ポリイミド樹脂の柱 ８，１０，１４ フォトレジストパターン ９ フォトレジスト １１，１２，１５ 金属膜 １１ａ スパイラルインダクタの金属配線 １３ ＳｉＮ膜 １５ａ ＭＩＭキャパシタの上部電極 1 Semi-insulating GaAs substrate 2 MESFET 3 Source / drain and channel impurity diffusion layer 4a Source electrode 4b Drain electrode 5 Gate electrode 6 Insulating film for surface protection 7 Polyimide resin 7a Polyimide resin pillar 8, 10, 14 Photoresist Pattern 9 Photoresist 11, 12, 15 Metal film 11a Metal wiring of spiral inductor 13 SiN film 15a Upper electrode of MIM capacitor
Claims (4)
素子及び受動素子から任意のものを複数個組み合わせ
て、これらを積層するマイクロ波集積回路の半導体装置
において、 能動素子あるいは受動素子が形成された下部層を有し、 受動素子が形成された上部層を有し、 該上部層を支持する支持部材を前記下部層の上に有し、 前記下部層と前記上部層の間に中空領域を有することを
特徴とする半導体装置。1. A semiconductor device of a microwave integrated circuit, comprising an active element and a passive element, combining a plurality of arbitrary ones of the active element and the passive element, and laminating the active element and the passive element, wherein an active element or a passive element is formed. A lower layer, an upper layer having a passive element formed thereon, a support member for supporting the upper layer is provided on the lower layer, and a hollow region is provided between the lower layer and the upper layer. A semiconductor device having.
記別の上部層を有し、 前記別の上部層を支持するための別の支持部材を有し、 前記別の上部層と前記上部層との間に中空領域を有する
ことを特徴とする請求項１に記載の半導体装置。2. An upper layer having the another upper layer on which a passive element is formed, further having another supporting member for supporting the other upper layer, The semiconductor device according to claim 1, further comprising a hollow region between the upper layer and the upper layer.
形成する金属配線であることを特徴とする請求項１、２
に記載の半導体装置。3. The passive element is a metal wiring forming a spiral inductor.
3. The semiconductor device according to claim 1.
下部層の上に、支持部材を形成する工程と、 該支持部材の高さまで樹脂にて埋め込む工程と、 前記支持部材及び前記樹脂の上に受動素子が形成された
上部層を作製する工程と、 前記樹脂を除去し、前記支持部材を残存させる工程とを
有することを特徴とする請求項１〜３に記載の半導体装
置の製造方法。4. A step of forming a support member on a lower layer on which an active element or a passive element is formed, a step of embedding resin up to the height of the support member, and the step of forming a support member and the resin on the lower layer. The method of manufacturing a semiconductor device according to claim 1, further comprising: a step of forming an upper layer on which a passive element is formed; and a step of removing the resin and leaving the supporting member.
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| JP01168796A JP3509362B2 (en) | 1996-01-26 | 1996-01-26 | Semiconductor device and manufacturing method thereof |
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|---|---|---|---|
| JP01168796A JP3509362B2 (en) | 1996-01-26 | 1996-01-26 | Semiconductor device and manufacturing method thereof |
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Cited By (11)
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| KR20000011585A (en) * | 1998-07-28 | 2000-02-25 | 윤덕용 | Semiconductor device and method for manufacturing the same |
| US6285069B1 (en) | 1998-04-10 | 2001-09-04 | Nec Corporation | Semiconductor device having improved parasitic capacitance and mechanical strength |
| KR100331226B1 (en) * | 2000-02-23 | 2002-04-26 | 이상헌 | microwave electric elements of using porous oxidized silicon pole |
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| KR100477547B1 (en) * | 2002-08-09 | 2005-03-18 | 동부아남반도체 주식회사 | Method for forming inductor of semiconductor device |
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1996
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| US6285069B1 (en) | 1998-04-10 | 2001-09-04 | Nec Corporation | Semiconductor device having improved parasitic capacitance and mechanical strength |
| US6383889B2 (en) | 1998-04-10 | 2002-05-07 | Nec Corporation | Semiconductor device having improved parasitic capacitance and mechanical strength |
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| US7579553B2 (en) * | 2000-07-27 | 2009-08-25 | Fujitsu Limited | Front-and-back electrically conductive substrate |
| KR100477547B1 (en) * | 2002-08-09 | 2005-03-18 | 동부아남반도체 주식회사 | Method for forming inductor of semiconductor device |
| CN100411135C (en) * | 2004-05-05 | 2008-08-13 | Atmel德国有限公司 | Method for producing a spiral inductance on a substrate, and a device fabricated according to such a method |
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