JPH09203609A - Distance measuring circuit using cmos structure - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a light projecting time from being increased and to prevent a current in a light projection section from being increased by a constitution in which a signal current is amplified by utilizing a current amplifying operation of an NPN transistor. SOLUTION: A light of an LED is projected to an object 2 of which distance is measured from a light projection section 1 and the reflection light is received by a PSD (semiconductor position detection element) 4 so that a pair of signal currents corresponding to the distance of the object 2 are outputted. The pair of signal currents are inputted to base terminals of PNP transistor 21, 121 for amplifying the currents to obtain a pair of signal amplified currents amplified by current amplification factor from emitter terminals. The pair of amplified currents are inputted to respective emitter terminals of two parasitic PNP transistor 41, 141 for signal compression in a MOS structure. An emitter voltage difference of the transistors 41, 141 is determined by a ratio if signal currents outputted from output terminals 5, 6 of the PSD. A relationship of the emitter voltage difference and the distance to the object 2 is obtained beforehand to be saved to a calculation section 7. Thereby, the distance to the object 2 is obtained in accordance with the emitter voltage difference of the transistors 41, 141.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active distance measuring circuit using a logarithmic compression circuit using a parasitic transistor formed in a CMOS structure.

[0002]

2. Description of the Related Art In order to measure a distance, a light beam having a strong directivity obtained by condensing light from a light emitting diode (LED) with a lens is projected onto an object to be measured, and the reflected light is fixed by a fixed baseline from the LED. An active triangulation method that detects the distance from the output current according to the light receiving position to the distance measuring object by receiving light with a semiconductor position detection element (PSD) installed at a place that is separated from the optical axis by a length Is commonly used.

FIG. 2 is a diagram showing a distance measuring circuit utilizing a parasitic transistor formed in a CMOS structure disclosed in Japanese Patent Laid-Open No. 6-347263. Before describing the configuration of this distance measuring circuit, first, regarding a parasitic transistor occurring in a CMOS structure, a case of using a P-type substrate will be described with reference to FIG. In the CMOS structure using the P-type substrate,
As shown in FIG. 3, a parasitic PNP transistor is formed in which the P ⁺ diffusion layer in the drain / source region of the PMOS transistor serves as the emitter, the N-Well layer of the PMOS transistor serves as the base, and the P-type substrate serves as the collector. This parasitic PNP
The transistor has a current amplification factor β as small as about 20 and has a constraint that the collector is fixed at the lowest potential.

The distance measuring circuit shown in FIG. 2 receives a reflected light through a lens 3 and a light projecting portion 1 for projecting an LED light pulse onto a distance measuring object 2 and a pair corresponding to a light receiving position. Position detecting element (PSD) 4 for outputting the current component of the power source, power source potential 15 and ground potential 16 for supplying power to the circuit, and PMOS transistors 61 to 62, NMOS transistors 63, resistors 64 to 65, current sources, respectively. 66-68 and PMOS transistors 161-162, NMOS transistor 163, resistor 16
4 to 165 and current sources 166 to 168, and sets the potentials of the PSD output terminals 5 and 6 to V _DD -V _{GS (61)} and V _DD -V, respectively.
_The feedback sections 11 and 12 fixed to _{GS (161)} and the same NMOS transistor as the NMOS transistors 63 and 163 are 100 transistors.
N for current amplification that amplifies the signal current output from PSD output terminals 5 and 6 by 100 times by connecting in parallel
The MOS transistors 71 and 171 are added to the emitters of the signal-compressing parasitic PNP transistors 41 and 141, which are formed in a MOS structure for flowing an amplified current into the emitter to obtain a logarithmic compression voltage. Parasitic capacitors 42 and 142, operational amplifier 51, reference potential parasitic PNP transistor 52, current source 53, NMOS
Transistor 54, Hold capacity 55, Resistor 56, Switch 57
And an operational amplifier 151, a reference potential parasitic PNP transistor 152, a current source 153, an NMOS transistor 154, a hold capacitor 155, a resistor 156, and a switch 157.
Background light removing sections 13 and 14 for removing background light components output from the output terminals 5 and 6, and a signal compression parasitic PNP.
It comprises an arithmetic unit 7 which inputs the emitter potentials of the transistors 41 and 141 to input terminals 8 and 9 and calculates distance information from an output terminal 10. Note that V _DD is the value of the power supply potential 15, and V _{GS (61)} and V _{GS (161)} are the gate-source voltages of the PMOS transistors 61 and 161.

Here, the feedback section 11, the current amplification NMOS transistor 71, the signal compression parasitic PNP transistor 41, the parasitic capacitance 42, and the background light removing section 13 are used to process the signal current from the PSD output terminal 5. On the Bch side, the Ach side is defined and the feedback unit 12, the current amplification NMOS transistor 171, the signal compression parasitic PNP transistor 141, the parasitic capacitance 142, and the background light removal unit 14 are used to process the signal current from the PSD output terminal 6. And The operations on the Ach side and the Bch side are exactly the same, so the operation will be described using the Ach side as an example.

First, before the LED light is projected onto the object 2 to be measured, the switch 57 is closed to form a feedback circuit for setting the + terminal of the operational amplifier 51 to the same potential as the-terminal.
As a result, only a current equal to that of the current source 53 flows into the signal compression parasitic PNP transistor 41, and P
The background light component current I _{CONT (A)} (unnecessary current) included in the current output from the SD output terminal 5 is _absorbed from the drain of the NMOS transistor 54. In the feedback circuit having such a configuration, when the positive terminal of the operational amplifier 51 has a higher potential than the negative terminal, the output of the operational amplifier 51 rises.
It will draw more current than the collector of the NMOS transistor 54. Therefore, the NMOS transistor 63
The current flowing into the signal compressing parasitic PNP transistor 41 also decreases and the potential of the + terminal of the operational amplifier 51 decreases. When the potential of the + terminal of the operational amplifier 51 becomes lower than the potential of the-terminal, the operation is completely reversed. In this way, feedback is applied so that the same current as the current source 53 flows through the signal compression parasitic PNP transistor 41.

Here, an NMOS transistor for current amplification
A current 100 times that of the NMOS transistor 63 flows through 71,
Since the current sum of the NMOS transistor 63 and the current amplification NMOS transistor 71 becomes equal to the current sum of the current source 53 and the current source 68, the current values of the current source 53 and the current source 68 are respectively I
Assuming that _{BIAS (53)} and I _{BIAS (68)} , the drain current I _{D (63)} of the NMOS transistor 63 at this time is expressed by the following equation (1). I _{D (63)} = I _{BIAS (53)} / 101 + I _{BIAS (68)} / 101 ・ ・ ・ ・ ・ ・ (1)

This operation is called a background light removing operation, and is performed in order to accurately detect the minute signal current buried in the background light component current. This is because the signal current I output from the PSD output terminal 5 when a light pulse is projected on the object 2 to be measured.
Whereas _{SIG (A)} is about 1 nA to 1 μA, the background light component current I _{CONT (A)} when the surroundings are bright is large at several μA, and the minute signal current I _{SIG (A)} is large when the background light removal operation is not performed. This is because it is buried in the background light component current I _{CONT (A)} and cannot be detected. In order to detect the minute signal current I _{SIG (A)} , the current source 53 is preferably 10 times (10 nA) or less than the minimum signal current (˜1 nA) output from the PSD output terminal 5. At this time, the PSD output terminal 5 has the PMOS transistors 61 to 62, the NMOS transistor 63, and the resistor 64 to.
Feedback is applied by 65 and current sources 66 to 68 so as to maintain a constant value (V _DD -V _{GS (61)} ). V _DD is the power supply potential of 15
, V _{GS (61)} is the gate-source voltage of the PMOS transistor 61.

Next, the switch 57 is opened, and at the same time, the LED light is projected onto the object to be measured 2 from the light projecting portion 1, and the reflected light from the object to be measured 2 is received by the PSD 4 to perform a signal detection operation. . Here, the gate potential of the NMOS transistor 54 is
Since the hold capacitor 55 holds the switch 57 in the closed state, the current drawn by the drain of the NMOS transistor 54 does not change even when the switch 57 is opened.
The background light component current I _{CONT (A)} is continuously absorbed. Therefore, the current I of the signal component output from the PSD output terminal 5
_{All SIG (A)} flows into the drain of the NMOS transistor 63.

At this time, the drain current I _{D (63)} of the NMOS transistor 63 at the time of the signal detection operation becomes as shown by the following equation (2) and increases by I _{SIG (A)} of the first term on the right side. I _{D (63)} = I _{SIG (A)} + I _{BIAS (53)} / 101 + I _{BIAS (68)} / 101 (2) Therefore, N for current amplification is compared with the background light removal operation.
The drain current _{ID (71) of the} MOS transistor 71 is also 100
× I _{SIG (A)} increments. Therefore, the signal compression parasitic P
The signal current I _{SIG (A)} input to the NMOS transistor 63 and the current amplifying NM are applied to the emitter of the NP transistor 41.
Amplified current 100 × I amplified by OS transistor 71
The sum of _{SIG (A)} 101 × I _{SIG (A)} flows in to raise the emitter potential V _{E (41)} of the signal compression parasitic PNP transistor 41. The minimum value of the signal current that can be detected is determined by the number of current amplification NMOS transistors 71.

Assuming that the signal currents output to the Ach side and the Bch side are I _{SIG (A)} and I _{SIG (B)} , respectively, the emitter potential difference Δ between the signal compression parasitic PNP transistors 41 and 141 is Δ.
V _SIG is represented by the following equation (5) from the following equations (3) and (4). V _{E (41)} = V _T ln {(101 × I _{SIG (A)} + I _{BIAS (53)} ) / I _S } ... (3) V _{E (141)} = V _T ln {(101 × I _{SIG ( B)} + I _{BIAS (153)} ) / I _S } ... (4) ΔV _SIG = V _{E (41)} −V _{E (141)} = V _T ln {(101 × I _{SIG (A)} + I _{BIAS (53)} ) / (101 × I _{SIG (B)} + I _{BIAS (153)} )} (5) where I _{BIAS (53)} <101 × I _{SIG (A)} and I _{BIAS (153)}
Assuming that <101 × I _{SIG (B)} , I _{BIAS (53)} = I _{BIAS (153)} , ΔV _SIG is the ratio of signal currents I _{SIG (A)} / I _SIG output from the PSD output terminals 5 and 6. _(B) Uniquely determined by (PSD light receiving position). However, V _T is a thermoelectromotive force and I _S is a saturation current.

From the above, the relationship between the emitter potential difference ΔV _SIG and the distance to the object to be measured is obtained in advance, and the calculation unit 7
If saved, the distance to the object to be measured can be known from the emitter potential difference ΔV _SIG between the signal compression parasitic PNP transistors 41 and 141. Further, in order to improve the distance measurement accuracy, it is general to perform the distance measurement for about 100 sets with the background light removal operation and the signal detection operation as one set and take the average value.

[0013]

However, in the conventional distance measuring circuit shown in FIG. 2, a large number of NMOS transistors 71 and 171 are provided at the emitter terminals of the signal compression parasitic PNP transistors 41 and 141 in order to amplify the signal current. Are connected, large parasitic capacitances 42 and 142 are added. Therefore, when the signal current output from the PSD output terminals 5 and 6 is very small, it takes time to charge the parasitic capacitances 42 and 142, and the signal compression parasitic PNP transistor 41.
And 141 the emitter potential response is very poor. Poor responsiveness means an increase in (LED) light projecting time from the light projecting unit 1, an increase in large current conduction time for the LED in the light projecting unit 1 (overload), and consumption in the light projecting unit 1. This causes an increase in current and an increase in distance measurement time. On the other hand, if the number of times of light projection is reduced in order to avoid these problems, the accuracy of distance measurement deteriorates.

The present invention has been made in order to solve the above-mentioned problems in the conventional distance measuring circuit, and has a good responsiveness even when the signal current output from the PSD output terminal is very small, and has a CMOS structure. It is an object of the present invention to provide a distance measuring circuit using a logarithmic compression circuit using the formed parasitic transistor.

[0015]

In order to solve the above problems, the present invention provides a light projecting means for projecting a light beam toward an object to be measured, and a reflected light of the light beam from the object to be measured. And a pair of NPN for receiving the pair of signal currents and a light receiving unit for receiving a pair of signal currents according to the distance of the object to be measured.
A current amplifying means for inputting to each base of the transistor and extracting a pair of amplified currents from each emitter, and the pair of amplified currents respectively input to the emitters of the parasitic bipolar transistors in the CMOS structure. A logarithmic compression unit that outputs a compressed signal and a distance detection unit that obtains the distance to the object to be measured from the pair of logarithmic compressed signals constitute a distance measurement circuit using a CMOS structure.

In the distance measuring circuit using the CMOS structure having the above-mentioned structure, a light beam is projected from the light projecting means to the distance measuring object, and the light receiving means receives the reflected light from the distance measuring object. , A pair of signal currents corresponding to the distance of the object to be measured is output. The pair of signal currents is flown into the base of the NPN transistor, and the current amplification factor times (β
To obtain a pair of signal amplification currents. Furthermore, 1
A pair of signal amplification currents are flown into the emitters of two parasitic transistors parasitic in the MOS structure, and a logarithmic compression signal is output. Further, the distance to the object to be measured is obtained by the distance detecting means from the voltage difference between the two logarithmic compression signals.

As described above, in the distance measuring circuit having the above configuration,
Since the signal current is amplified by utilizing the current amplification effect of the NPN transistor, it is not necessary to connect a large area MOS for signal current amplification to the emitter of the signal compression parasitic PNP transistor, and the emitter of the signal compression parasitic PNP transistor is not required. The parasitic capacitance attached to is extremely small. Therefore, P
Even when the signal current output from the SD output terminal is minute, deterioration of responsiveness can be avoided. Therefore, the LED of the projector
It is possible to suppress an increase in the light projection time of the LED, an increase in the large current conduction time to the LED (overload), an increase in the current consumption in the light projection unit, and an increase in the distance measurement time. Further, since it is not necessary to reduce the number of times the light is projected, it is possible to suppress a decrease in distance measurement accuracy.

[0018]

Next, an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 shows a CM according to the present invention.
In the figure showing the embodiment of the distance measuring circuit using the OS structure, the same reference numerals are given to the components corresponding to those of the conventional example shown in FIG. The distance measuring circuit using the CMOS structure of this embodiment has a light projecting unit 1 for projecting an LED light pulse to a distance measuring object, and a reflected light received by the light projecting unit 1 according to a light receiving position.
Semiconductor position detector (PSD) that outputs a pair of signal currents
4, power supply potential 15 and ground potential 16 for supplying power to the circuit
And a pair of current amplifying N for inputting a pair of signal currents output from the PSD output terminals 5 and 6 to the respective bases and outputting a β times signal amplification current from each emitter.
PN transistors 21 and 121, operational amplifier 31, PMO
S transistor 32, current sources 33 to 34 and operational amplifier 131,
PMOS transistor 132, current sources 133 to 134, voltage source
Feedback portions 17 and 18 which are composed of 35 and fix the potentials of the PSD output terminals 5 and 6 to a value equal to that of the voltage source 35, and a pair of signal amplification currents are flown into the respective emitters to obtain logarithmically compressed signals from the respective emitters. The signal compression parasitic PNP transistors 41 and 141 formed in the MOS structure, the parasitic capacitances 42 and 142 added to the emitters of the signal compression parasitic PNP transistors 41 and 141, the operational amplifier 51, the reference potential parasitic PNP transistor 52, Current source 53, NMOS transistor 54, hold capacitor 55, resistor 56, switch 57 and operational amplifier 151, reference potential parasitic PNP transistor
The background light removing units 13 and 14 for removing the background light components included in the currents output from the PSD output terminals 5 and 6 are composed of a current source 153, a current source 153, an NMOS transistor 154, a hold capacitor 155, a resistor 156, and a switch 157. And an arithmetic unit 7 which inputs the emitter potentials of the signal compression parasitic PNP transistors 41 and 141 to the input terminals 8 and 9 and calculates distance information from the output terminal 10.

Here, the current amplifying NPN transistor 21 for processing the signal current from the PSD output terminal 5 and the feedback section 17 are provided.
And the signal compression parasitic PNP transistor 41, the parasitic capacitance 42, and the background light removing unit 13 on the Ach side, and the current amplification NPN transistor 121 that processes the signal current from the PSD output terminal 6
The feedback section 18, the signal compression parasitic PNP transistor 141, and the parasitic capacitance 142 are on the Bch side.

Next, the operation of the distance measuring circuit thus constructed will be described. The operations on the Ach side and the Bch side are exactly the same, so the operation will be described using the Ach side as an example. Also in this embodiment, the background light removing operation and the signal detecting operation are performed as in the conventional example. First, LED on the distance measurement object 2
Before projecting light, switch 57 is closed and operational amplifier 51
A feedback circuit is configured to make the + terminal of the same potential as that of the-terminal, and the background light removal operation is performed. As a result, only the same current as the current source 53 flows into the signal compression parasitic PNP transistor 41, and the background light component current I _{CONT (A)} (unnecessary current) included in the output of the PSD output terminal 5 is supplied to the NMOS.
Suction from the drain of transistor 54. By configuring the feedback circuit in this way, when the potential of the + terminal of the operational amplifier 51 is higher than the potential of the-terminal, the output of the operational amplifier 51 rises, so that a larger amount of current is absorbed by the collector of the NMOS transistor 54. . Therefore, the current flowing into the base of the current amplifying NPN transistor 21 and the current flowing out from the emitter of the current amplifying NPN transistor 21 are reduced, the current flowing into the signal compression parasitic PNP transistor 41 is also reduced, and the potential of the + terminal of the operational amplifier 51 is reduced. Will fall. The potential of the + terminal of the operational amplifier 51 is −
When it becomes lower than the potential of the terminal, the operation is completely opposite. In this way, the signal compression parasitic PNP transistor 41
Feedback is applied so that a current equal to that of the current source 53 flows through.

The base current I _{B (21)} and the emitter current I _{E (21)} of the current amplifying NPN transistor 21 have a relationship shown by the following equation (6). −IE ₍₂₁₎ ≈β × IB ₍₂₁₎ ... (6) However, the negative sign attached to _{IE (21)} means that current flows out from the emitter, and β is bipolar. The current amplification factor of the transistor is about 100. Here, the current amplification NPN transistor 21 at the time of the background light removing operation includes a current source
Since the sum current of the current source 34 and the current source 53 is flowing, if the current values of the current source 34 and the current source 53 are I _{BIAS (34)} and I _{BIAS (53)} , respectively, the current amplifying NPN transistor 21 The base current I _{B (21) of} is as shown by the following equation (7). I _{B (21)} = I _{BIAS (34)} / β + I _{BIAS (53)} / β (7) Further, the PSD output terminal 5 includes an operational amplifier 31, a PMOS transistor 32, and a current source 33. By ~ 34, feedback is applied so as to keep the same value as the voltage source 35.

Next, when the switch 57 is opened, at the same time, the LED light is projected from the light projecting unit 1 onto the object to be measured 2 and the reflected light from the object 2 to be measured is received by the PSD 4. To do. Here, the gate potential of the NMOS transistor 54 is held by the hold capacitor 55 in the state in which the switch 57 is closed.
There is no change in the current drawn by the drain of the transistor 54, and the background light component current I _{CONT (A)} is continuously taken in. Therefore, the current I _{SIG (A)} of the signal component output from the PSD output terminal 5 is entirely the current amplifying NPN transistor 21.
Flows into the base of. As a result, the base current I of the NPN transistor 21 for current amplification at the time of signal detection operation
_{B (21)} is represented by the following equation (8), and increases by I _{SIG (A)} of the first term on the right side. I _{B (21)} = I _{SIG (A)} + I _{BIAS (34)} / β + I _{BIAS (53)} / β (8)

Therefore, compared with the background light removing operation, the emitter of the current amplifying NPN transistor 21 is
The current flowing out has increased by β × I _{SIG (A)} . This increased current β × I _{SIG (A)} flows into the drain of the PMOS transistor 32, and further the PMOS transistor 32
It flows into the emitter of the signal compression parasitic PNP transistor 41 from the source of 32, and raises the emitter potential V _{E (41)} of the signal compression parasitic PNP transistor 41.

If the signal currents output to the Ach side and the Bch side are I _{SIG (A)} and I _{SIG (B)} , respectively, the emitter potential difference ΔV _SIG between the signal compression parasitic PNP transistors 41 and 141 is The following equation (11) is obtained from the following equations (9) and (10). V _{E (41)} = V _T ln {(β × I _{SIG (A)} + I _{BIAS (53)} ) / I _S } ... (9) V _{E (141)} = V _T ln {(β × I _{SIG (B)} + I _{BIAS (153)} ) / I _S } ... (10) ΔV _SIG = V _{E (41)} −V _{E (141)} = V _T ln {(β × I _{SIG (A)} + I _{BIAS (53 )} ) / (Β × I _{SIG (B)} + I _{BIAS (153)} )} (11) where I _{BIAS (53)} <β × I _{SIG (A)} and I _{BIAS (153 ) )} <
Assuming that β × I _{SIG (B)} and I _{BIAS (53)} = I _{BIAS (153)} , ΔV _SIG is the ratio of signal currents I _{SIG (A)} / I _{SIG ( B)} (PSD light receiving position)
Is uniquely determined by. However, V _T is a thermoelectromotive force and I _S is a saturation current. Therefore, if the relationship between the emitter potential difference ΔV _SIG and the distance to the object to be measured is obtained in advance and saved in the arithmetic unit 7, the signal compression parasitic PNP transistor can be obtained.
The distance to the object to be measured can be known from the emitter potential difference ΔV _SIG between 41 and 141.

In addition, a large area MOS for current amplification is used for the emitters of the signal compression parasitic PNP transistors 41 and 141.
Is not connected, the parasitic capacitances 42 and 142 are small, and the parasitic PNP transistor for signal compression is used even when a minute signal is input.
Responsiveness of the emitter potentials V _{E (41)} and V _{E (141)} of 41 and 141 is sufficiently secured. Therefore, it is possible to suppress the increase of the light projecting time of the light projecting unit 1, and to suppress the increase of the large current conduction time (overload) of the LED in the light projecting unit 1, the increase of the current consumption, and the increase of the distance measurement time. Further, since it is not necessary to reduce the number of times the light is projected, it is possible to suppress a decrease in distance measurement accuracy. Furthermore, since most of the distance measuring circuit can be configured by the CMOS process, it has an advantage that it can be easily integrated with a digital circuit and a processing unit such as a CPU, and is advantageous in cost reduction.

[0026]

As described based on the above embodiments, according to the present invention, the signal current is amplified by utilizing the current amplifying action of the NPN transistor. Therefore, the signal compression parasitic bipolar transistor is used. Since it is not necessary to connect a large area MOS for signal current amplification to the transistor, the parasitic capacitance can be made extremely small, thereby avoiding the deterioration of responsiveness, suppressing the increase of the light projecting time, and the current consumption of the light projecting unit. It is possible to suppress an increase in the distance measurement time and an increase in the distance measurement time, and since it is not necessary to reduce the number of times the light is projected, it is also possible to suppress a decrease in the distance measurement accuracy.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing an embodiment of a distance measuring circuit using a CMOS structure according to the present invention.

FIG. 2 is a circuit configuration diagram showing a distance measuring circuit using a conventional CMOS structure.

FIG. 3 is a diagram showing an aspect of a parasitic transistor generated in a CMOS structure.

[Explanation of symbols]

 1 Light emitting unit 2 Distance measurement object 3 Lens 4 Semiconductor position detecting element 5,6 Semiconductor position detecting element output terminal 7 Arithmetic unit 8,9 Arithmetic unit input terminal 10 Arithmetic unit output terminal 13,14 Background light removing unit 15 Power supply potential 16 Ground potential 17,18 Feedback unit 21,121 Current amplification NPN transistor 31,131 Operational amplifier 32,132 PMOS transistor 33,34,133,134 Current source 35 Voltage source 41,141 Signal compression parasitic PNP transistor 42,142 Parasitic Capacitance 51,151 Operational amplifier 52,152 Reference potential parasitic PNP transistor 53,153 Current source 54,154 NMOS transistor 55,155 Hold capacity 56,156 Resistor 57,157 Switch

Claims (1)

[Claims] 1. A pair of light projection means for projecting a light beam toward an object to be measured, and a pair of light receiving means for receiving the reflected light of the light beam from the object to be measured and corresponding to the distance to the object to be measured. And a pair of NPN for receiving the pair of signal currents.
A current amplifying means for inputting to each base of the transistor and extracting a pair of amplified currents from each emitter, and the pair of amplified currents respectively input to the emitters of the parasitic bipolar transistors in the CMOS structure. A distance measuring circuit using a CMOS structure, comprising: a logarithmic compression means for outputting a compressed signal; and a distance detecting means for obtaining a distance to the distance measuring object from the pair of logarithmic compression signals.