JP2998805B2 - Integrator circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integration circuit used for measuring a minute current of a sensor or the like.

[Conventional technology]

Conventionally, various proposals have been made for a circuit for measuring a minute current obtained from a sensor by integration. As an example, an integration circuit used as a luminance measurement circuit in a camera or the like will be described with reference to FIG.

In FIG. 7, reference numeral 101 denotes a first operational amplifier. The + input terminal of the operational amplifier 101 is connected to a reference voltage source 102, and the output terminal is the base of a transistor 103 whose collector is connected to a circuit power supply V _CC. Is connected. The negative terminal of the first operational amplifier 101 is connected to the emitter of the transistor 103.
Input terminal is connected and further connected a current source 104 via the switch SW ₁ to GND. Also between the power supply terminal and the GND of the first operational amplifier 101, switch SW ₂ in conjunction with the switch SW ₁ is connected.

The photodiode 106 is connected between the + and-input terminals of the second operational amplifier 105, and the-input terminal of the first operational amplifier 101 and the emitter of the transistor 103 are connected to the + input terminal. , Integration capacitor 1
07 is connected, and the-input terminal and the output terminal are directly connected. The force terminal of the second operational amplifier 105 is connected to the-input terminal of the comparator 108, and the + input terminal of the comparator 108 is connected to the comparison voltage source 109.

In the integration circuit configured in this way, before starting the integration is closed switch SW ₁ and SW _2, the reference voltage V of the reference voltage source 102 to the positive input terminal of the second operational amplifier 105
_REF is added. When opening the switch SW ₁ and SW ₂ in this state, the first operational amplifier 101 becomes inoperative, the transistor 103 is also turned off, photocurrent generated in the photodiode 106 through the integrating capacitor 107. At this time, the output of the second operational amplifier 105 has a value represented by the following equation (1).

Here, I _P : photocurrent of the photodiode t: integration time C: capacity of the integration capacitor Further, since the output voltage of the second operational amplifier 105 is applied to the − input terminal of the comparator 108, When the input voltage, that is, the output voltage of the second operational amplifier 105 becomes a value represented by the following equation (2), the output level of the comparator 108 is inverted.

Here, V _{TH is the} comparison voltage of the comparison voltage source.
A pulse having a width indicated by is output.

Therefore, the photocurrent of the photodiode 106 can be obtained by counting the pulse width.

[Problems to be solved by the invention]

Incidentally, in the conventional integrating circuit shown in FIG. 7, the transistor 103 is off while the switches SW ₁ and SW ₂ are open, that is, during the integrating operation, and the output of the first operational amplifier 101, that is, the transistor 103 Is open or fixed to a low voltage, and the output voltage of the photodiode 106 is applied to the emitter of the transistor 103. Thus since the between the emitter and base of the transistor 103 such reverse bias V _R, the reverse bias V _R, a leakage current flows I _R shown by the following formula (4).

However, q: electron charge quantity k: Boltzmann's constant T: absolute temperature I _S: saturation current leakage current I _R of the PN junction increases with reverse bias V _R and the temperature rise. If the leakage current I _R is produced an output of the second operational amplifier 105, When the photocurrent of the photodiode 106 is small, a large error occurs or measurement becomes impossible.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem in the conventional integration circuit, and an object of the invention is to provide an integration circuit that suppresses leakage current during integration and enables measurement of a minute current.

[Means and Actions for Solving the Problems]

The configuration of the present invention for solving the above problem will be described based on the conceptual diagram shown in FIG. 1 with reference to FIG. The present invention provides a reference voltage source 1 for supplying a reference voltage, an integration amplifier 2 having an input terminal connected to an integration capacitor 16, and an on-state before the start of integration for applying the reference voltage to the integration capacitor before the start of integration. The switching transistor 12 (switching circuit 3) which is turned off after the integration is started, the base is connected to the current source, the emitter is connected to the output terminal of the integration amplifier, and the collector is connected to the base of the switching transistor 12. And a feedback transistor 5 configured to supply a voltage between the base of the switching transistor in the OFF state and the other electrode serving as an input terminal of the integrating amplifier to a collector of the feedback transistor. The integration circuit is configured to maintain the saturation voltage between the emitters. In FIG. 1, reference numeral 6 denotes a buffer amplifier, and reference numeral 7 denotes a switch for turning on / off the setting of the current source 4 to the power supply voltage V _CC .

In the integrating circuit thus configured, before the start of integration, the switching transistor 12 is on, the reference voltage of the reference voltage source 1 is applied to the integrating amplifier 2, and the output of the integrating amplifier becomes equal to the reference voltage. At this time, the feedback transistor 5 is turned off by keeping the current source 4 open. In this state, integration is started by giving an integration start signal from the outside and turning off the switching transistor 12. At the same time, by closing the current source 4, a constant current flows into the base of the feedback transistor 5, and the feedback transistor 5 is turned on. At this time, since the feedback transistor 5 is saturated, the saturation voltage V _{CB (SAT)} (≒ 0.2 V) is maintained between the collector and the emitter of the feedback transistor 5 even if the potential of the emitter changes. By connecting the collector of the feedback transistor 5 to the base of the switching transistor 12 where the leakage is a problem, the saturation voltage V is applied between the base and the collector or between the base and the emitter where the leakage of the switching transistor 12 occurs.
_{Since CB (SAT)} (≒ 0.2V) is maintained, the leakage current of the switching transistor 12 during integration can be suppressed,
Measurement of a minute current becomes possible.

Example Next, an example will be described. FIG. 2 is a circuit diagram showing a first embodiment of the integrating circuit according to the present invention.
Members corresponding to the members shown in the conceptual diagram shown in the drawings are denoted by the same reference numerals. In FIG. 2, 11 is the first
The reference voltage source 1 is connected to the + input terminal of the operational amplifier 11. Further to the output terminal of the first operational amplifier 11 and the base of the switching transistor 12 is connected to the emitter of the switching transistor 12 of the first operational amplifier 11 - through an input terminal, the switch SW ₁ to the GND One end of a current source (1) 13 connected to the other end is connected, and the collector of the transistor 12 is connected to the power supply voltage V _CC . Note the first operational amplifier 11 - power supply terminal is connected to GND via the switch SW _2.

Reference numeral 14 denotes a second operational amplifier.
The photodiode 15 is connected between the-input terminals, the-input terminal of the first operational amplifier 11 and the emitter of the switching transistor 12 are connected to the + input terminal, and the integration capacitor 16 is connected. I have. The negative input terminal and output terminal of the second operational amplifier 14 are directly connected, and the output terminal is connected to the positive input terminal of the third operational amplifier 6. The negative input terminal and the output terminal of the third operational amplifier 6 are directly connected and used as a buffer amplifier, and the output terminal is connected to the emitter of the feedback transistor 5.

The power supply voltage V _CC is connected to the base of the feedback transistor 5.
Current source (2) 4 connected to switch CSW via switch CSW
Are connected, and the collector is the switching transistor.
Connected to 12 bases. The output terminal of the third operational amplifier 6 is connected to the + input terminal of the comparator 17, and the comparison voltage source 18 is connected to the − input terminal of the comparator 17.

The first operational amplifier 11, the switching transistor 12, the current source (1) 13, and the switches SW ₁ and SW ₂ constitute a switching circuit 3. The second operational amplifier 1
4, the photodiode 15, and the integrating capacitor 16 constitute the integrating amplifier 2. Note that a resistor R ₁ for improving switching characteristics is provided between the base and the emitter of the feedback transistor 5.
And the second and third operational amplifiers 14 and 6 are assumed to measure a very small current.
It is desirable to use an S transistor.

Next, the operation of the integrating circuit thus configured will be described. First, the switches SW ₁ ,
Table 1 shows the states of SW ₂ and CSW.

Before the start of integration, since the switches SW ₁ and SW ₂ are closed, the points A, B and C at the + input terminal of the second operational amplifier 14, its output terminal and the output terminal of the third operational amplifier 6 are The potential becomes the voltage _VREF of the reference voltage source. At this time, since the switch CSW is open, the feedback transistor 5 is off, and does not affect the operation of the integrating amplifier 2. In this state, when the switches SW ₁ and SW ₂ are opened and the switch CSW is closed by the integration start signal, the integration starts, and the potential at the points A, B and C is expressed by the above equation (1). Similarly, the _{V REF + I P · t /} C.

As a result, the potential of the collector terminal D of the feedback transistor 5 that has been saturated becomes Becomes By this operation, the reverse bias V is applied between the base and the emitter of the switching transistor 12 during the integration operation.
_{CE (SAT)} (≒ 0.2V) is maintained. In general, the leakage current that occurs when a reverse bias of this level is applied between the base and the emitter of a transistor is less than the measurement limit, so there is no problem. Therefore, the small photocurrent generated in the photodiode can be measured with high accuracy. can do.

FIG. 3 is a circuit diagram showing a second embodiment, in which the same or equivalent members as those in the first embodiment shown in FIG. 2 are denoted by the same reference numerals. In this embodiment, the feedback transistor 5 is
This is a PNP transistor, and has the same operation and effect as the first embodiment except that the direction of current flow is different.

FIG. 4 is a circuit diagram showing a third embodiment.
Members that are the same as or equivalent to those of the first embodiment shown in the figures are given the same reference numerals. This embodiment, the output terminal of the first operational amplifier 11 is connected to the emitter of the switching transistor 12 is connected to a current source (1) 13 to the base with the base-emitter to a resistor R _2, the collector Is connected to the + input terminal of the second operational amplifier 14. And the first
The negative input terminal of the operational amplifier 11 and the negative input terminal (output terminal) of the second operational amplifier 14 are directly connected.

In the integration circuit thus configured, when the switching transistor 12 is off, there is no potential difference between the base and the emitter, and the potential difference between the base and the collector is maintained at the saturation voltage V _{CC (SAT)} of the feedback transistor 5. For,
All terminals of the switching transistor 12 have substantially the same potential, and the leakage current is effectively suppressed.

Figure 5 is a circuit diagram showing an embodiment in which an IC switching circuit in the present invention, the transistor Q ₇ is a switching transistor, the transistor Q ₈ is feedback transistor. In this embodiment, similarly to the above embodiments, during the integration operation, by keeping the inter-CE of the feedback transistor Q ₈ the saturation voltage V _{CE (SAT),} the feedback transistor potential between BE switching transistor Q ₇ Q ₈ saturation voltage
In addition to the operation of keeping V _{CE (SAT)} , the following functions are provided.

That is, the use of switching circuit according to the present invention, BE between the saturation voltage V of the switching transistor Q ₇
At the same time as being maintained at _{CE (SAT)} , the differential stage transistor Q ₄
Is maintained at the saturation voltage V _{CE (SAT)} . As a result, the transistor Q _{4 of the} differential stage formed with the IC
Can be prevented from operating. If the parasitic transistor of the transistor Q ₄ of the differential stage is operated, the photocurrent of the photodiode 15 does not flow into the integration capacitor 16, significantly measurement accuracy flows through the parasitic transistors is reduced.

This will be described in more detail with reference to FIG.
As shown in, in the NPN transistor constituting the transistor Q ₄ of the differential stage formed into an IC, a parasitic PNP transistor Q _X is formed between the base region and the substrate, shown in the equivalent circuit of FIG. 6 (B) Will be connected as follows. Focusing now on the transistor Q ₄ of the differential stage of the case of not using the switching circuit of the present invention, when explaining the operation, during the integration operation, the voltage at the collector terminal of the transistor Q ₄ are,
Before the integration operation is a certain potential V _X which has been charged in the capacitor C _1. Base potential of the transistor Q ₄ are contrary, (1) as indicated by the formula, is largely changed, the potential as _{(V REF + I P · t} / C), When the value shown in the above equation (7) is reached, the parasitic transistor Q _X
But works, will photocurrent I _P flows, correct integration is not performed. By providing a switching circuit as in the present invention, however, ensures the operation of the parasitic transistor Q _X of the transistor Q ₄ because between CB of the transistor Q ₄ is adapted to be held in the saturation voltage V _{CE (SAT)} And a highly accurate measurement of the minute photocurrent can be performed.

〔The invention's effect〕

As described above based on the embodiment, according to the present invention, the voltage between the base of the switching transistor and the other electrode serving as the input terminal of the integration amplifier is set by the feedback transistor that operates during integration. Since the configuration is such that the saturation voltage between the collector and the emitter of the feedback transistor is maintained, the leakage current of the switching transistor is suppressed to a small value, and a very small current can be measured with high accuracy.

[Brief description of the drawings]

FIG. 1 is a conceptual diagram for explaining an integrating circuit according to the present invention, FIG. 2 is a circuit configuration diagram showing a first embodiment of the present invention,
FIG. 3 is a circuit diagram showing a second embodiment of the present invention.
FIG. 5 is a circuit configuration diagram showing a third embodiment of the present invention, FIG. 5 is a circuit configuration diagram showing an embodiment in which the switching circuit of the present invention is formed into an IC, and FIG. FIG. 6B is a diagram showing an equivalent circuit to which parasitic transistors are connected, and FIG. 7 is a diagram showing a configuration example of a conventional integration circuit. In the figure, 1 is a reference voltage source, 2 is an integrating amplifier, 3 is a switching circuit, 4 is a current source, 5 is a feedback transistor,
Reference numeral 6 denotes a buffer amplifier.

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-62-159055 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G01R 19/00-19/32 G01D 1 / 04 H03F 1/34

Claims (2)

(57) [Claims] A reference voltage source for supplying a reference voltage; an integration amplifier having an input terminal connected to an integration capacitor; and an integration amplifier for applying the reference voltage to the integration capacitor before starting integration.
A switching transistor that is turned on before the start of integration and turned off after the start of integration, and a base is connected to the current source,
A feedback transistor having an emitter connected to the output terminal of the integrating amplifier and a collector connected to the base of the switching transistor, wherein the feedback transistor is
It is configured to maintain a voltage between the base of the switching transistor at the time of the OFF state and the other electrode serving as an input terminal of the integration amplifier at a saturation voltage between the collector and the emitter of the feedback transistor. An integrating circuit characterized by the above. 2. The integration circuit according to claim 1, wherein the current source connected to the base of the feedback transistor is turned on when the accumulation of the integration amplifier is started and turned off when the accumulation is completed. .