JPH09200039A - Reset processing unit for arithmetic circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent malfunction by avoiding reset processing of a peripheral circuit from being finished before the configuration of a programmable gate array is finished. SOLUTION: When a power supply circuit 6 is energized, at first 1st control module 5A starts the configuration of a programmable gate array 1. When the configuration is finished, a 2nd control module 5B terminates the programmable gate array 1 and a peripheral circuit 3. When the reset of the peripheral circuit 3 or the like is finished before the configuration of the programmable gate array 1 is finished, a control section 7 inform it to a host device 9.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reset processing device for an arithmetic circuit, which prevents malfunction when the arithmetic circuit constituted by a programmable gate array programmable by configuration and its peripheral circuit is reset.

[0002]

2. Description of the Related Art LSIs (high-density integrated circuits) and general-purpose ICs
FPGA (Field-Prog
ramable-Gate-Array) may be mixed. This F
The PGA is hereinafter referred to as a programmable gate array. This programmable gate array is a circuit in which the wiring of the logic module can be freely set by configuration, which is a program for setting the environment. That is,
Customize and operate the integrated circuit under pre-prepared environmental conditions. On the other hand, when the power is turned on and the device is started up, the arithmetic circuit is reset. The programmable gate array performs a reset process after performing a configuration in advance. Further, the peripheral circuits of the programmable gate array also execute the reset process at the same time. As a device for such reset processing, a module having a power-on reset function that monitors a rise in power supply voltage and outputs a reset control pulse when the power supply voltage exceeds a certain value is used. It Configuration is started by a pulse output from this module, or reset processing of peripheral circuits including a programmable gate array is executed.

[0003]

The conventional reset processing device for an arithmetic circuit as described above has the following problems to be solved. The programmable gate array is reset after the configuration is completed. However, if the peripheral circuit starts the reset process at the same time as the programmable gate array, the peripheral circuit may start operating before the reset process of the programmable gate array ends. In such a case, there is a problem that the peripheral circuit which operates by the output of the programmable gate array sends out uncertain data and causes a malfunction. In particular, when the reconfiguration function is provided so that the configuration is re-executed if the configuration fails due to external noise, etc., the reset end of the programmable gate array will be significantly delayed compared to other peripheral circuits. There is also. In such a case, the above-mentioned malfunction is likely to occur.

[0004]

The present invention employs the following structure to solve the above problems. <Configuration 1> A programmable gate array programmable by configuration and its peripheral circuits are reset, and a first control module for activating the configuration of the programmable gate array and terminating the configuration And a second control module that executes a reset process of the programmable gate array and its peripheral circuits after a predetermined time has elapsed from the start of the configuration. Circuit reset processing device.

<Description> The programmable gate array is
This is a circuit in which the wiring of the logic module can be freely set by configuration (execution of a program for setting the environment). As the peripheral circuit, various integrated circuits and the like are arranged. When the device is started up, the programmable gate array is configured and the reset process is executed. When the device is started up, the peripheral circuits of the programmable gate array are also reset. On the other hand, it takes a certain amount of time to configure the programmable gate array. If this configuration is not completed, the peripheral circuits will not operate normally. Therefore, first, the configuration of the programmable gate array is preceded, and the peripheral circuits including the programmable gate array are reset after a lapse of a predetermined time required to complete the configuration. As a result, it is possible to prevent an indeterminate signal from being sent to another circuit from the peripheral circuit whose reset has been completed first. The first control module and the second control module do not have to be physically separate bodies, and may have a structure in which both are integrated.

<Structure 2> In Structure 1, the first control module and the second control module monitor the rise of the power supply voltage and output a control pulse when the power supply voltage exceeds a certain value to supply the power supply voltage. A reset processing device for an arithmetic circuit, comprising a timer circuit capable of selecting a response time from when the control pulse exceeds a certain value to when the control pulse is output.

<Explanation> A module having a power-on reset function that outputs a reset control pulse by monitoring the power supply voltage is suitable for resetting the circuit at the time of starting the device. A module having the function is used as the first control module and the second control module, and different response times are set respectively. As a result, after the first control module causes the programmable gate array to start the configuration and after a predetermined time for ending the configuration has passed, the second control module resets the peripheral circuit including the programmable gate array. Can be terminated.

<Structure 3> In Structure 1, even if the reset of the peripheral circuits is completed, if the programmable gate array has not completed the configuration, a control unit for monitoring the state and notifying the external circuit is provided. A reset processing device for an arithmetic circuit characterized by the above.

<Explanation> If the configuration of the programmable gate array is not completed even after the resetting of the peripheral circuits is completed, an uncertain signal may be sent from the peripheral circuits to other circuits. If the control unit monitors this state and notifies the host device or the like, a corresponding action can be taken immediately and a malfunction can be prevented.

<Structure 4> In Structures 1 to 3, after the first control module starts the configuration of the programmable gate array, the second control module ends the reset process of the programmable gate array and its peripheral circuits. A reset processing device for an arithmetic circuit, characterized in that the fixed time of is set to be equal to or longer than a time at which reconfiguration can be repeated once or more after the initial configuration.

<Description> The configuration may fail due to intrusion of noise or the like. In this case,
There is a function to control the re-execution of the configuration. This is called reconfiguration. If the peripheral circuits are reset before this reconfiguration ends, an uncertain signal is still output to other circuits. Therefore, in order to secure the time for one or more reconfigurations, a fixed time is set until the second control module finishes resetting the programmable gate array and its peripheral circuits.

<Structure 5> In the structure 1, in the case where a programmable gate array which requires further initialization after the configuration is included, a first control module for activating the configuration of all programmable gate arrays and its A second control module for setting a predetermined time required for ending the configuration, and executing a reset process of the programmable gate array requiring the initial setting after the predetermined time has elapsed from the start of the configuration; A control for receiving the output of the second control module, executing the initialization of the programmable gate array, and executing the reset process of the peripheral circuit including the programmable gate array that does not require the initialization after the initialization is completed. With department Reset processing unit of the arithmetic circuit, characterized in that.

<Description> Some programmable gate arrays are initialized to an arbitrary state by the control unit after the configuration is executed.
In the case of including such a programmable gate array, it is necessary to reset the peripheral circuits in consideration of the initial setting time. However, the time required for the initial setting by the control unit varies depending on the contents of the initial setting and cannot be predicted in advance. Therefore, after the control unit completes the initial setting, the reset of the peripheral circuit including the programmable gate array that does not require the initial setting is completed.
The control unit accepts the output of the control module in order to recognize the end of resetting the programmable gate array that requires initialization. This is because the initial setting is started after the reset.

<Structure 6> In an arithmetic circuit in which a circuit that requires initial setting after reset processing and another circuit that does not require initial setting coexist, with respect to a circuit that requires initial setting after reset processing. The reset module and the circuit that requires the above initialization after receiving the output of this control module, and does not require the initialization after the initialization. A reset processing device for an arithmetic circuit, comprising a control unit that executes reset processing for other circuits.

<Explanation> Configuration 5 is applied to an arithmetic circuit including a programmable gate array for configuration, but various circuits that require initial setting and circuits that do not require initial setting are mixed. Even in such a case, it is preferable to similarly shift the reset processing timing. The configuration 6 is also applied to any arithmetic circuit that does not include a programmable gate array. Since no configuration is performed here, only one control module is required, and the other configurations are the same as those in the configuration 5.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to specific examples. <Specific Example 1> FIG. 1 is a schematic block diagram showing a specific example of the apparatus of the present invention. This device controls a reset process for an arithmetic circuit including a programmable gate array 1 and its peripheral circuit 3. An environment setting data memory 4 is prepared for the configuration of the programmable gate array 1. When executing the configuration, the programmable gate array 1 reads data from the environment setting data memory 4 and wires the logic module.

The first control module 5A is composed of a circuit that monitors the rise of the power supply voltage when the power supply circuit 6 is turned on and outputs a control pulse when the power supply voltage exceeds a certain value. It The second control module 5B also includes a similar circuit. First control module 5A
The timer circuit 7A provided in 1 sets the response time from when the power supply voltage exceeds a certain value to when the control pulse is output. In addition, the timer circuit 7B of the second control module 5B
Also, the response time from when the power supply voltage exceeds a certain value to when the control pulse is output is selected. In the present invention, the response time set by the timer circuit 7B and the timer circuit 7A
These time settings are made so that the programmable gate array 1 finishes the configuration within a time corresponding to the difference in response time set by. That is,
The first control module 5A first outputs the configuration activation signal 11 to the programmable gate array 1 to start the configuration.

Then, after the configuration is completed, the second control module 5B ends the reset process of the programmable gate array 1, the peripheral circuit 3 and the control section 7 by the reset process signal 12. When the configuration of the programmable gate array 1 is completed, the programmable gate array 1 is notified of that fact by the configuration end display signal 13 to the control unit 7. As a result, the control unit 7 monitors the completion of the configuration of the programmable gate array 1. Therefore, if the reset of the peripheral circuits 3 and the like is finished while the programmable gate array 1 has not finished the configuration, the control unit 7 notifies the upper device 9 of that fact,
Prevent malfunction.

The above is the outline of the apparatus of the present invention, and the more specific configuration of the present invention will be described below with reference to the block diagrams of FIG. FIG. 2 shows a specific example block diagram of an arithmetic circuit suitable for implementing the apparatus of the present invention. The device of the present invention is used for such an arithmetic circuit 20. The arithmetic circuit 20 is provided, for example, in an exchange of a communication network.
Here, a receiver 25-1, which receives a signal from the main signal system transmitter 23, LSIs 26-1 and 27-1, an FPGA.
1-1, LSI 28-1, and driver 29-1 are provided. Further, the receiver 25-2, the LSI 28-2, and the FP that process the signal received from the main signal system reception unit 24.
The GA 1-2, the LSI 27-2, the LSI 26-2, and the driver 29-2 are provided.

The operation of the arithmetic circuit 20 is controlled by the control unit 7, and the control unit 7 exchanges information for the operation of the arithmetic circuit 20 with a host device (not shown). FPG
CON4-1 and CON4-2 storing environment setting data are connected to the A1-1 and the FPGA 1-2, respectively. These FPGAs 1-1 and 1-2 are in a mode in which reconfiguration is started when the configuration fails. Also,
FPGA1-1 or FPGA1 during configuration
-2 has an indefinite output signal level, so pull-up resistor 22
-1 and 22-2 are provided respectively.

In the arithmetic circuit 20, the data received from the main signal system transmitting section 23 and the main signal system receiving section 24 are processed by the respective LSIs in accordance with the format thereof, and the result is output from the control section 7 to the higher order. The device is notified.
For example, in the case of a switchboard, F is a circuit for processing data so as to suit the protocol and various conditions.
PGA is customized by configuration. Note that the FPGA1- of the arithmetic circuit 20
A reset sequence generation circuit 22 is provided to perform reset processing of 1, 1-2 and other peripheral circuits. The reset processing device of the present invention includes the reset sequence generation circuit 22, FPGAs 1-1 and 1-2, and peripheral circuits thereof.

FIG. 3 is a block diagram of a specific reset processing device according to the present invention. The device shown in the figure has two power supply monitoring modules 31 and 32 and two FPGAs 33-
1, 33-2. Here,
Illustrations are omitted except for circuit blocks necessary for explaining the present invention. Therefore, in this figure, the CON4-1 and 4 shown in FIG.
Circuits such as -2 and peripheral circuits are not shown.

The power supply monitoring module 31, shown in this figure,
32 operates as the first control module and the second control module shown in FIG. 1, respectively. FPGA33-
Reference numerals 1 and 33-2 are programmable gate arrays included in the arithmetic circuit to be reset. This number may be one, or may be any number of two or more. Each of the power supply monitoring modules 31 and 32 has VsSENSE and RES
IN, CT, Vref and CLR terminals are provided. For VsSENSE terminal and RESIN terminal,
A voltage of + 5V is input from the power supply circuit 6 shown in FIG. CT
The capacitor C1 that forms the timer circuit 7A described with reference to FIG. 1 is connected to the terminal.

A capacitor C3 for generating a reference voltage is connected to the Vref terminal. Further, the CT terminal of the power supply monitoring module 32 is connected to the capacitor C2 corresponding to the timer circuit 7B provided in the second control module 2 shown in FIG. Further, a capacitor C4 for generating a reference voltage is connected to the Vref terminal.
The capacitor C1 is 1.5 μF, and the capacitor C2 is 4 μF.
4μF, capacitor C3 and capacitor C4 0.1μ
Selected as F. In addition, between the VsSENSE terminal and the CLR terminal of the power supply monitoring modules 31 and 32 are 4.
They are connected by 7KΩ pull-up resistors R1 and R2. For example, such power supply monitoring modules 31, 32
When a module of TL7705CPS-B (manufactured by TI) is used, the following signal is output from the CLR terminal.

FIG. 4 shows an operation explanatory diagram of the power supply monitoring module 31. In the graph shown on the upper side of the figure, the vertical axis represents the power supply voltage and the horizontal axis represents time. In the lower graph, the vertical axis represents the output level of the CLR terminal and the horizontal axis represents time. Here, when a power supply voltage is applied to the VsSENSE terminal of the power supply monitoring module 31 and the power supply voltage rises after a lapse of time as shown in the upper side of FIG. 4, when the power supply voltage reaches 3.5V at time t1,
A low level signal is output from the CLR terminal. When the power supply voltage reaches 4.5 V at time t2, the output level of the CLR terminal is switched to the high level at time t3 after a lapse of time corresponding to the capacitance of the capacitor C1. If the value of the capacitor C1 is selected to be 1.5 μF, the response time from time t2 to time t3 is about 10 milliseconds. The power supply monitoring modules 31 and 32 are
This is a module that generates such a power-on reset signal.

FIG. 5 shows an operation explanatory diagram of the power supply monitoring module 32. Each graph in this figure is exactly the same as the graph shown in FIG. C of power supply monitoring module 32
The capacitance of the capacitor C2 connected to the T terminal is 44μ
Since it is selected as F, after the power supply voltage reaches 4.5V at time t2 in the figure, the response time is 500 milliseconds and CL
Raise the output level of the R terminal to high level. That is,
The response time is from time t2 to time t4.

Returning to FIG. 3 again, the two Fs shown in FIG.
The PGAs 33-1 and 33-2 include, for example, EPF8118.
8 (manufactured by Altera) is used. This programmable gate array is provided with three terminals RST, nCNF and nSTAT. When the signal input to the nCNF terminal rises from low level to high level,
The rising edge is detected and the CON shown in FIG. 2 is detected.
4-1 and 4-2 are accessed to read environment setting data. In this way, the operation starts so that the configuration is started.

When the signal input to the RST terminal is switched from low level to high level, reset is executed and the set operation can be started. nSTA
The T terminal normally outputs a high level signal, and if the configuration fails, the output is set to a low level for several microseconds. Then, the FPGAs 33-1 and 33-
2 then releases and starts reconfiguration. Therefore, each FPGA 33-1 and 3
By sending the output of the nSTAT terminal 3-2 to the control unit, the control unit 7 shown in FIG. 2 detects the end of the configuration of these programmable gate arrays. In the case of EPF81188, one configuration time is 100 milliseconds. Reconfiguration requires the same time.

Here, the power supply monitoring module 3 shown in FIG.
The CLR terminal of No. 1 is connected to the nCNF terminal of the FPGA 33-1. Further, it is also output to the nCNF terminal of the FPGA 33-2. Therefore, FPGAs 33-1 and 3
The start of configuration 3-2 is controlled by the power supply monitoring module 31. On the other hand, the CLR terminal of the power supply monitoring module 32 is the R of the FPGAs 33-1 and 33-2.
In addition to being connected to the ST terminal, it is connected to the reset terminal of each LSI (not shown) and the reset terminal of the controller. Each LSI and control unit in FIG. 3 is the LSI 26-1 shown in FIG.
28-2 and the control unit 7.

Next, the operation of the apparatus shown in FIG. 3 will be described.
First, when the power is turned on and the power supply voltage rises,
As described with reference to FIG. 5 and FIG. 5, the output of the CLR terminal of the power supply monitoring module 31 is low level from time t1 to t3 and rises to high level at time t3. this is,
The inputs to the nCNF terminals of the FPGAs 33-1 and 33-2 start the configuration of these programmable gate arrays. Then, after this configuration is completed, that is, about 500 milliseconds after the time t2, the output of the CLR terminal of the power supply monitoring module 32 rises from the low level to the high level. This signal is
Since the signals are input to the RST terminals of the FPGAs 33-1 and 33-2, the FPGAs 33-1 and 33-2 are reset at this point. At the same time, the peripheral circuits of each LSI and the control unit are reset. Therefore, as shown in FIG.
LSI 28 that receives the outputs of FPGA 1-1 and 1-2
-1 and 27-2 do not output an uncertain signal because they start operating after the FPGAs 1-1 and 1-2 are reset.

By the way, the FPGA 33- shown in FIG.
1, 33-2 may fail the configuration due to some noise or the like during the configuration execution. In this case, reconfiguration is executed again. However, if the reset of the peripheral circuits is completed during this period, an indeterminate signal is output to other circuits. Therefore, when the response time of the power supply monitoring module 31 is set to about 10 milliseconds, the response time is set so that the CLR terminal output of the power supply monitoring module 32 rises at time t4, which is a time sufficiently long after the rising time t3. We have selected. FIG. 6 shows a diagram for explaining the relationship between the response times.

That is, the configuration is started at time t3, and if this fails, the reconfiguration is executed. In this example, it is assumed that the configuration is completed by two reconfigurations. In this case, 100 per configuration
If it takes milliseconds, the configuration will be completed approximately 300 milliseconds after the time t3. The time t4 when the output of the CLR terminal of the power supply monitoring module 32 rises is selected after a time sufficiently longer than this.
In this example, when the configuration time is tc and the time from time t3 to t4 is T, T ≧ n ×
Set to tc. This n is the number of times of configuration including reconfiguration.

By selecting the timers of the power supply monitoring module 31 and the power supply monitoring module 32 in this way, it is possible to reliably control the resetting of the peripheral circuits after the configuration is completed. Note that the configuration may not end even if the reconfiguration is performed more than the limited number of times for some reason. In this case, resetting of other circuits may end earlier, and an indeterminate signal may be output. Therefore, as shown in FIG. 3, the outputs of the nSTAT terminals of the FPGAs 33-1 and 33-2 are sent to the control unit. When the control unit receives a signal for reset control output from the power supply monitoring module 32 without detecting the end of reconfiguration, the control unit notifies the upper device of that fact. As a result, the host device can perform control so as not to accept an uncertain signal.

FIG. 7 shows a block diagram of a modification of the reset processing device. The programmable gate array receives the environment setting data from CON4-1 and 4-2 shown in FIG. 2 and connects the logic gates. However, an initial value may be set by the control unit for the programmable gate array. When such an initial setting is performed, if the peripheral circuits operate until the initial setting is completed, an uncertain signal may still be output. The device shown in FIG. 7 is configured to control the reset sequence in such a case.

The power supply monitoring modules 31, 3 shown in this figure
2. The FPGAs 33-1 and 33-2 are the same as those shown in FIG. In the device of this modification, the output of the CLR terminal of the power supply monitoring module 32 is set to the
It is configured to be connected to the RST terminal of the GA 33-1 and output this to the RSTIN terminal of the control unit 7. Further, the output of the RSTOUT terminal of the control unit 7 is FP
It is connected to the RST terminal of GA33-2 and each L
It is connected to the reset terminal of SI.

FIG. 8 shows an operation explanatory diagram of the apparatus of the modified example shown in FIG. The configuration of the graphs shown above and below is similar to the graphs shown in FIG. 4 and FIG. And FIG.
The CLR terminal outputs of the power supply monitoring modules 31 and 32 shown in FIG. 4 are as shown in FIGS. 4 and 5. First, when the power is turned on and the power supply voltage rises, the voltage becomes 3.
When the voltage reaches 5V, the CLR output of the power supply monitoring modules 31 and 32 becomes low level.

At time t3 in the figure, the output of the CLR terminal of the power supply monitoring module 31 rises to the high level, and the FPGA
The configuration of 33-1 and 33-2 is started. Then, at time t4 after this configuration is completed, the output of the CLR terminal of the power supply monitoring module 32 rises from low level to high level. As a result, the FPGA 33-1 is reset. That is, in this modification, the FPGA 33-1 is first reset and the control unit 7 is notified that the reset has been performed. At this point, the control unit 7 has the FPGA 33.
Initialize -1. Then, at the time t5 after the initialization is completed, the signal for executing the reset is output from the terminal RSTOUT. This allows the FPGA33
-2 and each LSI are reset.

In this way, the control unit 7 controls one of the FPGs.
FPGA33-2 while initializing A33-1
And the reset signal of other peripheral circuits can be made to wait. Therefore, in this case as well, it is possible to prevent the indeterminate signal from being output from the peripheral circuit. As described above, the power supply monitoring modules 31 and 32 can freely change the waiting time setting for configuration by selecting the values of the capacitors C1 and C2 that form the timer. In the above case, the FPG
An example of performing initial settings for A33-1 has been shown.
Similar control can be performed even when initial setting is performed on an LSI provided in another peripheral circuit including a GA. That is, when initializing an arbitrary circuit, it is possible to perform control such that the resetting of only the circuit that performs the initializing is preceded and the resetting of the other circuits is terminated after the initializing is completed.

[Brief description of drawings]

FIG. 1 is a schematic block diagram of an apparatus of the present invention.

FIG. 2 is a block diagram of a specific example of an arithmetic circuit.

FIG. 3 is a block diagram of a specific example of a reset processing device.

FIG. 4 is an operation explanatory diagram of the power supply monitoring module 31.

FIG. 5 is an operation explanatory diagram of the power supply monitoring module 32.

FIG. 6 is an explanatory diagram of a relationship between response times.

FIG. 7 is a block diagram of a modification of the reset processing device.

FIG. 8 is a diagram illustrating the operation of the modified apparatus.

[Explanation of symbols]

 1 Programmable Gate Array 3 Peripheral Circuit 4 Environment Setting Data Memory 5A First Control Module 5B Second Control Module 6 Power Supply Circuit 7 Control Unit 7A, 7B Timer Circuit 9 Upper Device

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Eiji Fusaki 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd.

Claims (6)

[Claims] 1. A programmable gate array programmable by configuration and its peripheral circuits are reset, and a first control module for activating the configuration of the programmable gate array and ending the configuration. A second control module is provided for setting a predetermined time required for the setting, and after the predetermined time has elapsed from the start of the configuration, executing the reset processing of the programmable gate array and its peripheral circuits. Reset processing device for arithmetic circuit. 2. The first control module and the second control module according to claim 1, monitoring the rise of the power supply voltage, outputting a control pulse when the power supply voltage exceeds a certain value, and A reset processing device for an arithmetic circuit, comprising a timer circuit capable of selecting a response time from when the control pulse is output after exceeding a certain value. 3. The control unit according to claim 1, further comprising a control unit for monitoring the status of the programmable gate array and notifying the external circuit when the programmable gate array has not completed the configuration even after the peripheral circuit has been reset. A reset processing device for an arithmetic circuit characterized by the above. 4. The method according to claim 1, wherein after the first control module starts the configuration of the programmable gate array, the second control module ends the reset processing of the programmable gate array and its peripheral circuits. A reset processing device for an arithmetic circuit, characterized in that the fixed time is set to be equal to or longer than a time at which reconfiguration can be repeated once or more after the initial configuration. 5. The first control module according to claim 1, which activates the configuration of all programmable gate arrays when a programmable gate array which requires further initialization after the configuration is completed, and its configuration. A second control module that sets a predetermined time required to end the configuration, and executes the reset process of the programmable gate array that requires the initial setting after the predetermined time has elapsed from the start of the configuration; A control unit which receives the output of the control module No. 2 and executes the initialization of the programmable gate array, and after the initialization, executes the reset process of the peripheral circuit including the programmable gate array which does not require the initialization. Equipped with Reset processing unit of the arithmetic circuit according to claim. 6. An arithmetic circuit in which a circuit that requires initial setting after reset processing and another circuit that does not require initial setting coexist, for a circuit that requires initial setting after reset processing, The control module that executes the reset process and the circuit that requires the initial setting after receiving the output of this control module perform the initial setting, and after the initial setting, A reset processing device for an arithmetic circuit, comprising a control unit for executing reset processing of the circuit.