JPH09198272A - Processor for emulation and emulator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain the emulation of plural CPUs having respectively different functions by an emulator based upon a user's selection by providing the processor with a selector circuit capable of selectively driving plural CPUs and executing the emulation of plural CPUs. SOLUTION: When CPUs 1, 2 in an operating state are transmitted to a low power consumption state by executing a SLEEP instruction or the like, the CPUs 1, 2 are turned to a stop state by a stop signal outputted from a system controller 16. When a low power consumption state releasing signal is outputted, the CPU selected by a CPU selection signal out of the CPUs 1, 2 is turned to an operating state by releasing the stop signal. An emulation interface 18 selectively inputs CPU status signals or the like from the CPUs 1, 2 and executes bus control. A selector circuit SEL1 selects the input of control signals outputted from the CPUs 1, 2 based upon a CPU selection signal outputted from an emulation control circuit 19.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an emulator constituting a development device for a semiconductor integrated circuit device, a microcomputer or a microcomputer application system, for example, an emulation processor for a microcomputer and such an emulation processor. It is related to the technology effectively used for the emulator.

[0002]

2. Description of the Related Art In order to develop an application system using a single-chip microcomputer, a so-called in-circuit emulator microcomputer development device is used. The microcomputer development device includes a system development device such as a so-called personal computer and an application system (user system) under development.
It has a function as a debugger, acting as a substitute for the function of a single-chip microcomputer (target microcomputer) that should be installed in the application system connected between the and, and supports the development of software or application systems. is there. In this microcomputer development device, an emulation processor for evaluation called an evaluation chip corresponding to the above single chip microcomputer outputs the function including the function of the single chip microcomputer and the internal state of the microcomputer. Providing a dedicated function for controlling the operation of the microcomputer facilitates the development of the microcomputer development device. For the microcomputer development device or the in-circuit emulator, see, for example, "LSI Handbook" P562, issued by Ohmsha, Ltd. on November 30, 1984.
And P563, and for an emulation processor, see, for example, JP-A-63-106.
No. 840 or the like is well known, and detailed description thereof will be omitted.

The function dedicated to the emulation processor is to stop the CPU when a central processing unit (hereinafter referred to as CPU) accesses a predetermined address,
It has a function of transferring control to the emulator side (break), a program dedicated to emulation at the time of such a break, a function of monitoring a user's memory, and a function of changing a memory to be used.

Further, a status signal or the like is output to the address bus or data bus, and further to the CPU, so that the operating state of the CPU can be analyzed.

An example of improving the development period and development efficiency by making it possible to select a microcomputer that can be supported by the emulation processor mounted on the emulator is disclosed in Japanese Patent Laid-Open No. 3-27183.
4, JP-A-6-150026 and the like. In such an example, the development efficiency of the emulation processor and the emulator can be improved, and the emulator can be promptly provided to the user. On the other hand, an example in which the address space is expanded while maintaining the compatibility of CPUs is disclosed in Japanese Patent Laid-Open No. 4-33315.
3 and JP-A-5-241826.

[0006] The memory capacity of the microcomputer is increased due to the higher function of the system in which the microcomputer is incorporated and the shift from the control by the microcomputer of a plurality of chips to the control by the microcomputer of a single chip due to the higher performance of the microcomputer. doing. Along with this, the range of the capacity of the built-in memory required for the microcomputer is expanding. For example, it is 32 kB to 128 kB. That is, depending on the application system, even if the main functions of the CPU are the same and the connected peripheral devices are also commonly used, those having different built-in memory capacities may be optimal.

For example, as described in JP-A-4-333153 and JP-A-5-241826, if an address space of 64 kB or less is sufficient, a relatively small register configuration and relatively few addressing modes and the like. CPU is sufficient. On the other hand, if the address space is 64 kB or more, the CPU must have a relatively large register configuration and a relatively large number of addressing modes. If the memory capacity may be small, the CPU having a relatively small built-in memory capacity may be used to reduce the logical / physical scale of the microcomputer and reduce the manufacturing cost.

If these microcomputers can be evaluated by one emulator and emulation processor, the development efficiency can be improved and the development device can be provided to the user as quickly as possible. Moreover, the user can conveniently select the memory capacity based on the result of the program development and select the CPU based on the result without changing the emulator.

[0009]

The extensibility of the conventional emulator is that the peripherals of the CPU are selectable or the compatibility of the CPUs differing only in the size of the address space is maintained. The CPUs were compatible only with those having the same function.

An object of the present invention is to provide a plurality of Cs having different functions in one emulator based on a user's selection.
It is intended to enable PU emulation, to improve the development efficiency of a microcomputer application system, to promptly provide a user with a system development device, and to improve usability.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0012]

The outline of the representative one disclosed in the present application will be briefly described as follows.

That is, a part or all of the object code set, internal status signals, interfaces, and the like are made common, and a plurality of different CPUs having the same operation timing are built in to enable selective operation. By doing so, an emulation processor capable of emulating a plurality of CPUs is realized.

Further, it is preferable that the interrupt control for the plurality of CPUs is also made common, and each CPU is configured such that one of them is the main and the other CPU is a subset thereof. Further, if the bus control is shared, the CPU to be emulated can be regarded as a CPU that operates exclusively, and when a bus master such as a direct memory access controller is built in as a peripheral module, these so-called bus arbitration control and The chip size can be reduced by sharing the control logic and simplifying the system development. It is advisable to make the interface with the peripheral module and the memory common.

Further, it is preferable that the plurality of CPUs be made selectable by a control flag or a control bit of a control register, and after the control bit is set, reset is performed so that the information of the control bit is reflected. Further, it is preferable that the CPU operating after the reset can be designated by a control signal from the outside.

According to the above-mentioned means, different CPUs are built in, and any one of the CPUs can be selected and emulated, so that the development apparatus of the microcomputer application system can be provided promptly and the development period can be shortened. In addition, the user can freely select the CPU, which improves usability.

Further, by making the bus control, interrupt control and emulation interface signal of the CPU common, the development efficiency of the emulation processor and emulator can be improved.

[0018]

FIG. 1 is a block diagram of an emulation processor to which the present invention is applied. Although not particularly limited, the emulation processor 10 of this embodiment is formed on one semiconductor substrate such as single crystal silicon.

The emulation processor 10 of this embodiment is a microprocessor C to be emulated.
PU1 and CPU2, ROM (read only memory) 11, RAM (random access memory) 1
2. A data transfer controller (DTC) 13 that performs data transfer, a bus controller (BSC) 14 that performs bus switching and control of the bus use right, an interrupt controller 15 that performs interrupt control for the CPU, CPUs 1, C
A system controller 16 for controlling the entire chip such as a stop signal for the PU 2, a user interface 17 for the emulation processor 10 to transmit and receive signals to and from a user system, and a signal for transmission and reception to and from other devices constituting the emulator. It is composed of functional blocks or modules such as an emulation control circuit 19 having an emulation interface 18 for transmitting and receiving. These functional blocks are the internal bus I
AB, IDB; PAB, PDB are connected to each other. Further, although not shown, a clock oscillator (CPG) and the like are also included.

The user interface 17 is a buffer BUF or timer connected to a bus on the user system,
Serial communication interface (SC
I), A / D converter (A / D), input / output port I / O, and the like. The interrupt request from the user system is supplied to the interrupt controller 15 via the input / output port I / O.

The CPU 1 and the CPU 2 are designated in a stopped state / operating state according to a stop signal output from the system controller 16. Further, based on the CPU selection signal output from the emulation control circuit 19,
Either one of the CPU 1 and the CPU 2 is always in the stopped state. That is, the CPU1 receives the logical sum signal of the CPU stop signal and the CPU selection signal, and the CPU2 receives the C signal.
A logical sum signal of the PU stop signal and the inverted signal of the CPU selection signal is given. In this embodiment, although not particularly limited, when the CPU selection signal is at "0" level, the CPU2
When the CPU is stopped and the CPU selection signal is at "1" level, CP
U1 is fixed in a stopped state.

When the CPUs in the operating state execute the SLEEP instruction or the like and transit to the low power consumption state, both CPUs are stopped by the stop signal output from the system controller 16. When the low power consumption state release signal is generated, the C selected by the CPU selection signal
The PU stop signal is released and the PU enters the operating state. The emulation interface 18 selectively receives a CPU status signal or the like output from the CPU 1 or the CPU 2 to control the bus operation. Any C
The selection circuit SEL1 selects whether to input the control signal output from the PU, based on the CPU selection signal output from the emulation control circuit 19. Further, the emulation interface 18 selectively supplies the control signal to the CPU1 and the CPU2.

The bus controller 14 is composed of the CPU 1 and the CP.
Control signals (read, write, size, etc.) output from U2 are selectively input to control bus operation. The CPU output from the emulation control circuit 19 is selected as to which of the CPUs outputs the control signal.
This is performed by the selection circuit SEL2 based on the PU selection signal. Further, the bus controller 14 forms a control signal (acknowledge signal, wait signal, etc.) to generate the CPU 1,
Supply to CPU2.

When the address space of the CPU 1 is larger than the address space of the CPU 2, the upper bits of the address that the CPU 2 does not output are regarded as 0 or sign extension, for example. If there is an addressing method of the number of bits corresponding to the address space of the CPU 2 in the addressing mode of the CPU 1, it is preferable to follow the address extension method at this time. For example, the address space of CPU1 is 1
When the address space of the CPU2 is 6 Mbytes and the address space of the CPU2 is 64 kbytes, the CPU1 has a so-called absolute address mode of the number of bits (16 bits) corresponding to the address space of the CPU2. In this case, the higher 8 bits of the 24-bit address are used.
The bit is sign-extended and has the same content as bit 15. The part of the CPU 2 where the address does not exist is sign-extended. It is preferable that the bus controller 14 has such an address extension function.

The interrupt controller 15 includes an interrupt signal from the user system, a DMA controller in the user interface 17, a timer, a serial communication interface (SCI), and an A / D converter (A / D).
D), an interrupt signal from an input / output port (I / O) or the like is input, and a control signal (interrupt request signal, vector number, etc.) is supplied to the CPU1 and CPU2. Further, the interrupt controller 15 selectively receives control signals (mask signal, interrupt clear signal, etc.) output from the CPU 1 and CPU 2, and performs control corresponding thereto. The selection of which CPU the control signal output from is input is performed by the selection circuit SEL3 based on the CPU selection signal output from the emulation control circuit 19.

As described above, the system controller 16,
The interrupt controller 15 and the bus controller 14 are C
Commonly used by PU1 and CPU2. For this reason, it is desirable to make the interfaces of the CPU 1 and the CPU 2 common. That is, the types of signals input to and output from the two CPUs are the same, and the timings are also the same. Alternatively, one CPU may be a subset of the other CPU. Here, the subset means that one CPU has all the functions of the other CPU and also has other functions.

Table 1 shows an example of the types of signals between the functional blocks or modules in the emulation processor 10 of FIG. 1 and the functions of the signals. In Table 1, the number of bits of the internal bus IAB is CPU1.
It is common to the CPU1 and the CPU2 except that it is set to 24 bits for the CPU and 16 bits for the CPU2. In Table 1,
For example, CPUCKSTP is a signal corresponding to the stop signal in FIG. In Table 1, a signal with N at the end means that it is a low active signal (“0” is a valid level). Reference symbol CPG is a clock pulse generator, SYSC is a system controller,
BSC is a bus controller, ASE is an emulation control circuit, INT is an interrupt controller, and PORT is a port of a user interface and an emulation interface.

[0028]

[Table 1]

Further, for example, BCMD, BUSRDY, C
Bus control signals such as PUACKN may be shared with other bus masters such as the data transfer controller 13. In that case, the response signal of the data transfer controller 13 corresponding to CPUACKN is DTCA.
It becomes like CKN. By doing so, the system controller 16, the interrupt controller 15, the bus controller 14, etc. need only be developed for one CPU, and the development efficiency can be improved. By reducing the development period of the emulation processor,
The emulator can be promptly provided to the user of the microcomputer, which can contribute to the early development of the user system.

Further, since the control circuits such as the system controller 16, the interrupt controller 15 and the bus controller 14 are shared and only the logic for one CPU is built in, the logical circuit of the emulation processor is
It is also possible to reduce the physical scale and reduce the manufacturing cost.

On the other hand, any CP in the embodiment of FIG.
The CPU selection signal for setting U to the operating state is configured to be designated by a predetermined control bit in the control register MCUCR provided in the emulation control circuit 19. This control register MC
The UCR is allowed to change each time a reset signal is input. When there are a plurality of reset signals, the change may be permitted when one or more predetermined reset signals are input. The reset includes a power-on reset and a manual reset, or a break reset and a user reset. The control register MCUCR in the emulation control circuit 19 may be provided with a control bit for controlling break control, bus control, module selection control, or the like, or may be provided in another control register.

The microcomputer to be emulated is selected by the setting in the module selection register as described above, and the emulation control circuit 1
An emulation processor CPU that should operate on 9
1, it forms and supplies a control signal for designating the CPU 2, and supplies it to a module select circuit included in the bus controller (BSC) 14 and other peripheral module parts. For example, the emulation control circuit 19 also supplies control signals for designating the number of usable channels of a timer or SCI, the number of valid IO ports, and the capacity of the internal ROM 12 and RAM 13. A module which should be unselected, that is, whose operation is prohibited, is configured so that operations such as read / write are suppressed by fixing the module selection signal to the inactive state.

Further, the emulation processor is configured so that it is possible to specify the prohibition of some of the functions built therein and the change of the operation, and one emulation processor emulates a plurality of microcomputers. You may allow it.

FIG. 2 shows a schematic block diagram of an example of a CPU selection signal generation circuit provided in the emulation control circuit 19.

Although not particularly limited, the CPU selection signal is designated by setting a predetermined bit CPUS in the emulation-dedicated control register MCUCR which can be read / written only in the break mode.

The emulation-dedicated control register MCUCR can be read / written only in the emulation program execution state, so-called break mode. The bits forming the control register are each formed of, for example, a D-type flip-flop. FIG. 2 shows a flip-flop FF1 constituting the CPU selection bit CPUS, and a predetermined bit signal of the data bus is input to the data input terminal D of the flip-flop FF1. Further, at the clock input terminal C, a BRKAK signal indicating a break mode and an AND gate G1 that performs a logical product of a decode signal from an address decoder that detects that the address designated by the control register is applied, and the AND gate G1.
AND gate G2 which takes the logical product of the output signal of the above and the write signal. That is, when the address designated by the control register is applied in the break mode and the write signal is at the effective level, the state of a predetermined bit on the data bus is written to the CPU selection bit CPUS.

Further, although not particularly limited, the output terminal Q of the flip-flop FF1 has a CP on the data bus.
A buffer BF1 for outputting the contents of the U selection bit CPUS is connected, and this buffer BF1 is connected to the above A
It is controlled by the output signal of the AND gate G3 which takes the logical product of the output signal of the ND gate G1 and the read signal. That is, the contents of the CPU selection bit CPUS are output onto the data bus when the address designated by the control register is applied in the break mode and the read signal is at a valid level.

On the other hand, the output of the flip-flop FF1 constituting the CPU selection bit CPUS is given to each part of the microcomputer via the second flip-flop FF2. The flip-flop FF2 is also composed of a so-called D-type flip-flop, and the reset signal is input to the clock terminal C. Therefore, even if the CPU selection bit CPUS is rewritten and the output of the flip-flop FF1 changes, the output of the flip-flop FF2 does not change until the reset signal is applied. Although not particularly limited, the reset signal provided to the flip-flop FF2 may be a break reset signal.
Although not particularly limited, an output buffer BF2 and a monitor terminal MP are provided so that the CPU selection signal output from the flip-flop FF2 can be externally monitored.

Although the embodiment in which the CPU selection is designated by the register has been described above, the CPU selection may be made by the external terminal input instead of the register designation. FIG. 3 shows such an embodiment. In this embodiment, the CPU selection bit CPUS
The input to the data terminal D of the flip-flop FF1 constituting the above is changed to a signal input from the external terminal P via the input buffer circuits (input protection circuits Q3 and Q4 and inverters Q1 and Q2). Further, the input circuit is provided with a pull-up resistor R, and when the external terminal P is released, the CPU 2 is selected, and when the external terminal P is connected to the lead L such as a ground (ground) terminal, CP
U1 is configured to be selected. The external terminal P does not need to be provided as a dedicated external terminal of the emulation processor as the semiconductor integrated circuit device, and may be shared with the leads such as adjacent ground terminals as shown in FIG. May be.
Also, input of external terminal, output of register, or C
The PU selection signal may be configured so as to be formed by changing the wiring of the semiconductor integrated circuit device, and the "1" level / "0" level may be fixedly generated.

When the fixed designation is used, the emulation processor or emulator cannot be arbitrarily selected and used for emulation of the two CPUs, but substantially one type of semiconductor integrated circuit is used. By developing this, and by changing the bonding and wiring, it is possible to obtain an emulation processor corresponding to two types of CPUs, so that the effect of shortening the development period can be obtained.

It is also possible to provide a means for displaying which CPU is selected. The contents displayed by the display means are controlled by the control register MCU.
It may be obtained by reading another bit of CR, or may be output from an external terminal.

Tables 2 to 4 show a list of functions of control signal input / output terminals provided in the emulation interface 18. In Tables 2 to 4, the signals with # at the end are row active (“0” is a valid level).
It means that the signal is.

[0043]

[Table 2]

[0044]

[Table 3]

[0045]

[Table 4]

FIG. 4 shows an overall schematic configuration of the emulator and the system development apparatus including the emulator.

Connector 2 at the end of the interface cable 21 extended from the emulation processor 10
2 is attached to the CPU socket 31 on the application system (user system) 30 instead of the single-chip microcomputer. Emulation processor 1
0 is the connector 22 and the interface cable 2
The user interface 17 (see FIG. 1) is used to input and output signals to and from the application system 30 via the user interface 1.

Although not particularly limited, the user system 30 has a user bus and a user memory connected thereto. The user memory is read / written according to the user strobe signal output from the emulation processor 10 and supplied via the interface cable 21. The reset signal generated by the user system 30 is supplied to the emulation processor 10 as the user reset signal URS via the interface cable 21. This user reset signal URS
Together with the reset signals SRS and ERS on the emulator side are input to the reset terminal RES of the emulation processor via the OR gate G4.

As the reset signal on the emulator side, a system reset signal SRS for resetting the entire emulator when the power of the emulator is turned on, and an emulation reset for resetting the emulator 20 by a command from the console of the host computer 40 are used. There is a signal ERS. The emulation reset gives a user reset based on information input from the host computer 40 as a command of the emulator. The emulator reset signal ERS is input to the emulation processor 10 as a wait signal ASEWAIT through the delay circuit DLY. As a result, the contents of the flip-flop FF1 in the circuit of FIG. 2 are moved to FF2 in the circuit of FIG. 2 to select the CPU only when the system reset signal of the emulator is input when the wait signal ASEWAIT is at the low level, and the wait signal ASEWAIT Even if the user reset signal URS is input at the high level, the CPU is not selected.

On the other hand, the emulation processor 10
Is connected to the emulation bus 23 via the emulation interface 18. The emulation bus 23 includes status signals, control signals, etc., which are not shown. Using the emulation bus 23, the emulation processor 10 outputs a state according to the internal states of the application system and the emulation processor, and various control signals for emulation are input to the emulation processor 10. It The emulation mode terminal (not shown) of the emulation processor 10 is fixed to the power supply level, and the emulation mode is set inside the emulation processor.

Further, although not particularly limited, the emulation bus 23 is composed of a RAM for substituting a memory built in the application system or the target microcomputer, instead of the emulation memory 24.
Is connected. In the emulation memory 24,
There are a high-speed memory that acts as a substitute for the built-in ROM and a lending memory that is released to the user. When creating a user program, it is often designed with ample capacity,
It may not fit in the storage capacity of the built-in ROM. Even in such a case, the user can use the rental memory of the emulator to substantially expand the program memory,
You can start debugging. As the debugging progresses, the program can be optimized so that it fits in a predetermined capacity. The rental memory does not necessarily need high speed because of its characteristics. From the low-speed memory of the emulation memory 24, a wait request signal ASEWAIT that causes the emulation processor 10 to wait for the reading of data is output. An emulation program is also stored in the emulation memory 24.

Further, the emulation processor 10
Monitor the control status and emulation bus status of
When the state reaches a preset state, the break control circuit 25 for inputting the emulator-specific interrupt to stop the execution of the user program by the CPU and transition to the emulation program execution state (break) And a real-time trace circuit 26 for sequentially storing addresses and data, and further control information given to the emulation bus based on a signal indicating a read operation or a write operation of the CPU, a signal indicating an instruction read operation, etc. are connected to the emulation bus 23. Has been done. The emulation memory 23, the break control circuit 25, and the real-time trace circuit 26 are mutually connected by the emulation bus 23. The break control circuit 25 supplies the break signal ASEBRK to the emulation processor 10.

On the other hand, the emulation memory 24,
Break control circuit 25, real-time trace circuit 26
Is connected to the control processor 28 via the control bus 27 and is controlled by the control processor 28. The control bus 27 is connected to the emulation processor control circuit, and is also connected to the host computer 40 via the host interface circuit 29, although not particularly limited thereto.

When the program input from the host computer 40 is transferred to the emulation memory 24 and the emulation processor 10 reads the program to be placed on the built-in ROM, the program on the emulation memory 24 is read. In addition, break conditions and real-time trace conditions can be given from the host computer 40.

FIG. 5 shows an outline of the operation procedure of the emulator. After the power is turned on, first, a reset process for the entire emulator is executed (step S1). Next, a process for setting the CPU selection bit CPUS of the control register MCUCR to select the CPU is performed (step S
2). Which CPU operates as the emulation processor is input from the host computer 40, and is set in the module control register MCUCR via the host interface 29, the control processor 28, and the emulation memory 25. Module selection is also done.

Since the CPU selection bit is composed of flip-flops, it is undefined immediately after the power is turned on. Therefore, the initialization program such as register setting after the first reset can be executed by both CPU1 and CPU2. Common instructions). The address is arranged in a range accessible by any CPU. When sign-extending the upper address bits of the CPU 2, the address range is, for example, in hexadecimal notation, H'000000 to H'0 of the address space of the CPU 1.
07FFF, H'FF8000 to H'FFFFFF. Place the specified address of the emulator dedicated control register within the above range.

After the CPU is selected and the lending memory and various control registers are set (step S3),
After performing the reset process (step S4) for resetting the user system, the emulation program is executed (step S5). If there is a command to execute the user program during execution of the emulation program, the execution of the emulation program is stopped and the process proceeds to execution of the user program (steps S6-S7).

Here, an example of a method of selecting the microcomputer to be emulated which is performed before the operation of the emulator is started will be described.

First, ":" indicating a command input waiting state is displayed on the screen of the display device of the host computer 40. In this state, MODE; C is input and the execution key is operated in order to select the microcomputer to be emulated. Then, the emulator displays a list of microcomputer types and the like as a selection menu of microcomputers that can be emulated. Here, the user inputs the desired microcomputer number. For example, as a microcomputer with a built-in CPU1, 1: MCU1A, 2: MCU1B,
3: MCU1C, 4: MCU1D, 5: MCU1E,
6: Like MCU1F, and as a microcomputer incorporating CPU2, 7: MCU2A, 8: MCU
2B, 9: Enter "1" to designate MCU1A when displayed like MCU2C.

Then, the emulator performs a CPU selection, a memory capacity selection, a built-in peripheral function selection, a package analysis, etc. based on the information registered internally in advance corresponding to the input number. , Give a program to the CPU inside the emulation processor, and
Write to a predetermined register such as UCR. In addition,
In selecting the microcomputer, the format and the like may be selected as a menu, or the type of the CPU, the memory capacity, and the like may be displayed so that the user can individually select.

In addition to the above microcomputer selection, emulator setting processing such as operation mode setting such as extended mode and single chip mode is performed, and the user program is executed based on commands input from the host computer 40. Is requested, the emulation processor detects it in step S6 of FIG. 5 and executes a return instruction, transitions to the user mode and executes the user program. In this state, if reset is requested from the user system, reset processing of the user program is performed (steps S8 and S9). At this time, since the wait signal ASEWAIT is set to the high level, the emulation-dedicated register MCUCR is not reset but its contents are held. That is, no CPU is selected. When the user program to be executed is terminated or the condition set by the user is satisfied, the execution of the user program is interrupted (break) and the emulation program execution is started (step S10).
-S5).

The CPU selection can be changed only while the emulation program is being executed. However, as described above, the output of the CPU selection bit CPUS is configured to be given to each part of the microcomputer through the flip-flop FF2 (see FIG. 2), so that the next reset is performed even if the selection is changed. It is not effective until it is input. Since the CPU is always started from the reset state,
No special processing is required. Moreover, the target microcomputer is CPU1 or CPU2.
It does not make sense to change the CPU during operation because it emulates only one of the CPUs and emulates a microcomputer containing any of the CPUs. Even if the change is permitted, the usability of the user is not impaired.

Bus timing and CP are shown in FIGS.
An example of U status signal timing is shown. Of these, FIG. 6 shows the operation timing of the address bus and the data bus.
ASEφ is the operating clock inside the emulator, ASEA
23-0 represents a 24-bit address bus signal, and ASED15-0 represents a 16-bit data bus signal.

FIG. 7 shows the timing of the read operation.
ASERD # is a read signal as a bus status signal which is set to a low level when the CPU1, CPU2 or another bus master reads an internal module, and is output from the emulation processor 10 to the outside. When the refresh cycle and another bus cycle are executed in parallel, the ASERD # signal has the bus cycle priority. Therefore, the emulator side cannot know the execution of the refresh cycle.

FIG. 8 shows the timing of the write operation.
ASEWR # is a write signal as a bus status signal which is set to a low level when the CPU1, CPU2 or another bus master writes to an internal module, and ASEEXWR # is a write signal which is set to a low level when writing to an external space, It is output from the emulation processor 10. When executing a word-size write by dividing it into two byte-size writes,
The EWR # signal outputs a low level once for word size access.

FIG. 9 shows the operation timing at the time of fetching an instruction. ASELIR # is an opcode fetch signal, C
It is a CPU status signal that outputs a low level during a PU instruction fetch cycle. ASELID1 # is an operation code execution signal, which is a CPU status signal that is set to a low level when the CPU starts executing instructions.

FIG. 10 shows the operation timing when executing a branch instruction. ASEBCCB # is a branch condition not satisfied signal as a CPU status signal which is set to a low level when the branch condition is not satisfied. When the CPU executes a conditional branch instruction,
The instruction at the branch destination is always fetched, and as a result of the condition determination, if the branch condition is satisfied, ASEBCCB # remains high level, and the instruction at the branch destination is executed without executing the next prefetched instruction. On the other hand, as a result of the condition determination,
When the branch condition is not satisfied, the ASEBCCB # signal is set to the low level in the branch destination instruction fetch cycle, the branch destination instruction is only fetched and not executed, and the next prefetched next instruction is executed.

FIG. 11 shows the timing of the interrupt operation. As described above, ASELID1 # is an opcode execution signal that is set to a low level when the CPU starts executing an instruction, A
SEIACK # is an interrupt acknowledge signal as a response signal to the interrupt request. The ASEIACK # signal changes to the low level (valid) with a delay of half a clock from the ASELID # signal, and the instruction corresponding to the ASELID # signal when the ASEIACK # signal becomes the low level is not executed.

The bus timing and the CPU status signal as described above are executed by the CPU 1 and the CPU 2 at a common timing. That is, when the common instructions of the CPU 1 and the CPU 2 are executed, the above timings are the same. When the address space of the CPU2 is smaller than that of the CPU1, the emulator ignores the upper address when emulating the CPU2. If the CPU 2 executes an instruction that exists only in the CPU 1, the unexecuted instruction is displayed. At this time, the signal indicating which CPU is selected may be referred to.

FIG. 12 shows an example of the emulator trace and disassemble list. AB is an address bus and DB is a data bus. MA indicates a memory access target, and EXT is an external address. R / W indicates read / write, and R is a read cycle. ST indicates the status, and PRG is the program fetch. IRQ, NMI, and RES are states of interrupts or system control signals included in a user interface (not shown).

Address bus, data bus, and other contents are sequentially stored in the trace memory, which is instructed by the control processor 28 to the host computer 4.
It can be displayed in the form of a list as shown in FIG. 12 on the display screen of 0 or can be output from the attached printer.

In addition to the address bus and data bus, read signals, write signals and CPU status signals are also traced. In the list of FIG. 12, the contents of the address bus and the data bus are displayed as they are, and the read signal / write signal is displayed correspondingly to R or W.
The CPU status signal is not directly displayed or output, but is provided to the analysis of the control processor.
For example, the signal indicated by ASELIR is assumed to be the instruction code fetched by the CPU, and PRG is displayed. The signal indicated by ASELID indicates the instruction code executed by the CPU, which is displayed as an assembler source. For example, 7A07,00FF,
ASELIR is output to FF0E, and 7A07
Is output to ASELID. Analyze this,
MOV. It is displayed as L # 00FFFF0E, ER7.

When displaying or outputting the trace of the CPU 2,
Even if the emulation processor sign-extends the high-order bits of the address, it is difficult for the user to understand if they are used on the trace display. Therefore, do not display the high-order address. Alternatively, the upper bits may be displayed as 0.

FIG. 13 shows another configuration example of the CPU incorporated in the emulation processor.

CPU1 and CPU2 are physically different CPUs.
However, if the functions of CPU1 include the functions of CPU2, only CPU1 is built in, and
For functions used only by PU1, CPU is used as a prohibition signal.
The selection signal is given. That is, CPU
If 1 is selected, the operation of all the functions of the CPU is permitted, and if CPU 2 is selected, the functions that cannot be used by the CPU 2 are prohibited. For example,
When the CPU 2 is selected, the reading / writing of the portion corresponding to the higher order of the general-purpose register is prohibited.

In FIG. 13, IR is an instruction register that holds the read instruction, CONT is a control section that supplies a control signal corresponding to the read instruction to the execution section,
MAB is an address output register, VAG is a vector number input register that takes in the vector number supplied at interrupt, MCR is a mode control register, R0 to R7 are general-purpose registers, PC is a program counter, ALU is an arithmetic logic unit, and DBR is a data input. The register and DBW are data output registers. In FIG. 13, the shaded portion is the portion where the circuit operation is prohibited when the CPU 2 is selected, and the CPU selection signal is given as the prohibition signal. That is, when the CPU 1 is selected by setting the CPU selection signal to "0", the operation in the shaded area is permitted. When the CPU selection signal is set to "1" and the CPU 2 is selected, the operation in the shaded area is prohibited.

As an example, FIG. 14 shows a method of permitting / prohibiting one high-order bit (bits 16 to 31) of a general-purpose register. The upper bit of the general-purpose register is composed of a D-type flip-flop FF3 with a clear terminal.
The CPU selection signal is applied to the clear terminal C of the flip-flop FF3. As a result, when the CPU 2 is selected, the output of the flip-flop FF3 is fixed to the low level by setting the CPU selection signal to "1". As a result, the high-order bit (bit 1
6 to 31) are fixed to "0".

Even when one of the two built-in CPUs does not necessarily include the other, a CPU including both functions is configured, and when one of the CPUs is selected, the function not used by the CPU is prohibited. It may be configured to do so. If an emulation processor incorporating such a CPU is developed, unnecessary CPU logic circuits can be deleted by so-called logic synthesis to obtain an optimized CPU logic circuit.

On the other hand, the prohibition function may not be provided. However, for example, when the function existing only in the CPU 1 is used when emulating the CPU 2, it is necessary to make the actual microcomputer correspond to the operation of the emulation processor so that they do not conflict with each other. For example, when the address 24-bit addressing mode that exists only in the CPU 1 is used, it can be executed in the CPU 2, and if the execution result indicates that the upper address is ignored, there is no problem. However, the emulation processor works, but in an actual microcomputer, if it runs out as an undefined instruction, the emulator's original function of debugging the program cannot be realized. Is. At least it should be displayed as an undefined instruction. For example, 7A0 in FIG.
CPU2 is selected for 7,000 FF and FF0E. L # 00FFFF0
If E and ER7 are undefined instructions, MOV. L # 00
Instead of displaying FFFF0E and ER7, they are displayed as undefined instructions.

If the above embodiment is applied to an emulator such as a cell-based IC having a built-in CPU, the optimum CPU can be selected at any time, and the user can design a cell-based IC using the optimum CPU. To be able to
It is suitable. As a result, it becomes possible to improve the development efficiency and reduce the physical scale of the designed cell-based IC, and hence the manufacturing cost.

According to the above embodiment, the following operational effects can be obtained.

(1) The user can use one emulator
Multiple CPUs can be selectively emulated.

(2) A plurality of microcomputers can be emulated by one emulator, development devices for the second and subsequent microcomputers can be provided promptly, and development efficiency can be improved.

(3) Since two CPUs having different address spaces can be emulated by one emulation processor, the program size may increase or decrease according to the user's program development. Also, the CPU can be immediately changed to perform emulation, and the CPU can be easily switched to the optimum CPU. As a result, development efficiency can be improved.

(4) Bus timing of a plurality of CPUs,
Emulator development can be facilitated by sharing the type and timing of the emulation CPU status signal and the like, and by sharing the object code of a plurality of CPUs.

(5) By providing a common bus controller or interrupt controller for a plurality of CPUs, the development efficiency of the emulation processor can be improved.

(6) By making it possible to change the CPU selection only at the time of reset, the CPU selection control can be facilitated and the development efficiency of the emulation processor can be improved.

The invention made by the inventors of the present invention is not limited to the embodiments, and various modifications can be made without departing from the scope of the invention. For example, the number of CPUs is not limited to two. In addition to the difference in address space, it may be possible to select enable / disable of a hardware accelerator (multiplier, divider, etc.). The size of the address space, the instruction set, the type of the CPU status signal and the bus timing, or the number and type of built-in functional blocks or modules, the number of pins, etc. are not particularly limited. Further, the specific configuration of the control register and the block dedicated to the emulation processor, the specific configuration of the emulator, etc. are not limited to the above embodiments, and
Various changes are possible.

In the above description, the case where the invention made by the present inventor is mainly applied to the emulation processor and the emulator, which are the fields of application which are the background of the invention, is not limited to the emulation processor and the emulator. It can be used for microcomputers and the like, which are mainly used for development and whose development period and the like are more important than manufacturing costs. Further, the present invention can be applied to other semiconductor integrated circuit devices, and at least the present invention can be applied to a semiconductor integrated circuit device having a plurality of CPUs or operating exclusively.

[0090]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, in one emulator,
Emulation of multiple CPUs is possible based on the user's selection, the microcomputer application system development device can be provided quickly, the application system development efficiency is improved, and the user can freely select the CPU, which is convenient for use. Is improved.

Further, by making the bus control, interrupt control and emulation interface signal of the CPU common, the development efficiency of the emulation processor and emulator is improved.

[Brief description of drawings]

FIG. 1 is a block diagram of an emulation processor showing an embodiment of the present invention.

FIG. 2 is a schematic block diagram showing an example of a CPU selection signal generation circuit.

FIG. 3 is a schematic block diagram showing another example of a CPU selection signal generation circuit.

FIG. 4 is a block diagram showing a schematic configuration of an emulator and an entire system development apparatus using the emulator.

FIG. 5 is a flowchart showing an outline of an operation procedure of the emulator.

FIG. 6 is a time chart showing an example of bus timing and timing of a CPU status signal.

FIG. 7 is a time chart showing an example of bus timing and timing of a CPU status signal.

FIG. 8 is a time chart showing an example of bus timing and timing of a CPU status signal.

FIG. 9 is a time chart showing an example of bus timing and timing of a CPU status signal.

FIG. 10 is a time chart showing an example of bus timing and timing of a CPU status signal.

FIG. 11 is a time chart showing an example of bus timing and timing of a CPU status signal.

FIG. 12 is an example of a trace and disassemble list of an emulator.

FIG. 13 is a block diagram showing another configuration example of a CPU incorporated in the emulation processor.

FIG. 14 is a circuit diagram showing a configuration example of bits that can be enabled / disabled in a general-purpose register.

[Explanation of symbols]

11 data transfer controller 12 read only memory 13 random access memory 14 bus controller 19 emulation control circuit 22 connector 30 user system (microcomputer application system) 31 single-chip microcomputer mounting area SEL1 to SEL3 selection circuit MCUCR control register MP monitor external Terminals FF1 to FF3 Flip-flop (latch circuit)

Claims (9)

[Claims] 1. A plurality of different CPUs having at least a part of an object code set, an internal status signal, an interface in common and the same operation timing, and a selection for selectively operating these CPUs. An emulation processor comprising a circuit and capable of executing emulation of a plurality of CPUs. 2. The emulation processor according to claim 1, further comprising a common interrupt control circuit that selectively controls interrupts to the plurality of CPUs. 3. A peripheral module which is a bus master is built-in, and a common bus control circuit for controlling the bus usage right between these peripheral modules and the plurality of CPUs is provided. An emulation processor described in. 4. A control flag or control register for selectively designating one of the plurality of CPUs is provided, and a predetermined control bit of the control flag or control register is provided with information of the control bit by a reset signal. The emulation processor according to claim 1, 2 or 3, wherein a reflected latch circuit is provided. 5. The emulation processor according to claim 1, further comprising an external terminal for outputting to the outside which one of the plurality of CPUs is selected. 6. The emulation processor according to claim 1, further comprising an external terminal for externally selecting and designating one of the plurality of CPUs. 7. The CPU having a small address space when the plurality of CPUs have different address spaces
The emulation processor according to claim 3, 4, 5 or 6, wherein the upper bit of an address not output by is configured to be 0 or sign-extended by the bus control circuit. 8. A CPU having a part of functions prohibited by a selection signal, wherein emulation of a plurality of CPUs can be substantially executed by prohibiting or allowing the parts of functions. Characteristic emulation processor. 9. The emulation processor according to any one of claims 1 to 8, a trace circuit for sequentially accumulating signals on a bus in which one of the CPUs in the processor is operating, and the CPU for detecting a predetermined state. And a break control circuit for stopping the execution of the program by the emulator.