JPH08255096A - Microprocessor and debugging system - Google Patents

Abstract

PURPOSE: To facilitate the connection between a user target system and a debugger and also facilitate the access to a peripheral device on the user target system. CONSTITUTION: This system consists of a processor core 20 which executes a monitor program debugging a user program and the user target system 70 and a debugging module 30 equipped with an interface function for a debugging tool enabling the processor core 20 to execute the monitor program and an execution control function which requests an interruption or exception for making the processor core 20 move from the user program to the monitor program during the execution of the user program from the processor core 20.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention has a function (PC trace function) of tracing a program counter, which is one of the debug functions, and also has an external function when a preset address or data of the debug function is accessed. The present invention relates to a microprocessor and a debug system having a function (trigger function) of notifying it to a user.

[0002]

2. Description of the Related Art FIG. 42 shows a conventional debug system. This conventional example is a debug system generally called an in-circuit emulator.

Referring to FIG. 42, a conventional debug system includes a user target system 500 and a debugger 5 for debugging the user target system 500.
It consists of 05. User target system 50
0 further indicates a microprocessor 501 and a memory 50.
3, I / O 502. The debugger 505 comprises a debugging microprocessor 506 and a monitor program memory 507.

In the conventional debug system, the microprocessor 501 on the target board is used for debugging.
Remove or disable the debugger 50
5 probe is connected to operate the debugging microprocessor 506 on the debugger 505 instead. The debugging microprocessor 506 controls the execution of the user program by executing the monitor program stored in the monitor program memory 507 on the debugger 505.

The debugging microprocessor 506 is
A program stored in the memory 503 on the user target system 500 is executed to access the data on the memory 503 and the I / O 502. Further, the debugger 505 has a trace memory 508, and the debug microprocessor 506 outputs trace information that cannot be obtained from the microprocessor 501. This makes it possible to trace a part of the internal state of the processor that cannot be traced only from the processor bus, for example, the value of the program counter (PC).

In this conventional example, the debugger 505 must be connected to all pins of the microprocessor on the user target system 500. The pins of the processor have, for example, 30 address signals, 4 byte enable signals, read signals, write signals, read response signals, write response signals, 32 data signals, for a total of 70 signals. Since the number of pins to be connected is large, the probe is expensive and the probing is often unstable. In addition, the memory 5 on the target system 500
03 and the monitor program memory 507 of the debugger 505, the bus must be switched, which is difficult to achieve with a processor having a high operating frequency.

Further, in the case where the derivative is a microprocessor to which the derivative is connected, the probe can be used for each derivative even though the same debugger can be used essentially because the package and the number of pins and the positions are different. Had to prepare for. In addition, the connection of the probe may affect the signal used in the user target system 500 to make the operation itself of the user target system 500 unstable.

FIG. 43 shows another conventional example of a debug system. This conventional example is a debug system generally called a ROM monitor.

In this conventional example, a serial interface 512 for connecting to a host computer 517 is prepared on a user target system 510, and a monitor program 514 is stored in a memory 513. The microprocessor 511 uses the monitor program 51
4 by executing the I / O 515, the memory 51
3. Access the register 516. Further, the software break instruction is used to control the execution of the user program.

In this conventional example, the monitor program 514
To execute in the memory 513 used by the user,
When the operation of the memory system of the user target system 510 is not complete, the monitor program itself may not operate stably. If the user's memory capacity is insufficient, the address space occupied by the monitor program may not be secured. In addition, some of the user's interrupts must be used to enter monitor mode, which can make debugging impossible for some programs. In addition, it is necessary to mount a circuit of the serial interface on the user target system 510 in advance, and it is necessary to provide the target system with a circuit that may not be used after debugging. Furthermore, because it does not have resources such as hardware breakpoints for debugging,
The debugging function was poor and I couldn't get a trace.

FIG. 44 shows another conventional example of the debug system.

In this conventional example, a serial interface 526 required for communication with a debug tool 529 in a microprocessor 521 on a user target system 520 and a sequencer 525 for interpreting and executing an electric signal sent from the debug tool 529. Built in. The sequencer 525 suspends the execution of the user program in accordance with the transmitted signal,
To access the memory 524 and the I / O 523 using the bus controller 527 to control the execution of the user program. The signal from the serial interface 526 is directly sent to the host computer 53.
Since it is often impossible to connect to 0, debug tool 52
9 converts commands from the host computer into electric signals that the microprocessor 521 can understand, and converts signals from the microprocessor 521 into a data format that the host computer 530 can understand.

In this conventional example, since the sequencer 525 is built in the microprocessor 521 and the sequencer 525 accesses the processor 521, the logic circuit for connection with the debug tool 529 becomes complicated, and the on-chip chip becomes complicated. The area has also grown. Further, since the sequencer 525 has to be changed when a register is added, it takes a lot of work to change the sequencer. Moreover, the trace could not be obtained even in this conventional example.

[0014]

As described above, the conventional debug system has a drawback in that the number of signals required for connection increases because the user target system and the debug processor are connected by the processor bus. Further, in the conventional debug system shown in FIG. 42,
The microprocessor on the debugger had to access the memory and I / O of the user target system, and the access timing was difficult.

Further, in the conventional debug system in which the monitor program is stored in the user's memory, the memory space used by the user is reduced. Furthermore, it has been difficult to perform debugging reliably and sufficiently.

On the other hand, in the conventional example in which a microprocessor has a built-in sequencer for interpreting and executing a signal given from the debug tool for debugging, the configuration for connection with the debug tool is complicated and large. Also,
When the addition of the configuration of the microprocessor or the like occurs, the sequencer must be changed, which requires a great deal of labor.

Further, as described above, in the conventional debug system, the signal required for the connection is required to connect the user target system and the processor for debugging with the processor bus even if the PC trace cannot be performed or the PC trace is possible. There was a drawback that it increased.
Further, in the conventional debug system shown in FIG. 42, the microprocessor on the debugger must access the memory and I / O of the user target system, which makes access timing difficult.

Further, as described above, the conventional debug system shown in FIGS. 43 and 44 does not have the trigger function.
Further, in the conventional example shown in FIG. 42, a trigger function can be provided in a microprocessor dedicated to debugging,
There was a problem that the number of signals that output trigger information increased. In addition, the method of FIG. 41 has a drawback in that the number of signals required for connection increases because the debug processor is connected to the processor bus, and the microprocessor for debugging uses the memory and I / I of the user target system. O had to be accessed, and the timing of access was difficult.

Therefore, the present invention has been made in view of the above, and it is possible to reduce the signals required for connecting the user target system and the debugger by providing the microprocessor on the user target system with a debug function. To aim.

The present invention also provides a microprocessor on the user target system with a debug function,
Another object is to facilitate the access to the memory and I / O on the user target system by operating the microprocessor on the user target system even during debugging.

Another object of the present invention is to realize a PC trace function with a small number of signals by providing a microprocessor on the user target system with a debug function.

The present invention also provides a microprocessor on the user target system with a debug function,
Another object is to facilitate the access to the memory and I / O on the user target system by operating the microprocessor on the user target system even during debugging.

The present invention further includes a debugging function in the microprocessor on the user target system,
By sharing the address and data comparison circuits of the hardware break function and the trigger function, and outputting the trigger information to the outside using the information output signal of the PC trace, it is possible to realize the trigger function with the minimum hardware. Has other purposes.

[0024]

In order to achieve the above object, a first feature of the present invention is to provide a processor core for executing a monitor program for debugging a user program and a user target system, the processor core and internal debug. An interface means connected to a debug tool for enabling the processor core to execute a monitor program, which is connected through an interface or a processor bus, and for shifting from the user program to the monitor program while the processor core is executing the user program. And a debug module having an execution control means for requesting the interrupt or exception of the processor core to the processor core.

A second feature of the present invention is to provide a debug tool including a monitor program for debugging a user target system, a processor core for executing a user-program or a monitor program, the processor core and an internal debug interface or a processor bus. Connected via the debug tool and an external debug interface, interface means with the debug tool for enabling the processor core to execute a monitor program, and the processor core during execution of the user program. A microprocessor comprising a debug module having an execution control means for requesting an interrupt or an exception for shifting from a user program to a monitor program to the processor core; A memory that is connected to a processor and a processor bus to configure a user-target system to be debugged and that stores information necessary for the microprocessor to execute a user program, and is connected to the microprocessor and the processor bus. And an I / O device that constitutes a user target system to be debugged.

According to the first and second features, the microprocessor on the user target system is provided with the debug function, and the signals required for connecting the user target system and the debugger can be reduced. Also,
By operating the microprocessor on the user target system even during debugging, it is possible to easily access the memory and I / O on the user target system.

A third feature of the present invention is that a microprocessor is connected to a processor core that executes a program, the processor core via an internal debug interface, and the instruction being executed is output from the processor core. And a PC trace circuit for outputting the value of the address to the number of PC output signals smaller than the bit width of the address of the instruction.

According to the third feature, the present invention can reduce the interface signals required for PC trace output by providing the microprocessor on the user target with the debug function.

A fourth feature of the present invention is that when the microprocessor matches the processor core executing the program with the set address and the accessed address,
Alternatively, when the set address and data match the accessed address and data, a break circuit requesting a break to the processor core or enabling a trigger output request signal, and a trigger output request signal from the break circuit When it becomes valid, it is composed of a PC trace circuit which outputs the information to an external status signal.

According to the fourth feature, by providing the microprocessor on the user target with the debug function, the address comparison circuit of the hardware break function and the trigger function is shared, and the information output signal of the PC trace is used. Then, by outputting the trigger information to the outside, the trigger function can be realized with the minimum hardware.

[0031]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a block diagram of a microprocessor and a debug system of the invention according to claim 1 or 2.

In FIG. 1, the debug system comprises a user target system 70 and a debugger 60.

The user target system 70 comprises a microprocessor 10 having a built-in debug function, a memory 40, and an I / O 50.

The microprocessor 10 comprises a processor core 20 and a debug module 30. The processor core 20 accesses the memory 40 and the I / O 50 via the processor bus 80 and executes the program. Further, the processor core 20 is connected to the debug module 30 by an internal debug interface and the processor bus 80. Debug module 30
Is a debugger 60 through an external debug interface
Connected with.

The debug system has two execution modes: a debug mode in which a monitor program is executed and a normal mode in which a user program is executed.

<Operation in Debug Mode> When the processor core 20 generates a debug exception or a debug reset, the debug mode is entered. The processor core 20 is
Vector address of debug exception (FF20_0200)
Alternatively, the debug reset vector address (FF20
_0000) and assert the debug mode signal DM. The memory corresponding to these vector addresses is placed on the debugger 60. The processor core 20 receives the debugger 60 via the debug module 30.
Run the above monitor program. The monitor program implements execution control functions such as reading and writing of memory and registers, designating the end address of the user program, and designating the execution start address of the user program.
The processor core 20 returns to the normal mode by executing the return instruction to the normal mode, and starts executing the user program. Processor core 20
Jumps to the address specified by the return instruction to the normal mode and negates the debug mode signal DM.

<Operation in Normal Mode> In the normal mode, the debug system executes the user program. At the same time, PC (program counter) information is traced (PC trace function). The debug system can request a debug exception / debug reset to the processor core 20 by a hardware break, a software break, a debug interrupt, a debug reset, etc., and can transfer control to the debug mode.

The PC trace function, hardware break function, software break function, debug interrupt function, debug reset function and trace trigger function that are effective in the normal mode will be described below.

The PC trace function is provided by the processor core 20.
Is a function for tracing the value of the PC when executing the user program. When the processor core 20 is executing the user program on the memory 40,
This is realized by outputting the PC trace information to the internal debug interface, inputting the information by the debug module, processing the information, and then outputting it to the debugger 60 via the external debug interface.

The hardware break function is a function of causing the processor core 20 to generate a debug exception and transferring control to the monitor program of the debugger 60 when an instruction at a predetermined address is executed or data is accessed. In this function, the debug module 30 outputs the instruction execution address, the data access address and the value of the data output from the processor core 20 to the internal debug interface and the processor bus 80.
This is realized by comparing with the value of the address or data set in the register in the inside and requesting a debug exception or a debug interrupt to the processor core 20 when they match.

The software break function causes the processor core 20 to execute a software break instruction to generate a debug exception. This allows control to be transferred to the monitor program.

The debug interrupt function is a function in which the processor core 20 generates a debug exception by asserting the debug interrupt signal of the processor core 20. This allows control to be transferred to the monitor program.

The debug reset function is a function in which the processor core 20 generates a debug reset by asserting the debug reset signal of the processor core 20. As a result, the internal states of the processor core 20 and the debug module 30 are initialized, the processor core 20 enters the debug mode, and the program execution starts from the debug reset vector address (FF20_0000).

The trace trigger function is used when an instruction at a predetermined address is executed or data is accessed.
The microprocessor 10 has a function of outputting the state to an external signal. The debugger 60 inputs this signal and the PC
Controls ON / OFF of trace. This function is to execute the instruction execution address, the data access address, and the value of the data output by the processor core 20 to the internal debug interface and the processor bus 80, to the address set in the register in the debug module 30, Compare with the value of the data,
It is realized by outputting the trigger information to the debugger 60 when they match.

Next, the debug module 30 will be described in more detail.

FIG. 2 shows an internal block of the debug module 30. In FIG. 2, the debug module 30
Is composed of an instruction / data address break circuit 31, a PC trace circuit 32, a processor bus break circuit 33, a serial monitor bus circuit 34, a register circuit 35, an external interface circuit 36, and a clock supply circuit 37.

Instruction / data address break circuit 31
Are connected to the processor core 20 via an internal debug interface. The instruction address output from the processor core 20 is input, and when the value matches the instruction address set in the register circuit 35, an instruction address break exception is requested to the processor core 20. Further, the data address output from the processor core 20 is input, and when the value matches the data address set in the register circuit 35, a data address break exception is requested to the processor core 20.

The PC trace circuit 32 is connected to the processor core 20 via an internal debug interface. The PC trace information output from the processor core 20 is input, the information is processed and output to the external interface circuit 36.

The processor bus break circuit 33 is connected to the processor core 20 by the processor bus 80. Monitor the bus cycles on the processor bus 80,
When the address and data bus cycles set in the register circuit 35 are executed, an exception is requested to the processor core 20.

The serial monitor bus circuit 34 is connected to the processor core 20 by the processor bus 80, and interfaces with the processor core 20 when executing the monitor program on the debugger 60.

The register circuit 35 includes a control register built in the debug module 30 and controls the function of the debug module. Processor core 20 by processor bus 80 and internal debug interface
And the processor core 20 can read / write the contents of the control register. Further, the content of the control register is output to each circuit of the debug module and the processor core 20 to control the debug function.

The external interface circuit 36 is the PC trace circuit 32 in the debug module 30, the serial monitor bus circuit 34, the processor core 20 and the debugger 6.
It is a circuit that controls the interface with 0.

The clock supply circuit 37 has a clock signal C.
This is a circuit for dividing LK. The serial monitor bus circuit operates with the divided clock CLK2.

<Description of External Signal> Debug Module 3
0 and the following eight dedicated interface signals between the external debugger 60. 1. SDAO / TPC: Output 2. SDI / DINT *: Input 3. DCLK: Output 4. DRESET *: Input 5-7. PCST [2: 0]: Output 8. DBGE *: Input

(1) DCLD (Debug Cloc
k): Output This signal is a clock output to the debugger 60. The timing of the signals of the serial monitor bus and PC trace interface are all based on this debug clock DCLK.
Stipulated in. In the serial monitor bus operation, the operation clock of the processor core 20 is divided by two.

(2) DRESET * (Debug Re
set): Input (terminal with pull-up) This signal is a debug reset input, and Low Acti
ve. When DRESET * is asserted, the debug module is initialized (regardless of DBGE *). When not using the debug 60, leave this terminal unconnected.

(3) PCST [2: 0] (PC Tra
ce Status): Output This signal outputs the following PC trace status information and the mode of the serial monitor bus.

111 (STL): Pipeline installation 110 (JMP): Branch / jump taken (with PC output) 101 (BRT): Branch / jump taken (without PC output) 100 (EXP): Exception occurred (exception vector code) 011 (SEQ): Sequential execution (indicates that one instruction has been executed) 010 (TST): Trace trigger output during pipeline installation 001 (TSQ): Trace trigger output during execution 000 (DBM): Debug mode ( 0: Low,
1: High level (4) DBGE * (Debugger Enable)
e): Input (terminal with pull-up)

This signal indicates whether or not the debugger 60 is connected. When the debugger 60 is not connected to the outside, H
When the debugger 60 is connected to Low (NC not connected), Low is input.

The debugger 60 is not connected (DBG
When the E * signal is High), the DEV signal of the processor core 20 becomes Low, and the debug exception vector address becomes FF20_0200. The debug module function is initialized by user reset (RESET *), and all the debugger functions are disabled. Output signal (SDA0 / TPC, DCLK, PCST
[2: 0]) are all Hi-z.

A debugger 60 is connected (DBGE
* When the signal is Low), the DE of the processor core 20
The V signal becomes High, and the debug exception vector address becomes FF20_0200 (in the monitor area). The user reset (RESET *) does not initialize the debug module.

(5) SDAO / TPC (Serial
Data and Address Output / Ta
rget PC): In the output debug mode (PCST = DBM), the serial monitor bus interface SDAO (Series)
al Data and Address Outpu
t), in the normal mode (PCST ≠ DBM), TPC (Tar of the PC trace interface)
as a get PC).

SDAO (Serial Data an
d Address Output) (debug mode, when PCST = DBM), data, address,
It is a signal that serially outputs the read, write, and byte enable signals bit by bit. The start bit is output before the bus cycle starts. (Low is output for one clock.) The order of output is the start bit (Low) when reading,
A [2] -A [19], R / W * BE [0] *-BE
[3] *. When writing, start bit (Lo
w), A [2] -A [19], R / W *, BE [0] *
-BE [3] *, D [0] -D [31].

TPC (Target PC) (normal mode, when PCST ≠ DBM) is a signal for outputting a target address of a branch / jump instruction and an exception / interruption vector number. The target address is sequentially output from the lower address A [2] to A [31].

(6) SDI / DINT * (Serial
Data Input / Debug Interru
pt): Input (terminal with pull-up) In the debug mode (PCST = DBM), SDI (Serial of serial monitor bus interface)
Normal mode (P
When CST ≠ DBM), PC trace interface DINT * (Debug Interrupt)
Acts as.

SDI (Serial Data Inp)
ut) (debug mode, when PCST = DBM) is a data input signal. At the time of reading, when a start bit (Low for one clock) is input from the outside, data input is started from the next clock. When Low is input during writing, the bus cycle ends.

The order of input is the start bit (Low) and D [0] -D [31] at the time of reading. At the time of writing, only the end bit (Low) is input.

DINT * (Debug Interru
put) (normal mode, when PCST ≠ DBM)
Is a debug interrupt input from the debugger 60.
When not using the debug 60, leave this terminal unconnected.

FIG. 3 shows the configuration of the register circuit 35. In FIG. 3, the register circuit 35 is the address decoder 3
51 and a register unit 352.

The address decoder 351 receives the address input A [3 from the processor bus 80 of the processor core 20.
1: 0], read signal RD *, write signal WR *, debug mode signal DM, and core clock CLK.
The address decoder 351 decodes the address in the bus cycle of the processor core 20, and the register unit 352.
At the time of reading to the address of the register in the register core 352, the register read signal for reading the corresponding register in the register unit 352 is asserted,
Asserts the read response signal RDACK *.

Further, at the time of writing to the address of the register of the register unit 352, a register write signal for writing to the corresponding register in the register unit 352 is asserted, and the read response signal R of the processor core 20.
Assert DACK * and write response signal WRACK *
Assert.

However, in the normal mode, the register unit 3
52 is inaccessible. At this time, the address decoder 351 only asserts the read response signal RDACK * to the processor core 20 during the read bus cycle and the write response signal WRACK * during the write bus cycle. Therefore, the value read by reading becomes indefinite, and the write data is ignored.

Even in the debug mode, if the memory protection bit MP of the DCR register is set, access to the registers of the register unit 352 other than the DCR register is prohibited. Address decoder 35
1 is a read response signal RD in the read bus cycle
In the case of ACK *, write bus cycle, the write response signal WRACK * is only asserted to the processor core 20. Therefore, the value read by reading becomes indefinite, and the write data is ignored.

The address decoder 351 operates as shown in Table 1.

[0076]

[Table 1] The register unit 352 has a DCR (Debug Control) function.
ol Register) register, IBS (Inst
reduction break status (DBR) register, DBS (Data Break Status) register, PBS (Processor Bus Breth)
ak Status register, IBA0 (Instr
Function Break Address 0) register, IBC0 (Instruction Break)
Control 0) register, DBA0 (Data)
Break Address 0) register, DBC
0 (Data Break Control 0) register, PBA0 (Processor Bus Br)
eak Address 0) register, PBD0 (P
processor Bus Break Data
0) register, PBM0 (Processor Bus)
Break Data Mask 0) register, P
BC0 (Processor Bus Break C)
control 0) is included.

The register reset condition is user reset (RESET * active and DBGE * = High) when the debug reset DRESET * of the microprocessor 10 is asserted or when the debugger 60 is not connected.

The function of each register will be described below.

FIG. 4 shows the DCR (Debug Control)
l Register).

TM: (Trace Mode) (at reset: 0) This is a bit for designating the operation mode of PC trace. 0: It becomes the mode which outputs PC trace information in real time. 1: The mode is in which the PC trace information is completely output.
(Real-time property is not guaranteed.) The TM bit is output to the PC trace circuit 32. MRst: (Mask User Reset) (at reset: 0) This bit is used to specify a mask for user reset. 0: Mask user reset during debug exception. 1: User reset is allowed during debug exception.

The MRst bit is output to the external interface circuit 36. MP: (Memory Protection) (at reset: 1) 0: In the debug mode, writing to the monitor area is possible. 1: In the debug mode, write protection to the monitor area (FF20_0000 to FF3F_FFFF) excluding the DCR register is protected.

The MP bit is output to the address decoder 351 and the serial monitor bus circuit 34.

MNmI: (Mask Non-mask
Interrupt) (at reset: 1) 0: Mask NmI generation of the processor core 20. The NmiMask signal of the processor core 20 is set to Low. 1: Permit NmI generation of the processor core 20. The MNmI bit is output to the processor core 20. MInt: (Mask Interrupt) (at reset: 1) 0: Mask generation of external interrupt (Int [5: 0] *) of the core. 1: Permits generation of core external interrupt (Int [5: 0] *). The MInt bit is output to the external interface circuit 36. ENM: (Endian Memory) (User) Indicates the value of the Endian signal at reset. This bit can only be read, writes are ignored.

0: Little endian 1: Big endian The ENM bit is obtained by latching the ENDIAN signal at the rising edge of the core clock when the user reset is Low. HIS: (Halt Status) Indicates the value of the Halt signal when DINT * of the processor core 20 becomes active. This bit can only be read, writes are ignored.

0: Not in Halt state. 1: Halt state.

At the falling edge of the debug interrupt signal DINT *, the one obtained by latching the HALT signal is
Bit. DzS: (Dose Status) Indicates the value of the Dose signal when DInt * of the processor core 20 becomes active. This bit can only be read, writes are ignored. 0: Not in the Doze state. 1: Doze state. The DzS bit is obtained by latching the DOZE signal at the falling edge of the debug interrupt signal DINT *.

FIG. 5 shows IBA0 (Instruction).
The Break Address 0) register is shown.

IBA: (Instruction Br
eak Address) Stores the instruction break address. This address is a virtual address. The IBA field is output to the instruction / data address break circuit 31.

FIG. 6 shows IBC0 (Instruction).
The Break Control 0) register is shown.

BE: (Break Enable) (at reset: 0) This bit specifies whether the instruction address break function is valid or invalid. 0: The instruction address break function is disabled. 1: Instruction address break function is enabled. BE = 1
At this time, if the virtual address of the instruction immediately before execution matches the address set in the IBA0 register, an instruction break request is issued to the processor core 20, and the BBS of the IBS register is issued.
Set the S0 bit. (The processor core 20 generates an instruction address break exception immediately before the execution of the instruction having the matched address.) The BE bit is the instruction / data address break circuit 31.
Output to

TE: (Trace Trigger E
(reset: 0) This bit specifies whether the instruction address trace trigger function is valid or invalid. 0: The instruction address trace trigger function is disabled. 1: The instruction address trace trigger function is valid. T
When E = 1 and the trace trigger is valid, when the virtual address of the executed instruction matches the address set in the IBA0 register, the trace trigger information (TST (010) or TSQ (001)) is displayed in PCST [2: 0]. ) Is output and the BS0 bit of the IBS register is set. The TE bit is used for the instruction / data address break circuit 31.
Output to

FIG. 7 shows an IBS (Instruction)
Break Status) register.

BCN: (Break Channel
Number) Indicates the number of channels for instruction break. This field can only be read. Lights are ignored. 0000: None (reserved) 0001: 1 channel ... 1111: 15 channel (reserved) BS0: (Break Status 0)

A status bit indicating that an instruction address break or an instruction address trace trigger has occurred. 0: Indicates that a channel 0 instruction address break or instruction address trace trigger has not occurred. 1: Indicates that when the IBC0 register is BE = 1 or TE = 1, the virtual address of the instruction matches the set address and an instruction address break exception or an instruction address trace trigger occurs. This bit is
Cleared by writing 0. The BS0 bit is set when the BS0 set signal of the IBS register from the instruction / data address break circuit is asserted.

FIG. 8 shows DBA0 (Data Break).
Address 0) register.

DBA: (Data break address) Stores a data break address. This address is a virtual address. The DBA field is output to the instruction / data address break circuit 31.

FIG. 9 shows DBC0 (Data Break).
Control 0) register. BE: (Break Enable) (At reset:
0) This bit specifies whether the data address break function is valid or invalid. 0: The data address break function is disabled. 1: The data address break function is valid. BE =
When 1, the virtual address of the data immediately before execution and the DB
When the addresses set in the A0 register match, a data break request is issued to the processor core 20 and the BS0 bit of the DBS register is set.

The BE bit is output to the instruction / data address break circuit 31. TE: (Trace Trigger Enable)
(At reset: 0) This bit specifies whether the data address trace trigger function is valid or invalid. 0: The data address trace trigger function is disabled. 1: The data address trace trigger function is valid.
When the trace trigger is valid with TE = 1 and the virtual address of the executed data matches the address set in the DBA0 register, trace trigger information (TST (010) or TSQ (001)) is displayed in PCST [2: 0]. Is output and the BS0 bit of the DBS register is set. The TE bit is used for the instruction / data address break circuit 31.
Output to

FIG. 10 shows a DBS (Data Break).
Status) register.

BCN: Break Channel Number) Indicates the number of channels of data break. This field can only be read. Lights are ignored. 0000: None (reserved) 0001: 1 channel ... 1111: 15 channel (reserved) BS0: (Break Status 0)

A status bit indicating that a data address break or a data address trace trigger has occurred. 0: Indicates that no data address break or data address trace trigger of channel 0 has occurred.

1: Indicates that when BE = 1 or TE = 1 of the DBC0 register, the virtual address of the data matches the set address and a data address break exception or a data address trace trigger occurs.

This bit is cleared by writing a 0. The BS0 bit is set when the BS0 set signal of the DBS register from the instruction / data address break circuit 31 is asserted.

FIG. 11 shows PBA0 (Processor).
A Bus Break Address register is shown.

PBA: (Processor Bus
Break Address) Stores the break address of the processor bus break / trace trigger function. This address is a physical address. The PBA field is output to the processor bus break circuit 33.

FIG. 12 shows the PBD0 (Processor).
Bus Break Data 0) register.

PBD: (Processor Bus
Break Data) Stores break data of the processor bus break / trace trigger function. The PBD field is output to the processor bus break circuit 33.

FIG. 13 shows the PBM0 (Processor).
Bus Mask 0) register.

PBM: (Processor Bus
Break Data Mask) PBD of processor bus break / trace trigger function
When comparing with the data stored in the register, specify the bit that invalidates (masks) the comparison. 0: Compare corresponding bits of PBD register. 1: Do not compare corresponding bits of PBD register. The PBM field is output to the processor bus break circuit 33.

FIG. 14 shows the PBC0 (Processor).
Bus Control 0) register. BE: (Break Enable) (At reset:
0) Specify whether the processor bus break is valid or invalid. 0: Processor bus break is invalid. 1: The processor bus break is valid. When the comparison result of the address and the data matches the set value, a debug interrupt is requested to the processor core 20.

The BE bit is output to the processor bus break circuit 33. TE: (Trace Trigger Enable)
(At reset: 0) Specifies whether the processor bus trace trigger is valid or invalid. 0: The processor bus trace trigger is invalid. 1: The processor bus trace trigger is valid. If the comparison result of the address and data matches the set value, PCST
The trace trigger information (TST (010) or TSQ (001)) is output at [2: 0]. The TE bit is output to the processor bus break circuit 33.

IFUC: (Instruction F
etch from Uncache Area) Specifies whether to compare the address and data in the instruction fetch from the non-cache area.

0: No comparison between address and data is made by instruction fetch from the non-cache area.

1: The address and the data are compared by fetching the instruction from the non-cache area.

The IFUC bit is output to the processor bus break circuit 33.

DLUC: (Data Load pro
m Uncache Area) Specifies whether to compare address and data when loading data from the non-cache area.

0: No comparison between address and data is performed when data is loaded from the non-cache area.

1: Address and data are compared by loading data from the non-cache area.

The DLUC bit is output to the processor bus break circuit 33.

DSUC: (Data Store to
Uncache Area) Specifies whether to compare address and data in the data store to the non-cache area.

0: The address and data are not compared in the data store in the non-cache area.

1: The address and data are compared in the data store in the non-cache area. The DSUC bit is output to the processor bus break circuit 33.

DSCA: (Data Store to
Cache Area) Specify whether to compare address and data in the data store to the cache area.

0: The address and data are not compared in the data store in the cache area.

1: Address and data are compared in the data store in the cache area. The DSCA bit is output to the processor bus break circuit 33.

FIG. 15 shows a PBS (Processor B).
us Break Status register. BCN: (Break Channel Number
r) Indicates the number of channels of the processor bus break.

0000: 0 channel (reserved) 0001: 1 channel ... 1111: 15 channel (reserved) BS0: (Break status 0.) (at reset: 0) A processor bus break or a processor bus trace trigger is generated. This is the status bit to indicate.

0: Indicates that a processor bus break of channel 0 or a processor bus trace trigger has not occurred. 1: When BE = 1 or TE = 1 of the PBE0 register, the channel 0 processor bus break or
Indicates that a processor bus trace trigger has occurred.

This bit is cleared by writing 0, and when BE = 1, the debug interrupt requested to the processor core 20 is also cleared. The BS0 bit is set when the BS0 set signal in the PBS register from the processor bus break circuit is asserted.

FIG. 16 shows the instruction / data address break circuit 31. Instruction / data address break circuit 31
Is an instruction address comparator 311 and a data address comparator 3
12 and AND circuits 313, 314, 315, 316.

If the break enable BE bit or the trigger enable TE bit of the IBC0 register is set, the instruction address comparator 311 receives the instruction address valid signal from the processor core 20 and asserts the processor address. The instruction address input from is compared with the address stored in the IBA0 register. When these addresses match, a signal that sets the BS0 bit of the IBS register is output. At the same time when BE is set, the output of the AND circuit 313 is asserted, requesting an instruction address break to the processor core 20, and when TE is set,
The output of the AND circuit 314 is asserted, and the PC trace circuit 32 is requested to output the trace trigger.

The data address comparator 312 uses the DBC0
If the break enable BE bit or the trigger enable TE bit of the register is set, the data address input from the processor core 20 and the DBA0 register are stored when the data address valid signal from the processor core 20 is asserted. Compare addresses. When these addresses match, DB
A signal that sets the BS0 bit of the S register is output. At the same time, when BE is set, the output of the AND circuit 315 is asserted, a data address break is requested to the processor core 20, and when TE is set, the output of the AND circuit 316 is asserted and P
Request the trace trigger output to the C trace circuit 32.

FIG. 17 shows the processor bus break circuit 33.
Shows the configuration of.

The processor bus break 33 monitors the bus operation of the processor bus and requests a debug interrupt to the processor core 20 when the bus operation of the address and data set in the register occurs.

The processor bus break circuit 33 comprises a processor bus address comparator 331, a masked data comparator 332, and AND circuits 333, 334, 335.

The processor bus address comparator 331 is
When the break enable BE or the trigger enable TE of the PBC0 register is set, the address of the processor bus is compared with the address set in the PBA0 register. In addition, D of the PBC0 register
The SCA, DSUC, DLUC, and IFUC bits specify enable / disable of comparison for non-cache area / cache area, data store / data load / instruction fetch. The processor bus address comparator 331, the processor core 2 in the processor bus cycle.
ID signal output from 0 (indicating instruction fetch or data access), read RD * signal, write signal WR
The operation shown in Table 2 below is performed by * and CACHE *.

[0137]

[Table 2] In the read bus cycle (read signal RD * = Low), the masked data comparator 332 compares the data input DIN [31: 0] of the processor bus 80 with the value of the PBD0 register only for 0 bit of the PBM0 register. . Further, the masked data comparator 332 determines that the write bus cycle (write signal WR * = Low)
Only for the 0 bit of the PBM0 register, the data output DOUT [31: 0] of the processor bus 80 and the PBD
Compare the values in the 0 registers.

When the outputs of the processor bus address comparator 331 and the masked data comparator 332 are both H, that is, when the comparison of the address and the data coincides, AN
The output of the D circuit 333 is asserted, requesting the register circuit 35 to set the BS0 bit of the PBS register.
At this time, if BE of PBC0 is set, A
If the output of the ND circuit 334 is asserted, a debug interrupt is requested to the processor core 20, and the TE bit of PBC0 is set, the output of the AND circuit 335 is asserted and the PC trace circuit 32 is requested to output a trigger. .

FIG. 18 shows the serial monitor bus circuit 34. The serial monitor bus circuit 34 includes a serial monitor bus control circuit 341, a serial output circuit 342,
It comprises a serial input circuit 343.

Serial monitor bus control circuit 34
1 is a data output from the processor bus DOUT [31:
0], address A [31:20], read signal RD *,
Write signal WR *, coprocessor read signal CPRD
*, Coprocessor write signal CPWR *, debug mode signal DM, divided clock C from clock supply circuit 37
LK2, the MP bit of the DCR register from the register circuit 35, and SDI from the external interface circuit 36.

Further, the serial monitor bus control circuit 341 sends the read response signal RDAC to the processor bus.
K *, write response signal WRACK *, coprocessor read response signal CPRDACK *, coprocessor write response signal CPWRACK * to serial output circuit 342, serial monitor bus read / write signal, serial monitor bus byte enable signal, serial monitor bus data The signal, the data load signal and the output shift signal of the output shift register 344 in the serial output circuit 342, the input shift signal of the input shift register 345 and the output enable signal of the output buffer 346 are output to the serial input circuit 343. Serial monitor bus read / write signal is
It becomes High level during read bus operation and Low level during write bus operation.

The serial output circuit 342 comprises an output shift register 344. When the data load signal of the serial monitor bus control circuit 341 is asserted,
The start bit (fixed to Low), address signals A [2] to A [19], serial monitor bus read / write signal, serial monitor bus byte enable signal, and serial monitor bus data signal are loaded from the LSB to the output shift register 344. It When the output shift signal is asserted, the value in the output shift register 344 is shifted by 1 bit from MSB to LSB, and High is input to MSB. The LSB value of the output shift register 344 is SDAO.
Is output to

The serial input circuit 343 comprises an input shift register 345 and an output buffer 346. When the input shift signal of the serial monitor bus control circuit 341 is asserted, the value of the input shift register 345 is set to L.
Shift 1 bit from SB to MSB and change SDI value to LS
Input to B.

Next, the operation of the serial monitor bus circuit 34 shown in FIG. 18 will be described.

During the debug mode, the processor core 20
Address 0xFF20_0000 to 0xFF2F_F
The memory on the debugger 60 is accessed through the serial monitor bus circuit 34 when the area up to FFF is accessed and when the coprocessor bus operation is performed by executing the read / write (CTC0, CFC0) of the coprocessor. . In the write operation using the serial monitor bus, the serial monitor bus circuit 34
Outputs an address, a bus control signal, and data serially to the SDAO signal bit by bit. In the read operation, the address and bus control signals are output to the SDAO signal, and the data is serially input bit by bit from the SDI signal.

The serial monitor bus is the processor core 2
Clock CLK2 obtained by dividing the operating clock CLK of 0 by 2
Works with.

A) Access by read / write bus operation In the read bus operation, the processor core 20 outputs the address to be accessed to A [31: 0], and RD
* Assert the signal. When the read response signal RDACK * is asserted, the data bus input DIN [31: 0]
The data is read from and the bus operation ends.

In the write bus operation, the processor core 20 sets the address to be accessed to A [31: 0].
To the data bus output DOUT [31: 0] and assert the WR * signal. Write response signal WR
The bus operation ends when ACK * is asserted.

When the processor core 20 executes the bus operation for the following monitor area in the debug mode, the debugger 60 is executed via the serial monitor bus circuit 34.
Is accessed.

Addresses 0xFF20_0000 to 0xFF2F_FFFF 1M bytes (A [31:20]) = 1111_1111_0010 (0: Low, 1: High level) In the write bus operation, for example, a store instruction (SW instruction) for writing data to the memory is issued. To use. less than,
An example of a store instruction is shown.

Sw r8 0x0004 (r9) In this example, the value obtained by adding the 16-bit offset value 0x0004 and the general-purpose register r9 is the memory address. To access the monitor area of the serial monitor bus, set the value of the general-purpose register in advance to 0xFF20. 0000-0
xFF2F Must be set to 0000.

The serial monitor bus circuit 34 outputs a bus cycle signal to the SDAO signal of the serial monitor bus every clock. Processor bus address A [1
9: 2] is output from the lower order, and next, when reading, Hi is output.
It outputs gh level and Low level when writing.
Next, the byte enable BE [3: 0] * is output from the lower order. In the case of read, input 32-bit data from the SDI signal, and input data DIN signal of the processor bus
The value is output at [31: 0]. When writing, data output DOUT [31: 0] of the processor bus.
The value of is output to the SDAO signal.

The address output to the serial monitor bus is 1 of the address signal A [19: 2] of the processor core 20.
It has 8 bits and can access a 1 Mbyte memory space.

Since the byte enable signals BE [3: 0] of the processor core 20 are output to the serial monitor bus, it is possible to access bytes, halfwords and 3 bytes. However, in the serial bus, 32-bit data (D [31: 0]) is transferred even in the case of byte, halfword, and 3-byte access. When writing 1 byte, half word, and 3 bytes, the data output at the byte position where BE [3: 0] * is inactive is undefined,
When reading, the data at the inactive byte position is ignored by the processor core 20 and is not read.

Even in the debug mode, the protection of the monitor area is set (MPR of the DCR register is set).
= 1), writes to FF20_0000 to FF2F_FFFF are ignored. At this time, the serial monitor bus circuit 34 returns only WRACK * to the processor core 20 and ends the bus operation.

FF20_0000 in debug mode
When reading from FF2F_FFFF, correct data is read from the serial monitor bus regardless of the value of the MP bit.

In the normal mode, the monitor area FF20
Writes to _0000 to FF2F_FFFF are also ignored, and the result of reading is undefined. At this time, the serial monitor bus circuit 34 sends the WRAC to the processor core 20.
K * or RDACK * is returned and only bus operation is completed.

B) Access by coprocessor bus operation (CTC0 / CFC0) Processor core 20
Executes the read bus operation of the coprocessor when CFC0 is executed and the write bus operation of the coprocessor when the CTC0 instruction is executed. In the coprocessor bus operation, the following CFC0 and CTC0 instructions are output as they are to the address A [31: 0] of the processor bus.

A [31: 0] COP0 CT rt rd 0 A [31: 0] COP0 CF rt rd 0 CFC0 (0: Low, 1: High level) rt: General-purpose register rd: Coprocessor control register (serial monitor) It doesn't make sense on a bus.)

Further, the processor core 20 asserts the CPRD * signal in the coprocessor read operation, and when the coprocessor read response signal CPRDACK * is asserted, the data bus input DIN [31: 0].
The data is read from and the bus operation ends.

In the coprocessor write operation, the processor core 20 asserts the CPWR * signal and outputs the value of the general-purpose register of the processor core to the data bus output DOUT [31: 0]. When the coprocessor write response signal CPWRACK * is asserted, the bus operation ends.

The processor core 20 uses CTC0 and CFC0.
When you execute a coprocessor bus operation of instructions,
The debugger 60 is accessed via the serial monitor bus.

The serial monitor bus circuit 34 outputs a bus cycle signal to the SDAO signal of the serial monitor bus for each clock. The address signal A [19: 2] of the processor core 20 is output from the lower order, and High is output next for coprocessor read, and Low is output for coprocessor write. The byte enable signal of the serial monitor bus is BE [3: 0] * of the processor bus.
It outputs Low for 4 clocks regardless of. Therefore,
Coprocessor bus operations of CTC0 and CFC0 instructions are always transferred in 4-byte units.

In the case of the CFC0 instruction, 32 from the SDI signal
Bit data is input and the value is output to the data input signal DIN [31: 0] of the processor bus. Also, C
For TC0 instruction, data output DO of processor bus
The value of UT [31: 0] is output to the SDAO signal.

In the debug mode, the write bus operation of the serial monitor bus by CTC0 is executed regardless of the protection of the monitor area (the value of the MP bit of the DCR register). Further, the read operation of the serial monitor bus by CFC0 is also executed.

Writing by CTC0 in the normal mode is ignored, and the result of reading by CFC0 is undefined. The debug module sends CP to the processor core 20.
Only RDACK * and CPWRACK * are returned to the processor core 20, and the bus operation ends.

The following is a timing diagram for serial monitor bus operation. a) Read bus operation of serial monitor bus FIG. 19 shows a timing chart of read bus operation of the serial monitor bus.

(1) Processor core 20 has address 0x
FF20_0000 to 0xFF2F_FFFF (A [3
1:20] = 1111_1111_0010) The read bus operation for the area is started (cycle 1). The processor core 20 outputs the address for accessing A [31: 0] and asserts RD *. The byte enable signal BE [3: at the byte position to be read
0] is asserted.

(2) When the serial monitor bus circuit 34 recognizes the start of the read bus operation to the monitor area, the serial clock bus circuit 34 divides the core clock CLK into C by dividing the core clock CLK into the SDAO signal.
The LK2 signal outputs a low level for one clock (cycle 2).

(3) The serial monitor bus circuit 34 outputs the addresses A [2] to A [19], High (indicating read), BE [0] * to BE output by the read bus operation of the processor core 20. [3] * to SDAO
The signal is output every one clock of CLK2 (cycles 3 to 25).

(4) The debugger 60 outputs Low to the SDI signal for one clock before outputting data (cycle n). The serial monitor bus circuit 34 goes low on SDI.
When ow is detected, data D [0]
D [31] is read every clock (cycle n +
1-n + 32).

(5) The serial monitor bus circuit 34 uses the read bus response signal RDACK * of the processor core 20.
And outputs the read 32-bit data D [31: 0] to the data bus DIN [31: 0] (cycle n + 33).

(6) The processor core 20 reads the data on the data bus DIN [31: 0] and ends the read bus operation (cycle n + 33).

B) Write Bus Operation of Serial Monitor Bus FIG. 20 shows a timing diagram of write bus operation of the serial monitor bus.

(1) Processor core 20 has address 0x
FF20_0000 to 0xFF2F_FFFF (A [3
1:20] = 1111_1111_0010) The write bus operation for the area is started (cycle 1). The processor core 20 outputs the address for accessing A [31: 0] and asserts WR *. The byte enable signal BE [3: at the byte position to be written
0] is asserted.

(2) When the serial monitor bus circuit 34 recognizes the start of the write bus operation to the monitor area, it divides the core clock CLK into the SDAO signal and divides it by C.
The LK2 signal outputs a low level for one clock (cycle 2).

(3) The serial monitor bus circuit 34 outputs the addresses A [2] to A [19], Low (indicating writing), BE [0] * to BE output by the write bus operation of the processor core 20. [3] * Write data outputs DOUT [0] to DOUT [31] are output to the SDAO signal every one clock of CLK2 (cycles 3 to
57).

(4) The debugger 60 outputs Low for the SDI signal for one clock when the data write is completed (cycle n).

(5) The serial monitor bus circuit 34 uses the S
When Low is detected in DI, the response signal WRACK * of the write bus of the processor core 20 is asserted (cycle n + 1).

(6) The processor core 20 ends the write bus operation (cycle n + 1).

C) Read bus operation by CFC0 instruction FIG. 21 shows the timing of the read bus operation by the CFC0 instruction.

(1) When the processor core 20 starts the coprocessor read bus operation by the CFC0 instruction, A [31:21] is set to the address of the processor bus.
= 0100 — 0000 — 010 is output and CPRD * is asserted (cycle 1).

(2) When the serial monitor bus circuit 34 recognizes the start of the read bus operation to the monitor area, it divides the core clock CLK into the SDAO signal and divides it by C.
The LK2 signal outputs a low level for one clock (cycle 2).

(3) The serial monitor bus circuit 34 outputs the addresses A [2] to A [19] output from the coprocessor read bus operation of the processor core 20 to S.
The DAO signal is output for one clock of CLK2 (cycles 3 to 20). Next, High is output for one clock to indicate the read operation (cycle 2
1). Next, regardless of the byte enable signal of the processor bus, Low is output only for 4 clocks (cycles 22 to 25).

(4) The debugger 60 outputs Low for the SDI signal for one clock before outputting data (cycle n). The serial monitor bus circuit 34 goes low on SDI.
When ow is detected, data D [0]
D [31] is read every clock (cycle n +
1-n + 32).

(5) The serial monitor bus circuit 34 uses the response signal CP of the coprocessor read of the processor core 20.
Asserts RDACK * and sets data bus DIN [31:
The 32-bit data D [31: 0] read to 0] is output (cycle n + 33).

(6) The processor core 20 reads the data on the data bus DIN [31: 0] and ends the coprocessor read bus operation (cycle n +
33).

D) Write Bus Operation by CTC0 Instruction FIG. 22 shows the timing of the write bus operation by the CTC0 instruction.

(1) When the processor core 20 starts the coprocessor write bus operation by the CTC0 instruction, the processor bus address A [31:21] =
It outputs 0100_0000_110 and asserts CPWR * (cycle 1).

(2) When the serial monitor bus circuit 34 recognizes the start of the write bus operation to the monitor area, it divides the core clock CLK into the SDAO signal and divides it by C.
The LK2 signal outputs a low level for one clock (cycle 2).

(3) The serial monitor bus circuit 34 outputs the addresses A [2] to A [19] output by the coprocessor write bus operation of the processor core 20 to S.
The DAO signal is output for one clock of CLK2 (cycles 3 to 20). Next, Low is output for one clock to indicate the write operation (cycle 21).
Next, regardless of the byte enable signal of the processor bus, Low is output to the SDAO signal only for 4 clocks (cycles 22 to 25). Further, the values of the data bus outputs DOUT [0] to DOUT [31] are output to SDAO every one clock (cycles 26 to 57).

(4) The debugger 60 outputs Low for the SDI signal for one clock when the data write is completed (cycle n).

(5) The serial monitor bus circuit 34 uses the S
When Low is detected in DI, the response signal CPWRACK * of the coprocessor write bus of the processor core 20 is asserted (cycle n + 1).

(6) The processor core 20 ends the coprocessor write bus operation (cycle n +
1).

FIG. 23 shows a flowchart of the operation of the serial monitor bus control circuit 341.

Serial monitor bus control circuit 34
1 monitors the bus operation of the processor bus.

(1) Monitor area (address A [31: 2
0] = 0xFF2) read bus operation (RD
* = Assert (Low) in debug mode (D
M signal = High, the read bus operation of the serial monitor bus is started (steps S120 and S12).
4, S125).

(2) Monitor area (address A [31: 2
0] = 0xFF2) read bus operation (RD
* = Assert (Low)) and when not in the debug mode (DM signal = Low), the processor core 20
RDACK * is asserted to end the bus operation (steps S120, S124, S132, S
133).

(3) Monitor area (address A [31: 2
0] = 0xFF2) write bus operation (WR
* = Assertion (Low), debug mode (DM signal = High) and writing is possible (M in DCR register)
When P bit = 0, the write bus operation of the serial monitor bus is started (steps S120 and S1).
21, S126, S127).

(4) Monitor area (address A [31: 2
0] = 0xFF2) write bus operation (WR
* = Assert (Low)) and not in debug mode (DM signal = Low), or write protected (MP bit of DCR register = 1)
If so, WRACK * of the processor core 20 is asserted to end the bus operation (step S1).
20, S121, S126, S134, S135).

(5) CFC0 instruction (address A [31:
21] = 0100_0000_010) coprocessor read bus operation (CPRD * = assert (L
ow)) in debug mode (DM signal = High)
h), the coprocessor read bus operation of the serial monitor bus is started (steps S120 and S12).
1, S122, S128, S129).

(6) CFC0 instruction (address A [31:
21] = 0100_0000_010) coprocessor read bus operation (CPRD * = assert (L
ow)) and not in the debug mode (DM signal = L
ow), CPRDACK of the processor core 20
Assert * to end the bus operation (steps S120, S121, S122, S128, S1
36, S137).

(7) CTC0 instruction (address A [31:
21] = 0100_0000_110) coprocessor write bus operation (CPWR * = assert (L
ow)) in debug mode (DM signal = High)
h), the coprocessor read bus operation of the serial monitor bus is started (steps S120 and S12).
1, S122, S123, S130, S131).

(8) CTC0 instruction (address A [31:
21] = 0100_0000_110) coprocessor write bus operation (CPWR * = assert (L
ow)) and not in the debug mode (DM signal = L
ow), CPWRACK of the processor core 20
Assert * to end the bus operation (steps S120, S121, S122, S123, S13
8, S139).

FIG. 24 shows a flowchart of the operation of the serial monitor bus circuit 34 in the read bus operation of the serial monitor bus.

Serial monitor bus control circuit 34
In the read bus operation, 1 outputs High level to the serial monitor bus read / write signal, BE [3: 0] of the processor bus to the serial monitor bus byte enable signal, and High to all serial monitor bus data signals. , Assert the data load signal (cycle 1).

During the coprocessor read bus operation by the CFC0 instruction, the serial monitor bus control circuit 341 sets the serial monitor bus read / write signal to High level, the byte enable signal of the serial monitor bus to Low, and the serial monitor bus data. All signals are output as High, and the data load signal is asserted. The low level of these values and LSB is latched in the shift register 344.

Next, a low level is output to the SBAO signal. Serial monitor bus control circuit 341
Asserts the output shift signal (cycle 2).

Next, the serial monitor bus control circuit 341 asserts the output shift signal. SDAO
The signal latched in the output shift register 344 in cycle 1 is output every clock (cycles 3 to 2).
5).

Next, the serial monitor bus control circuit 341 waits for the SDI input signal to be asserted Low (cycles 26 to n).

Next, the serial monitor bus control circuit 341 asserts the input shift signal of the serial input circuit 343 and sets the value of the SDI input signal to the data input D.
[0] -D [31] as the input shift register 345
(Cycles n + 1 to n + 32).

Next, the serial monitor bus control circuit 341 asserts the read response signal RDACK * of the processor bus during the read bus operation. During coprocessor read bus operation,
Assert the coprocessor read response signal CPRDACK *. The output enable signal of the serial input circuit 343 is asserted. Data bus input signal DIN [31:
0] to the data D [31: of the input shift register 345.
0] is output (cycle n + 33).

FIG. 25 shows a flowchart of the operation of the serial monitor bus circuit in the write bus operation of the serial monitor bus.

First, during the write bus operation, the serial monitor bus control circuit 341 serially sets the serial monitor bus read / write signal to Low level and the serial monitor bus byte enable signal to BE [3: 0] of the processor bus. The data output DOUT [31: 0] is output to the monitor bus data signal, and the data load signal is asserted.

During the coprocessor write bus operation by the CTC0 instruction, the serial monitor bus control circuit 341 sets the serial monitor bus read / write signal to the low level and the serial monitor bus byte enable signal to the 4-bit low level, and then performs serial monitor. The data output DOUT [31: 0] is output to the bus data signal and the data load signal is asserted. The low level of these values and the LSB is latched by the output shift register 344 (cycle 1).

Next, a low level is output to the SDAO signal. Serial monitor bus control circuit 341
Asserts the output shift signal (cycle 2).

Next, the serial monitor bus control circuit 341 asserts the output shift signal. SDAO
Output to signal The value latched in cycle 1 is output to the shift register 344 every clock (cycles 3 to 5).
7).

Next, the serial monitor bus control circuit 341 waits for the SDI input signal to be asserted Low (cycles 58 to n).

Next, the serial monitor bus control circuit 341 asserts the write response signal WRACK * of the processor bus during the write bus operation. In the coprocessor bus operation, the coprocessor write response signal CPWRACK * is asserted (cycle n + 1).

Next, the PC trace circuit 32 will be described.

Here, the indirect jump, direct jump, and branch are defined as follows.

Indirect jump: A jump in which the jump destination cannot be specified by the instruction itself, such as using a value stored in a register or a memory as a jump destination address.

Direct jump: PC of instruction itself
Jumps can be specified by the (program counter) and the code in the instruction.

Branch (or conditional branch): PC of instruction itself
And a jump whose branch destination can be specified by the sum of a part of the code in the instruction. Whether the branch actually jumps depends on the condition. A jump is actually taken and a branch is taken (Branch Take), and a jump is not taken (Branch Not Take).
n).

[0225] Figure 26 shows the configuration of the PC trace circuit 32. The PC trace circuit 32 inputs the following signals from the processor core 20.

Debug mode signal DM: Indicates whether the current execution mode of the processor core 20 is the debug mode or the normal mode.

Pipeline execution signal: Indicates that one instruction has been executed.

30-bit target PC [31: 2]
Signal: branch instruction, target address of jump instruction,
Or it indicates the vector address of the exception. This is valid when the following indirect jump signal, direct jump signal, branch taken signal, and exception occurrence signal are asserted.

Indirect jump signal: Indicates that an indirect jump has been executed.

Direct jump signal: Indicates that a direct jump has been executed.

Branch taken signal: Indicates that a branch taken branch instruction has been executed.

Exception occurrence signal: Indicates that an exception has occurred.

Further, the PC trace circuit 32 outputs the following signals to the processor core 2 in order to perform the PC trace completely.
Output to 0.

Pipeline install request signal: This signal stalls the pipeline of the processor core 20 in order to completely output the target PC. PC
When the next indirect jap occurs while the target PC for the indirect jump is output, the trace circuit 32 asserts this signal and stalls the bipline of the processor core 20. When the output target PC is completely output, this signal is negated to restart the pipeline processing of the processor core 20.

The PC trace circuit 32 receives the trigger request signal from the instruction / data address break circuit 31 and the processor bus break circuit 33. The TM bit of the DCR register and the debug enable signal DBGE * are input. The debug enable signal, when asserted low, indicates that the debugger 60 is valid.

The PC trace circuit 32 converts the PC trace information output from the processor core 20 in the normal mode into a 1-bit PC output (TPC signal) and a 3-bit status signal (PCST [2: 0] signal). Output to the debugger 60.

The PCST [2: 0] and TPC signals will be described below.

A) PCST [2: 0] The instruction execution state is changed to PCST [2:
0]. (Indicates 0: Low, 1: High level.) -111 (STL): Pipeline installation Indicates that the instruction execution has not been completed without a trace trigger output request.

-110 (JMP): Branch / jump taken (with PC output) Execution of the branch instruction and jump instruction for branch taken is completed, and T
It indicates that the output of the target address (branch or jump destination address) has been started to the PC signal.

-101 (BRT): Branch / Jump taken (no PC output) Indicates that the execution of a branch taken branch instruction or a direct jump instruction has been completed. In this case, no target address is output to the TPC signal.

-100 (EXP): Exception occurred (exception vector code output) Indicates that an exception occurred. At the same time, it indicates that the code output of the exception vector to the TPC signal is started.

-011 (SEQ): Sequential execution (indicating that one instruction has been executed) If the branch / jump is not established (JMP, BRT) or the trace trigger output request (TSQ) is not executed, the instruction is executed. Indicates. This state also occurs when a branch instruction that does not branch is executed.

-010 (TST): Trace trigger output at pipeline stall Indicates that an address trace trigger or processor bus trace trigger has occurred at a clock at which instruction execution is not completed.

-001 (TSQ): Trace trigger output during execution Indicates that an address trace trigger or a processor bus trace trigger has occurred at the clock at which the execution of the instruction is completed.

-000 (DBM): Debug mode (this state does not occur in normal mode).

TPC is a signal for outputting the target address of a branch instruction or a jump instruction. PCST [2:
The output of the target address is started from the clock when 110 (JMP code) is output to [0]. The target address is output from the lower A (2) every one clock. The 3-bit code of the exception vector is output from the clock at which 100 (EXP code) is output to PCST [2: 0]. Codes are from lower code (0) to code
(1) and code (2) are output in order of one clock. The exception vector address and 3-bit code are shown below.

Vector Address code (2: 0) Reset, Nmi BFC0_0000 4 (100) UTLB (BEV = 0) 8000_0000 0 (000) UTFB (BEV = 1) BFC0_0100 6 (110) Others (BEV_0) 1 (BEV = 0) 1 001) Others (BEV = 1) BFC0_0187 7 (111) Since the target address is output in 1-bit serial by the TPC signal, while the previous branch jump instruction is being output to the TPC signal, the next branch, jump instruction or Exceptions may occur. The priority of the target address output to the TPC in this case will be specified.

A) When a new indirect jump occurs during the output of the target PC, the output of the target PC at that time is ended and the output of the target PC of the new indirect jump is always started.

B) When an exception occurs during target PC output, the exception vector number (3 bits) is always output, and then the interrupted PC output is restarted.

C) When a new direct jump or branch occurs during output of the target PC, the target address of the direct jump or branch is not output. For direct jump and branch, the target PC is output only when the target PC is not output at the time of occurrence.

Next, a PC trace output example will be described with reference to the drawings.

(Example 1) PC trace of a branch instruction FIG. 27 shows an example of PC trace output of a branch instruction.

In the branch instruction beq for the first branch taken, T
Since the target PC is not output to PC, PCST
The JMP code is output at [2: 0] and the output of the target PC to the TPC is started. Branch instruction bne not taken
Then, the SEQ code is output to PCST [2: 0].
In the branch instruction bne for which the second branch is taken, since the target PC of the first branch instruction is output, the target PC is not output to TPC. BR for PCST [2: 0]
Output T code.

(Example 2) P of the indirect jump instruction
C Trace FIG. 28 shows an example of PC trace output of the indirect jump instruction.

First indirect jump instruction jr1
Then, output the JMP code to PCST [2: 0], and
Start outputting the target PC to the PC. In the branch instruction bne that does not branch, the SEQ code is output to PCST [2: 0]. Second indirect jump instruction j
At r2, the output of the target PC of the first indirect jump instruction is stopped, and the target PC of jr2 is output to the TPC. The JMP code is output to PCST [2: 0].

(Example 3) PC trace of exception and indirect jump instruction FIG. 29 shows an example of PC trace output of exception and indirect jump instruction.

An exception occurs at the software break instruction break. The EXP code is output to PCST [2: 0], and the output of the exception vector code is started to TPC.
PCST [2: 0] for the branch instruction bne for which the branch is not taken.
The SEQ code is output to. In the indirect jump instruction jr2, the target PC of jr2 is output to TPC, and the JMP code is output to PCST [2: 0].

Next, the output of the trace trigger to the PCST [2: 0] signal will be described.

In the instruction / data address break and the processor bus break, when the bus cycle that matches the set address and data is executed, the trace trigger information is output to the PCST [2: 0] signal.

When a request for an instruction address trace trigger, a data address trace trigger, or a processor bus trace trigger occurs, the trace trigger information TSQ code or TST code is output to the PCST [2: 0] signal. However, if PCST [2: 0] is added with JMP, BRT,
TS of trace trigger when EXP code is output
The output of the Q and TST codes is delayed. When there is no trace trigger request, PCST [2: 0] output is SEQ code,
The TSQ code and the TST code are output to the PCST [2: 0] signal at the clock that is the STL code.

(A) Instruction / data address trace trigger In the instruction / data address trace trigger, PCST
At the timing of outputting the trace information of the instruction in which the trace trigger has occurred to the [2: 0] signal, PCST [2:
0] signal, the trace trigger information TSQ is output. However, if the instruction that generated the trace trigger is a branch instruction with a successful branch, a jump instruction, or an instruction that generated an exception,
Normally, when the PCST [2: 0] output is not the SEQ code, the output of the trace trigger is delayed. When there is no trace trigger request, PCST [2: 0] output is SEQ, ST
PC with TSQ code and TST code with L clock
Output to the ST [2: 0] signal.

(Example 1) Generation example of instruction / data address trace trigger FIG. 30 shows a generation example of an instruction / data address trace trigger.

P by the add instruction that generated the instruction address trace trigger or the data address trace trigger
Trace trigger code TS to CST [2: 0] signal
Output Q.

(Example 2) Example in which instruction / data address trace trigger is generated by exception generation instruction FIG. 31 shows an example in which instruction / data address trace trigger is generated by exception generation instruction.

When an instruction address trace trigger or a data address trace trigger occurs in the software break instruction break, the break instruction causes P
Exception generation code EXP is output to the CST [2: 0] signal, and a trace trigger code is output at the next clock. In this example, the TST code is output because it is in the stalled state.

(Example 3) Example in which instruction / data address trace trigger is generated by indirect jump instruction FIG. 32 shows an example in which instruction / data address trace trigger is generated by indirect jump instruction.

When the instruction address trace trigger or the data address trace trigger is generated by the indirect jump instruction jr2, PCST is executed by the jr2 instruction.
The jump code JMP is output to the [2: 0] signal, and the trace trigger code is output at the next clock. In this example, since the instruction is being executed, the TSQ code is output.

(B) Processor Bus Trace Trigger When a processor bus trace trigger request is issued, P
The trace trigger information TSQ code or TST code is output to the CST [2: 0] signal. However, PCST
If the JMP, BRT, and EXP codes are output at [2: 0], the output of the TSQ and TST codes of the trace trigger will be delayed. PCST when there is no trace trigger request
The [2: 0] output becomes the SEQ code and the STL code, and the TSQ code and the TST code are changed to PCST [2:
0] signal.

Next, the output of the debug mode DBM code will be described.

When the processor core 20 generates a debug exception or a debug reset, the debug mode signal DM is asserted High to enter the debug mode. The PC trace circuit 32 outputs the DBM code to the PCST [2: 0] output.

FIG. 33 shows PCST when a debug exception occurs.
The output timing of [2: 0] is shown.

When the target PC is not output,
Immediately after execution of the instruction that caused the debug exception, the debug mode is entered. The PC trace information up to the instruction immediately before the debug exception occurred is output.

FIG. 34 shows PCST [2: 0] output timing when the target PC is being output when a debug exception occurs.

When the target PC is being output, the debug mode is entered after the target PC output is completed. The PC trace information up to the instruction immediately before the debug exception occurred is output. While the target PC is being output, STL is output to PCST [2: 0].

FIG. 35 shows P when returning from the debug mode.
The output timing of CST [2: 0] is shown.

Debug exception, return instruction from debug mode The branch delay slot instruction of the DERET instruction enters the debug mode. From the instruction to which the DERET instruction has returned, the normal mode is entered and PC trace is enabled.

Next, returning to FIG. 26, the PC trace circuit 32 will be described.

In FIG. 26, the PC trace circuit 32
Is a PC trace control circuit 321, a target PC shift register 322, an exception vector coding circuit 3
23, exception code shift register 324, selector 32
It consists of 5.

The PC trace control circuit 321 is
Exception code output status bit 326, target P
A C output counter 329 is included.

Next, the operation of the PC trace circuit 321 will be described.

PCST [2: when the TM bit is 0:
0] output is as shown in Table 3. In Table 3, 1 indicates active and x indicates don't care.

[0282]

[Table 3] In Table 3, the trigger request signal is the logical sum of the instruction address trace trigger request signal, the data address trace trigger request signal and the processor bus trace trigger request signal.

5-bit target PC output counter 3
When 27 is not 0, it indicates that TPC is being output. When the exception code output status bit is 1, it indicates that the exception vector code is being output. The internal status indicating that the target PC or exception code is being output in Table 3 is 1 when the target PC output counter 327 is not 0 or the exception code output status 326 is 1.

The target PC output counter 327 is updated as follows.

(1) The target PC output counter 327 is cleared to 0 when the target PC is not output to the TPC signal or when a new PC output is started.

(2) When the exception vector is being output to the TPC signal, the internal state indicating that the PC is being output and the counter retain the same value.

(3) When the counter value reaches 30, the target PC output counter 327 is set to 0. This indicates that the output of the target PC has ended.

(4) In cases other than (1), (2) and (3), the value of the target PC counter 327 is incremented by 1. In this state, the value of the target PC is output as the TPC signal.

As for the exception code output status 326, when an exception occurs, the internal state indicating that the exception code is being output is asserted for 3 clocks. When the exception code output status 326 is asserted, the exception code shift signal and the exception code output switching signal are asserted. The exception code load signal is PCST [2:
0] is asserted on condition that an EXP code is output, and the value of the exception vector code output from the exception vector coding circuit 323 is loaded into the exception code shift register 324.
The target PC load signal is PCST [2:
0] is asserted on condition that the JMP code is output, and the value of the target PC is loaded into the target PC shift register 322. The target PC shift signal is asserted when the value of the target PC counter 327 is not 0 and the exception code output status 326 is not asserted.

When the TM bit of the DCR register is set to 1, PC trace is completed. When the DBGE * signal is asserted and the TM bit of the DCR register is set, the PC trace control circuit 321 generates the next indirect jump when the target PC of the indirect jump is output. The pipeline install request signal is asserted to stall the pipeline of the processor core 20.
When the output target PC is completely output, the pipeline install request signal is negated to restart the pipeline processing of the processor core 20.

PCST [2: when TM bit is 1]
0] output is as shown in Table 4. In Table 4, 1 is active and x is don't care.

[0292]

[Table 4] When the next indirect jump is executed while the target PC or the exception code is being output and the indirect jump signal becomes active, the pipeliner installation request signal of the processor core 20 becomes active. The internal state of the target PC or exception code output becomes active for 30 clocks from the start of target PC output.

The target PC shift register 322 is
Target PC of PC trace control circuit 321
When the load signal is asserted, it loads the value of the target PC. In addition, the PC trace control circuit 32
When the target PC shift signal of 1 is asserted, the value of the target PC shift register 322 is changed from MSB to L.
Shift 1 bit to SB.

The exception vector coding circuit 323 sets the exception vector address to A [2 of the vector address as follows.
9], A [8], A [7].

Vector Address (A29, A8, A7) code reset, Nmi BFC0_0000 (100) 4 UTLB (BEV = 0) 8000_0000 (000) 0 UTLB (BEV = 1) BFC0_0100 (110) 6 Other (BEV = 0) 8000_0080 (001) 1 Other (BEV = 1) BFC0 — 0180 (111) 7 The exception vector coding circuit 323 outputs the addresses A [29], A [8], A [7] of the target PC to the exception code shift register.

The exception code shift register 324 is a PC
When the exception code load signal of the trace control circuit 321 is asserted, the exception vector coding circuit 323
Load the exception vector code of the output of. When the exception code shift signal of the PC trace control circuit 321 is asserted, the exception code shift register 324
The value of is shifted from MSB to LSB by 1 bit.

When the exception code output switching signal of the PC trace control circuit 321 is asserted, the selector 325 outputs the LSB of the exception code shift register 324.
The value of is output to TPC. When the exception code output switching signal is negated, the LSB value of the target PC shift register 322 is output to the TPC.

Next, an operation example of the PC trace circuit 32 will be described with reference to a timing chart.

FIG. 36 shows an operation example when the target PC outputs. When the indirect jump signal, the direct jump signal, or the branch taken signal is asserted when the target PC output counter 327 is 0, the PC trace control circuit 321 asserts the target PC load signal.

At the next clock, the LS of the target address loaded in the target PC shift register 322
B bit A [2] is output to TPC, PCST
The JMP code is output at [2: 0], and the PC trace control circuit 321 asserts the target PC shift signal. The target PC shift register 322 is M
One bit is shifted from SB to LSB, and A [3] is output at the next clock. The target PC shift signal is asserted until the target PC output counter 327 reaches 30, and the value of the target PC is T every clock.
Output to PC. Target PC output counter 327
Value of 30 is then cleared to 0, the target PC shift signal is negated, and the target PC output to the TPC ends.

FIG. 37 shows an example of the operation timing when the next indirect jump occurs during the output of the target PC.

When the second indirect jump occurs, the target PC output counter is cleared to 0,
The target PC load signal is asserted. At the next clock, A [2] of the LSB bit of the target address loaded in the target PC shift register 322 is T
It is output to the PC, the JMP code is output to PCST [2: 0], and the PC trace control circuit 321 asserts the target PC shift signal. Target address is 1 bit per cycle from the next clock TPC
It is output to the signal.

FIG. 38 shows an example of operation timing when an exception occurs during output to the target PC.

When the exception occurrence signal is asserted during the output of the target PC, the exception code load signal is asserted and the value of the exception code is set to the exception code shift register 324.
Is loaded into. From the next clock, the exception code output status 326, the exception code shift signal, and the exception code output switching signal are asserted. The exception code is output for 3 clocks. During this period, the target PC shift signal is negated. When the exception code output status 326 and the exception code switching signal are negated, the target P
Output of C to TPC begins.

FIG. 39 shows the external interface circuit 36.

The external interface circuit 36 is a DBM.
Code detection circuit 361, selectors 362 and 363, mask circuits 364, 365, 366, output buffer 367
A, 367B, 367C, input buffer with pull-up resistor 368A, 368B, 368C, input buffer 36
It consists of 9A and 369B.

The DBM code detection circuit 361 uses the PCST
Code DBM (000) in debug mode at [2: 0]
Asserts the output signal when is output.

The selector 362 outputs the divided clock CLK2 when the output of the DBM code detection circuit 361 is asserted, that is, in the debug mode, and D
When the output of the BM code detection circuit 361 is negated, that is, in the normal mode, the core clock C
LK is output.

When the output of the DBM code detection circuit 361 is asserted, that is, in the debug mode, the selector 363 outputs S of the serial monitor bus circuit 34.
When DAO is output and the output of the DBM code detection circuit 361 is negated, that is, in the normal mode, the TPC of the PC trace circuit 32 is output.

The mask circuit 364 masks the value of the external DINT * / SDI input so that the DINT * input of the processor core is always negated in the debug mode.

The mask circuit 365 is the M of the DCR register.
When Int is 0, Int [5: 0] of the processor core
Set * to High to mask interrupts.

The mask circuit 366 is used for the M of the DCR register.
When Rst is 0, debug exception handler is being executed (DM
Signal = High) Mask user reset.

The output buffer 367A has a selector 362.
Is output as DCLK to the outside. The output buffer 367B outputs the output of the selector 363 to TPC / SDAO.
To the outside as. The output buffer 367C is a PC
PCST [2: 0] of the output of the trace circuit 32 is set to external P
Output as CST [2: 0].

Input buffer 368A with pull-up resistor
Inputs an external DINT * / SDI signal to the inside. Since it has a pull-up resistor, the output is always at High level when the external DINT * / SDI signal is not connected. The input buffer 368B with pull-up resistor is an external DBG
Input the E * signal internally. With pull-up resistor, output is always High when external DBGE * signal is not connected.
It becomes the h level. Input buffer 36 with pull-up resistor
8C inputs the external DRESET * signal internally. Since it has a pull-up resistor, the output is always at High level when the external DRESET * signal is not connected.

External DINT * / SDI signal, external DBG
The E * signal and the external DRESET * signal are not connected when the debugger is not connected. Internally, these input signals become High level, and the function of the debug module is disabled.

The input buffer 369A inputs the external interrupt signal INT [5: 0] *. Input buffer 369
B inputs the external user reset signal RESET *.

FIG. 41 is a diagram showing the structure of a microprocessor and a debug system according to an embodiment of the present invention.

In this embodiment, the microprocessor 1
0 has a built-in memory 90 and a peripheral circuit 100, and other configurations are the same as those in the above embodiment.

The processor core 20 reads and executes the program of the memory 90 via the internal processor bus 80, reads or writes data on the memory 90, and the processor core 20 accesses the built-in peripheral circuit 100. The processor core 20 executes the monitor program on the debugger via the debug module 30 in the debug mode.

Also in this embodiment, if the functions and timings of the interface signals of the debug module and the debugger are the same, the same debugger 6 as that of the above embodiment will be used regardless of the difference between the built-in memory 90 and the peripheral circuit 100.
0 can be used.

Further, if the function of the processor core 20 is the same as that of the above embodiment, the same monitor program on the debugger 60 can be used.

In the two embodiments described above, the instruction /
The case where the number of data address breaks and the number of processor bus break channels are 1 has been described as an example, but the present invention is not limited to this configuration. It can be applied even if the number of channels is two or more. FIG. 40 shows the configuration of the IBS register when the number of instruction address break channels reaches 15.

In the two embodiments described above,
The case where the bit width of the serial monitor bus is 1 bit has been described as an example, but the present invention is not limited to this configuration. If more microprocessor external signals are available for the serial monitor bus, the bit width can be more than 2 bits.

Furthermore, in the above-mentioned two embodiments, an example in which the output of the target PC is performed using one external signal has been described, but the present invention is not limited to this configuration. If more microprocessor external signals are available for target PC output,
Target PC output can be done using multiple external signals.

Furthermore, in the above two embodiments, the clock supply circuit 37 outputs the clock signal (CLK) to 2
Although it was a frequency dividing circuit, the present invention is not limited to this configuration. It is also possible to output a clock signal having the same frequency as the clock signal (CLK) or an integral multiple or a power of 2 of the clock signal (CLK), and use this clock signal as the operation clock signal of the serial monitor bus circuit.

As described above, according to the present invention, the hardware specifications of the debug tool can be made common, and the number of signals for connection with the debug tool can be reduced. For example, in the conventional method, a user target system and a debugger are combined with 30 address signals, 4 byte enable signals, read signals, write signals, read response signals, write response signals, 32 data signals, for a total of 70 signals. It was necessary to connect, but in this system, it is sufficient to connect with eight signals. This makes the probe smaller,
The price can be reduced.

Since the microprocessor on the user target accesses the memory and I / O, the timing condition required for the debug tool is improved. It has no effect on signals that are not connected to the debug tool. The communication speed between the debug tool and the microprocessor can be slowed down if necessary. This makes it possible to support a high-speed microprocessor.

Further, the following effects can be obtained as compared with the conventional example shown in FIG. Since the monitor program is executed in the memory on the debug tool side, the user's memory is not used. Since a dedicated debug exception and debug reset are provided to enter the monitor, the user interrupt is not limited. There is no need to provide a serial interface in the user target system. Hardware breakpoints are available.

On the other hand, as compared with the conventional example shown in FIG. 44, since it is not necessary to have a sequencer inside the microprocessor, the logic circuit for debugging added inside the microprocessor becomes simple. Since the monitor program accesses the registers, even if the microprocessor of the derivative product adds the registers, it is possible to easily access the registers by changing the monitor program.

[0330]

As described above, according to the present invention, the microprocessor on the user target system is provided with the debug function. Therefore, the microprocessor on the user target system is provided with the debug function. It is possible to reduce the signal required for connection with. Further, since the microprocessor is made to operate on the user target system even during debugging, it is possible to easily access the memory and I / O on the user target system.

According to the tenth aspect of the invention, since the debug tool and the control register in the debug module cannot be accessed during execution of the user program (normal mode), the debug tool is executed by the user program. The memory and registers used in will not be accidentally destroyed, and a highly reliable debug system can be realized.

Further, according to the invention of claim 11,
Even after the processor core enters the debug mode, access to the control register in the debug tool and the debug module is prohibited. It is possible that the processor core generated a debug exception and entered debug mode, but the write operation of the immediately preceding user program has not yet completed. At this time, even if the write is a write to the control register in the debug tool or the debug module, the write access can be prohibited if the MP bit is set. As a result, the memory and registers used by the debug tool are not accidentally destroyed by the user program, and a highly reliable debug system can be realized.

According to the twelfth or thirteenth aspect of the invention, writing to the debug tool by the CTC0 instruction in the debug mode is always possible regardless of the value of the MP bit of the DCR register, and Unlike the memory write instruction, it is not necessary to use the general purpose register to make the address of the monitor area.

Therefore, it is possible to save the value of the general-purpose register in the memory on the debug tool immediately after the occurrence of the debug exception, without overwriting the contents of the general-purpose register. In this way, the debug tool does not overwrite the contents of the general-purpose registers used by the user, and a highly transparent debug system can be realized.

Further, according to the present invention, the microprocessor on the user target is provided with the debug function, so that the interface signals required for the PC trace output can be reduced.

Further, according to the present invention, the trigger function can be realized with the minimum hardware by providing the microprocessor on the user target with the debug function.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a microprocessor and a debug system according to an embodiment of the invention described in claim 1 or 2.

FIG. 2 is a diagram showing a configuration of a debug module of the embodiment shown in FIG.

FIG. 3 is a diagram showing a configuration of a register circuit of the embodiment shown in FIG.

4 is a diagram showing a configuration of a DCR register in the register unit shown in FIG.

5 is a diagram showing a configuration of an IBA0 register in the register unit shown in FIG.

6 is a diagram showing a configuration of an IBC0 register in the register unit shown in FIG.

7 is a diagram showing a configuration of an IBS register in the register unit shown in FIG.

8 is a diagram showing a configuration of a DBA0 register in the register unit shown in FIG.

9 is a diagram showing a configuration of a DBC0 register in the register unit shown in FIG.

10 is a diagram showing a configuration of a DBS register in the register unit shown in FIG.

11 is a diagram showing a configuration of a PBA0 register in the register unit shown in FIG.

12 is a diagram showing a configuration of a PBD0 register in the register unit shown in FIG.

13 is a diagram showing a configuration of a PBM0 register in the register unit shown in FIG.

14 is a diagram showing a configuration of a PBC0 register in the register unit shown in FIG.

15 is a diagram showing a configuration of a PBS register in the register unit shown in FIG.

16 is a diagram showing a configuration of an instruction / data address break circuit of the debug module unit shown in FIG.

17 is a diagram showing a configuration of a processor bus break circuit of the debug module unit shown in FIG.

18 is a diagram showing a configuration of a serial monitor bus circuit of the debug module unit shown in FIG.

FIG. 19 is a timing diagram of a read operation of the serial monitor bus.

FIG. 20 is a timing diagram of a write operation of the serial monitor bus.

FIG. 21 is a timing diagram of a serial monitor bus read operation by a CFC0 instruction of the serial monitor bus.

FIG. 22 is a timing diagram of a write operation of the serial monitor bus according to the CTC0 instruction of the serial monitor bus.

FIG. 23 is a diagram showing an operation flow of the serial monitor bus control circuit shown in FIG. 18.

FIG. 24 is a diagram showing an operation flow of a read bus operation of the serial monitor bus.

FIG. 25 is a diagram showing an operation flow of a write bus operation of the serial monitor bus.

FIG. 26 is a diagram showing the configuration of a PC trace circuit of the debug module unit shown in FIG.

FIG. 27 is a timing diagram of PC trace output of a branch instruction.

FIG. 28 is a timing diagram of PC trace of an indirect jump instruction.

FIG. 29 is a timing chart of PC trace output of an exception and an indirect jump instruction.

FIG. 30 is a timing diagram of an instruction / data address trace trigger.

FIG. 31 is a timing diagram when an instruction / data address trace trigger is generated by an exception generation instruction.

FIG. 32 is a timing diagram when an instruction / data address trace trigger occurs with an indirect instruction.

FIG. 33 is a timing diagram of PCST [2: 0] output when a debug exception occurs.

FIG. 34 is a timing diagram of PCST [2: 0] output when a debug exception occurs during target PC output.

FIG. 35: PCST when returning from debug mode
FIG. 6 is a timing diagram of [2: 0] output.

FIG. 36 is a timing diagram of output from the target PC.

FIG. 37 is a timing diagram when the next indirect jump occurs while outputting the target PC.

FIG. 38 is a timing diagram when an exception occurs during target PC output.

39 is a diagram showing a configuration of an external interface circuit of the embodiment shown in FIG.

FIG. 40 is a diagram showing an extension example of an IBS register.

FIG. 41 is a diagram showing a configuration of a debug system according to an embodiment of the invention as set forth in claim 3;

FIG. 42 is a diagram showing a configuration of a debug system for debugging a conventional user target system.

FIG. 43 is a diagram showing another configuration of a debug system for debugging a conventional user target system.

FIG. 44 is a diagram showing still another configuration of the debug system for debugging the conventional user target system.

[Explanation of symbols]

 10 Microprocessor 20 Processor Core 30 Debug Module 31 Instruction / Data Address Break Circuit 32 PC Trace Circuit 33 Processor Bus Break Circuit 34 Serial Monitor Bus Circuit 35 Register Circuit 36 External Interface Circuit 37 Dividing Circuit 40 Memory 50 I / O 60 Debugger 70 User target system 80 system bus

Claims (26)

[Claims] 1. A processor core for executing a monitor program for debugging a user program and a user target system, and a processor core connected to the processor core via an internal debug interface or a processor bus to enable the processor core to execute the monitor program. And a debug module having an execution control means for requesting an interrupt or an exception for the processor core to shift from the user program to the monitor program while the processor core is executing the user program. A microprocessor having. 2. A debug tool including a monitor program for debugging a user target system, a processor core for executing a user program or a monitor program, and a processor core connected to the processor core via an internal debug interface or a processor bus.
An interface unit with the debug tool, which is connected to the debug tool through an external debug interface and allows the processor core to execute a monitor program, and a monitor program from the user program while the processor core is executing the user program. And a microprocessor including a debug module having an execution control means for requesting an interrupt or an exception to shift to the processor core, and a user target system to be debugged, which is connected to the microprocessor by a processor bus However, a memory that stores information necessary for the microprocessor to execute a user program and a memory that is connected to the microprocessor via a processor bus are not a target for debugging. Debugging system characterized by having a I / O device to configure a user target system. 3. The debug module inputs an address of an instruction or data output from the processor core, and when the value matches the preset address, a break requesting an address break exception to the processor core. A circuit, connected to the processor core by the processor bus,
A processor bus break circuit that monitors a bus cycle on the processor bus and requests an exception to the processor core when a preset address and data bus cycle is executed; and the processor core by the processor bus. A serial monitor bus circuit that is connected and that interfaces when the processor core executes a monitor program on a debug tool and information that controls the function of the debug module are stored, and the stored information is read / written by the processor core. A register circuit to be written, the serial monitor bus circuit, an external interface circuit that controls the interface between the processor core and the debug tool, and transfer of signals that are input / output between the microprocessor and the debug tool 3. A microprocessor or a debug system according to claim 1 or 2, further comprising a clock signal supply circuit for supplying a clock signal defining a speed to the debug tool. 4. The microprocessor or debug system according to claim 3, wherein the clock signal supply circuit supplies a clock signal having a cycle of an integer multiple of the clock signal for operating the processor core or a power of two. . 5. The connection signal between the debug module and the debug tool is used only for connection with the debug tool.
Microprocessor or debug system as described. 6. The microprocessor or debug system according to claim 1, wherein all connection signals between the debug module and the debug tool are unidirectional signals. 7. The debug module sequentially outputs a plurality of address signals or bus control signals of the processor core to the debug tool at preset time intervals when the processor core accesses a specific address area. Then, when the processor core makes a write access, a data output signal is further sequentially output to the debug tool at a preset time interval,
When the processor core performs read access, input signals from the debug tool are sequentially input at preset time intervals, a data signal of a plurality of bits is configured and output to the processor core. Item 1,
2. The microprocessor or debug system according to 2, 3, 4, 5 or 6. 8. The microprocessor or debug system according to claim 7, wherein the preset time interval is defined by an output clock of the clock signal supply circuit. 9. The debug module and the debug tool transfer a plurality of bus interface signals of the processor core serially to the debug tool via one first transfer line, and transfer the plurality of bus interface signals to the debug tool. 9. The microprocessor or debug according to claim 1, 2, 3, 4, 5, 6, 7 or 8, wherein information is transferred from said debug tool to said debug module serially via two transfer lines. system. 10. The processor core has a mode signal which becomes valid when an exception or a reset requesting a transition to a monitor program is generated, and the debug module has the processor core only when the mode signal is valid. 5. The register circuit in the debug tool or the debug module can be accessed from the device.
Microprocessor or debug system as described. 11. The processor core has a mode signal that becomes valid when an exception or a reset requesting a transition to a monitor program is generated, and the debug module has a control bit for prohibiting access to the debug module. When the control bit is valid, the access to the register circuit in the debug tool or the debug module from the processor is prohibited even if the mode signal is valid. 2. The microprocessor or debug system according to 2 or 4. 12. The processor core has a mode which becomes valid when an exception or a reset requesting a transition to a monitor program is generated, and outputs the value of a general-purpose register to a data signal and also outputs a first write signal. 2. A first write instruction for making valid and a second write instruction for making the value of the general-purpose register output to the data signal and making the second write signal valid.
2. The microprocessor or debug system according to 2 or 4. 13. The debug module has a control bit for prohibiting access to the debug module, and prohibits write access to the debug module by the first write signal when the control bit is valid. 13. The microprocessor or debug system according to claim 12, wherein write access to the debug module by the second write signal is permitted regardless of the value of the control bit. 14. A processor core for executing a program, the address value of an instruction being executed, which is connected to the processor core via an internal debug interface, and is output from the processor core, A PC trace circuit that outputs to a PC output signal of a number smaller than the width, and a microprocessor. 15. The processor core, when executing an indirect jump instruction, enables an indirect jump enable signal indicating the indirect jump instruction, and outputs the value of the jump destination address of the indirect jump instruction to the PC trace circuit. When the indirect jump enable signal becomes valid, the PC trace circuit inputs the jump destination address from the processor core and outputs the jump destination address to the PC output signal from the lower bit of the address. 15. The microprocessor according to claim 14, wherein the information indicating that the output of the jump destination address is started is output to the PC status signal. 16. The processor core, when an exception occurs, validates an exception valid signal indicating the exception and outputs a value of a jump destination address corresponding to the exception to the PC trace circuit. Indicates that when the exception valid signal becomes valid, the jump destination address is input from the processor core, the jump destination address is encoded into information of a small number of bits, and the output of the exception jump destination address is started. Information is transferred to the PC status signal
16. The microprocessor according to claim 14, wherein the microprocessor outputs the C output signal. 17. When the PC trace circuit outputs a jump destination address of a first indirect jump, when the processor core executes a second indirect jump, the processor core includes: When the second indirect jump instruction is executed, the indirect jump valid signal indicating the second indirect jump instruction is validated, and the value of the jump destination address of the second indirect jump instruction is output to the PC trace circuit. The circuit inputs the jump destination address of the second indirect jump from the processor core when the indirect jump enable signal corresponding to the second indirect jump becomes valid, and the jump destination of the first indirect jump is input. 2nd indirect after stopping address output The jump destination address of the Jump is output to the PC output signal, the microprocessor of claim 15, wherein the information indicating that it has started the output of the jump destination address to output to the PC status signal, characterized by. 18. When the PC trace circuit outputs a jump destination address of an indirect jump, when the processor core generates an exception, when the processor core generates the exception, The exception valid signal indicating that is validated, the value of the jump destination address corresponding to the exception is output to the PC trace circuit, and the PC trace circuit causes the exception from the processor core when the exception valid signal becomes valid. Of the indirect jump, the output of the jump destination address of the indirect jump is temporarily suspended, the jump destination address of the exception is coded into information of a small number of bits, and is output to the PC output signal. Information indicating that the output of the jump destination address is started is output to the PC status signal, and the exception After the output of the code is completed, the microprocessor of claim 15, 16 or 17 wherein a, outputs a jump destination address of the indirect jump that has been suspended. 19. The processor core, when executing a direct jump instruction or a conditional branch instruction of branch success, validates a direct jump enable signal indicating the instruction, and sets the jump destination address of the direct jump instruction or the conditional branch instruction. A value is output to the PC trace circuit, and when the direct jump valid signal becomes valid, the PC trace circuit outputs the jump destination address from the processor core when not outputting the jump destination address of the indirect jump. Input, output the jump destination address from the lower bit of the address to the PC output signal, and output the information indicating that the output of the jump destination address is started to the PC status signal, and the jump destination of the indirect jump. When outputting the address Simply microprocessor of claim 15, 16, 17 or 18, wherein the, for outputting information indicating execution of the conditional branch instruction of the execution of the direct jump or branch success to the PC status signal. 20. The processor core outputs a pipeline execution signal that becomes valid when an instruction is executed, and the PC trace signal inputs the pipeline execution signal from the processor core to output the pipeline execution signal. Information indicating that an instruction has been executed in the processor core is output to the PC status signal when the line execution signal is valid, and information indicating that the instruction has not been executed when the pipeline execution signal is invalid. Is output to the PC status signal.
The microprocessor according to 17, 18 or 19. 21. When the PC trace circuit is outputting a first indirect jump destination address,
When the processor core executes the second indirect jump instruction, when the processor core executes the second indirect jump instruction, the processor core validates an indirect jump enable signal indicating the second indirect jump instruction, The value of the jump destination address of the indirect jump instruction is output to the PC trace circuit, and when the processor core stop signal becomes valid, the execution is temporarily stopped, and the PC trace circuit corresponds to the second indirect jump. When the indirect jump enable signal is enabled, the processor core stop signal is enabled,
Complete the output of the first jump destination address, then input the jump destination address of the second indirect jump from the processor core, and output the jump destination address of the second indirect jump to the PC output signal. 15. The microprocessor according to claim 14, wherein the information indicating that the output of the jump destination address is started is output to the PC status signal. 22. When the PC trace circuit is outputting a first indirect jump destination address,
When the processor core executes the second indirect jump instruction, when the processor core executes the second indirect jump instruction, the processor core validates an indirect jump enable signal indicating the second indirect jump instruction, The value of the jump destination address of the indirect jump instruction is output to the PC trace circuit, and when the processor core stop signal becomes valid, the execution is temporarily stopped, and the PC trace circuit outputs the jump destination output of the indirect jump. In a mode that has a trace mode signal input indicating whether or not to perform completely and outputs the jump destination of the indirect jump completely, when the indirect jump valid signal corresponding to the second indirect jump becomes valid,
The processor core stop signal is enabled, the output of the first jump destination address is completed, and then the jump destination address of the second indirect jump is input from the processor core, and the jump destination of the second indirect jump is input. In the mode in which the address is output to the PC output signal, the information indicating that the output of the jump destination address is started is output to the PC status signal, and the jump destination of the indirect jump is not completely output, the second indirect When the indirect jump valid signal corresponding to the jump becomes valid, the jump destination address of the second indirect jump is input from the processor core, and the output of the jump destination address of the first indirect jump is stopped, Jump destination address for the second indirect jump The output to the PC output signal, the microprocessor of claim 14, wherein outputting the information indicating that it has started the output of the jump destination address to the PC status signal, characterized by. 23. The processor core executes a monitor program for debugging a user program and a user target system, and when an interrupt or exception for shifting to the monitor program during execution of the user program is externally requested, The execution of the user program is interrupted, the monitor program is jumped to perform the instruction fetch of the monitor program, and the PC trace circuit outputs the jump target address or the exception code even when the processor core jumps to the monitor program. 2 is delayed, the instruction fetch of the processor core is delayed until these outputs are completed.
4,15,16,17,18,19,20,21 or 2
2. The microprocessor according to 2. 24. A break to the processor core when the processor core that executes the program matches the set address and the accessed address, or when the set address and data match the accessed address and data. Or a break circuit for validating the trigger output request signal, and P for outputting the information to the external status signal when the trigger output request signal from the break circuit is validated.
A microprocessor having a C trace circuit. 25. The PC trace circuit encodes the internal state information of the processor core and outputs it as an external status signal, and when the processor core is in the first internal state, the trigger output request signal is valid. Even if, the information is output to the external status signal without outputting the information to the external status signal, the information of the same internal state as when there is no trigger request, and the processor core is in the second internal state, 25. The microprocessor according to claim 24, wherein when the trigger output request signal becomes valid, information indicating that a trigger has occurred is output to an external status signal. 26. The first internal state is execution of a jump instruction or the occurrence of an exception, and the second internal state is sequential execution of an instruction or pipeline stall. 25. The microprocessor according to 25.