JPH09191252A - Current addition type d/a converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a layout area in an IC without deteriorating conversion precision. SOLUTION: Two sets of current mirror circuits 11, 12 have a series circuit group consisting of MOS transistors(TRs) Q1 -Q7 and source resistors R1 -R7 . Thus, it is not required to make a voltage between a gate of the MOS TR and a DC power supply VDD equal between a high order bit group 11 and a low-order bit group 12 and the voltage drop by each source resistor and gate- source voltage of each MOS TR are adjusted uniquely to each group and values of R1 /R7 and W7 /W1 are reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a current-summing digital / analog (hereinafter referred to as D / A) conversion circuit composed of a metal oxide semiconductor field effect transistor (hereinafter referred to as MOS transistor).

[0002]

2. Description of the Related Art FIG. 5 is a circuit diagram showing an example of a conventional current addition type D / A converter. In the figure, 1 is a DC power source (hereinafter referred to as V _DD ), 2 is a ground point (hereinafter referred to as GND), 3 is a constant current source, 4 is an output resistance, and Q _{1 to} Q _n are D with a bit number n.
A / A conversion P-channel MOS transistor (hereinafter simply referred to as a PMOS transistor), R _{1 to} R _n are source resistors connected between the sources of the MOS transistors Q _{1 to} Q _n and V _DD 1, and the least significant bit (Least). Significant Bi
The resistance value of the resistor R ₁ (t, hereafter referred to as LSB) is gradually reduced to 1/2 as the maximum value becomes higher-order bits, and becomes the minimum value at the most significant bit (Most Signi-ficant Bit, hereafter referred to as MSB). _{as, R 1: R 2: R} 3: R 4: ...: R n = 1: 1/2: 1/4:
Resistance values having a relationship of 1/8: ...: 1/2 ^n-1 are selected.

Q ₁₀ is one of these MOS transistors Q _{1 to} Q _n.
And a driving PMOS transistor forming a current mirror circuit, the source of which is V _DD 1 via a resistor R ₁₀ .
The drain is short-circuited with the gate and connected to the GND via the constant current source 3.
2 are connected. sw ₁ to SW _n are each MOS transistors Q ₁ to Q _n gates and MOS transistor switch connected between the drain of Q ₁₀ of, are opened and closed in response to the input digital signal. OUT is the output terminal, I ₁ ~I _n, I ₁₀ is the drain current of the MOS transistors Q ₁ ~Q _n, Q _10,
The input digital signal of V _REF is 0 (switches sw _{1 to} sw _n
Is the output voltage value when all are open).

FIG. 6A is a plan view showing the structure and mask pattern of each PMOS transistor, and FIG. 6B is a sectional view, in which D drain, S is a source, G is a gate, and L is a gate. The length and W are the gate width. This MO
If the threshold voltage of the S transistor is V _THO , the drain current is I _D , and the conductance is β, β = K ₁ W / L in the saturation region, and the voltage V _GS between the gate G and the source is expressed by the following equation. Be done. Here, K ₁ and K ₂ are proportional constants.

[Equation 1]

Each of the MOS transistors Q _{1 to} Q _n , Q ₁₀
Have the same gate length L and a different gate width W for each MOS transistor, and their values W _{1 to} W _n , W ₁₀
The _{W 1: W 2: W 3} : W 4: ...: W n = 1: 2: 4: 8: ...:
2 ^n-1 W ₁₀ = W ₁ × R ₁ / R ₁₀ . Thus, the gate widths W _{1 to} W _n and W ₁₀ of the MOS transistors Q _{1 to} Q _n and Q ₁₀ are
Since the drain currents I _{1 to} I _n and I ₁₀ to be supplied are in proportion to each other, if the V _{THO of} each MOS transistor is equal, the voltage V _GS between the gate G and the source is equal in all transistors. .

Next, the operation will be described. If any of the switches sw ₁ to sw _n , for example, the switches sw ₁ and sw ₃ are turned on according to the input digital signal, the MOS transistor Q is turned on via the turned on switches sw ₁ and sw _3.
A voltage drop (I ₁₀ × R ₁₀ ) due to the resistance R ₁₀ of the constant current I ₁₀ supplied to the MOS transistor Q ₁₀ from the constant current source 3 and the gate-source voltage between the gates of ₁ and Q ₃ and V _DD 1. V
_A constant gate voltage (V _G = I ₁₀ ×
R ₁₀ + V _GS ) is applied. Then, the MOS transistor Q ₁₀ , the source resistance R _10, and the MOS transistor Q ₁ ,
Due to the current mirror circuit composed of Q ₃ and source resistors R ₁ and R ₃ , drain currents I ₁ and I ₃ having the values shown in the following equations flow through the MOS transistors Q ₁ and Q ₃ . _{I 1 = (V G -V GS} ) / R 1 = I 10 × R 10 / R 1, I 3 = I 10
× R ₁₀ / R ₃

Since R ₁ = 2 × 2 × R _{3, the} output current I _out is I _out = I ₁ + I ₃ = I ₁₀ × R ₁₀ × (1 / R ₁ + 1 / R ₃ ).
= 5 × I ₁₀ × R ₁₀ / R ₁ . That is, the analog current value of LSB (I ₁ = I ₁₀ × R
An output current of 101 times in terms of ₁₀ / R ₁ ) in binary and 5 times in terms of decimal flows through the output resistor 4, and the output voltage obtained by adding the voltage drop thereof to V _REF is output to the output terminal OUT.

That is, since the source resistances R _{1 to} R _{n of the} MOS transistors Q _{1 to} Q _n have the above relationship, the MOS transistors Q ₁ when the switches sw _{1 to} sw _n are turned on.
Drain current I ₁ ~I _n of to Q _n are _{I 1: I 2: I 3} : I 4: ...: I n = 1: 2: 4: 8: ...: 2 n-1 ... become a relationship (2) , MOS transistors Q corresponding to the switches sw _{1 to} sw _n that are turned on in response to an input digital signal
_The drain currents I _{1 to} I _n flowing through _{1 to} Q _n are added and flow to the output resistor 4, and the analog output voltage corresponding to the input digital signal is taken out from the output terminal OUT.

[0009]

In the conventional current addition type D / A converter as described above, each MOS transistor Q ₁
Drain current I ₁ ~I _n of to Q _n are (1: 2: 4: 8:
..: 2 ^n-1 ), the gate widths W _{1 to} W _n of these MOS transistors are (1: 2: 4: 8: ...: 2).
ⁿ⁻¹ ), and the source resistance values R _{1 to} R _n must be (1: 1/2: 1/4: 1/8: ...: 1/2 ⁿ⁻¹ ). There is a drawback that the layout area occupied by these in a circuit (hereinafter referred to as an IC) becomes large. For example, 7 bit D / A converter, MOS gate width W ₇ of the transistor Q ₇ to 64 times the gate width W ₁ of the MOS transistor Q _1, the resistance value of the source resistance R ₇ a resistance value of the source resistance R ₁ Is 64 times. If the gate voltage V _G is reduced, the source resistance ratio (R ₁ / R _n ) and the gate width ratio (W _n / W ₁ ) of the LSB and the MSB are reduced, but the conversion error becomes larger and the accuracy becomes higher. However, there is a problem in that

The present invention has been made to solve the above-mentioned problems, and it is possible to reduce the conversion accuracy without lowering the conversion accuracy.
It is an object of the present invention to obtain a current addition type D / A conversion circuit which can reduce the layout area in an IC.

[0011]

According to the current addition type D / A conversion circuit of the present invention, a predetermined number of series circuits of a first MOS transistor and a source resistor are connected in parallel between a first potential source and an output terminal. And a predetermined gate voltage is applied between the gate of each of the first MOS transistors and the first potential source via each switch that opens and closes according to an input digital signal, and the output terminal In the current addition type digital-analog conversion circuit for extracting the sum of the switch-on first transistor currents, the first MOS
A series circuit group of a transistor and a source resistor is divided into a plurality of groups, and each group constitutes a first MOS transistor and a current mirror circuit of each group.
A series circuit of a second MOS transistor having a gate and a drain short-circuited and a source resistor is connected between the gate voltage application terminal of the S transistor and the first potential source, and the series circuit of the second MOS transistor of each set is connected. The first and second MOS transistors described above are connected between the drain and the second potential source, and a third MOS transistor having an opposite polarity is connected to form a current mirror circuit with the third MOS transistor of each set. The source is connected to the second potential source, the drain is connected to the first potential source via a constant current source, and has the same polarity as the third MOS transistor, and the gate and the drain are short-circuited. A fourth MOS transistor connected to the gate of the third MOS transistor is provided.

Further, in the above-mentioned configuration, the voltage between the gate and the first potential source of the second MOS transistor of the divided upper bit side is set to the second M of the lower bit side set.
The voltage is set to be higher than the voltage between the gate of the OS transistor and the first potential source.

Further, in the above-mentioned one, the source resistance of each of the divided first MOS transistor and the second MOS transistor and the magnitude of the voltage drop due to the current flowing therethrough are made equal to each other, and The voltage drop of the set on the high-order bit side is set to be larger than the voltage drop of the set on the low-order bit side.

Further, in the above structure, the gate lengths of the first MOS transistor and the second MOS transistor of each of the divided sets are made equal to each other, and the gate length of the set on the upper bit side is It is designed to be shorter than the gate length of the lower bit group.

Furthermore, the first MO of each divided set
The gate-source voltage determined by the gate length, the gate width, and the drain current of the S transistor and the second MOS transistor is made equal for each set, and the gate-source voltage of the set on the upper bit side is set to the set on the lower bit side. It is designed to be higher than the gate-source voltage of.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. 1 is a circuit diagram showing a first embodiment of the present invention, and FIG. 2 is a circuit diagram for explaining the operation thereof.
In FIG. 1, reference numeral 1 is a DC power supply V that constitutes a first potential source.
_DD , 2 are ground points GND that constitute the second potential source, 3 is a constant current source, 4 is output resistance, and Q _{1 to} Q ₇ are D / A having 7 bits.
A PMOS transistor that is a first MOS transistor for conversion, R _{1 to} R ₇ are source resistances of the MOS transistors Q _{1 to} Q ₇ , sw _{1 to} sw ₇ are switches that are opened and closed according to an input digital signal, and OUT is an output. The terminal, V _REF, is the output voltage value when the input digital signal is 0.

Q ₁₁ is a MOS transistor Q ₁ , Q ₂ , Q ₃ of the first set 11 and their switches sw ₁ , sw ₂ , sw _3.
Second MOS that forms a current mirror circuit when the
A PMOS transistor which is a transistor, R ₁₁ is a source resistance of this MOS transistor Q ₁₁ , Q ₁₂ is a MOS transistor Q ₄ , Q ₅ , Q ₆ , Q ₇ of the second set 12 and their switches sw ₄ , sw ₅ , When sw ₆ and sw ₇ are on, a PMOS transistor that is a second MOS transistor forming a current mirror circuit when it is on, R ₁₂ is a source resistance of this MOS transistor Q ₁₂ .

Q ₂₁ is an N-channel MOS transistor (hereinafter referred to as an NMOS transistor) which is a third MOS transistor connected in series between the drain of the PMOS transistor Q ₁₁ and GND 2, and Q ₂₂ is the drain of the PMOS transistor Q ₁₂ . An NMOS transistor Q ₃₀ , which is a third MOS transistor connected in series between GND2, forms a current mirror circuit with these NMOS transistors Q ₂₁ and Q ₂₂ , the gate and drain are short-circuited, and the source is GND2, The drain is connected to V _DD 1 through the constant current source 3, and the gates are connected to the NMOS transistors Q ₂₁ and Q.
It is an NMOS transistor which is a fourth MOS transistor connected to the gates of ₂₂ respectively.

I _{1 to} I ₇ , I ₁₁ , I ₁₂ , and I ₃₀ are drain currents of the MOS transistors Q _{1 to} Q ₇ , Q ₁₁ , Q ₁₂ , and Q ₃₀ , and I ₁ / I ₂ = I ₂ / I _{3 = I 3 / I 4 =} I 4 / I 5 = I 5 / I 6 =
I ₆ / I ₇ = 2 That is, the resistance R is set for each of the groups 11 and 12 so that the formula (2) is obtained.
_{1 to} R ₇ are R ₁ × I ₁ = R ₂ × I ₂ = R ₃ × I ₃ = R ₁₁ × I ₁₁ R ₄ × I ₄ = R ₅ × I ₅ = R ₆ × I ₆ = R ₇ × I ₇ = R ₁₂ x I
₁₂ , that is, R ₁ / R ₂ = R ₂ / R ₃ = 1/2, R ₄ / R ₅ = R ₅ / R ₆ =, so that the voltage drop of the source resistance in each set becomes equal.
The relationship of R ₆ / R ₇ = 1/2 is set. And in this embodiment, R ₁₁ ×
I ₁₁ <R ₁₂ × I ₁₂ , that is, the voltage drop of the source resistance of the first set 11 is set to be smaller than that of the second set 12. Therefore, R ₃ / R ₄ <1/2 is set.

In addition, each set of MOS transistors Q ₁ to
The gate lengths of Q ₇ , Q ₁₁ , and Q ₁₂ are L _{1 to} L ₇ , L ₁₁ , L ₁₂ ,
Assuming that the gate widths are W _{1 to} W ₇ , W ₁₁ , and W ₁₂ , these relationships are L ₁ = L ₂ = L ₃ = L ₁₁ , L ₄ = L ₅ = L ₆ = L ₇ = L ₁₂ , L
₁₁ > L ₁₂ , that is, the gate lengths of the MOS transistors in each set are equal, and the gate length of the first set 11 is set to the second set 12
Set to be longer than that.

Further, each of the MOS transistors Q _{1 to} Q ₇ , which is determined by the ratio of the gate length and the gate width in the equation (1),
Gate-source voltage V of Q ₁₁ , Q ₁₂ , Q ₂₁ , Q ₂₂ , and Q _{30
GS1 ~V GS7, V GS11, V} GS12, V GS21, V GS22, V GS30
The _{V GS1 = V GS2 = V GS3} = V GS11, V GS4 = V GS5 = V GS6 =
V and _{GS7 = V GS12, V GS21 =} V GS22 = V GS30, V GS11 <V GS12, i.e., equal to the gate-source voltage of the MOS transistor constituting the same current source circuit, and the gate of the first set 11 The source-to-source voltage is set to be lower than that of the second set 12. As a result, the gate widths W _{1 to} W ₇ of the respective first MOS transistors Q _{1 to} Q ₇ are W ₁ / W ₂ = W ₂ / W ₃ = 1/2, W as is apparent from the equation (1). ₄ / W ₅ = W ₅ / W ₆ = W
₆ / W ₇ = 1/2. However, it is set so that W ₃ / W ₄ > 1/2.

Next, the operation will be described. Third NMOS
A transistor Q _21, Q ₂₂ and the first 4 NMOS transistor Q ₃₀ of which is a current mirror circuit, the gate and the gate voltage between GND2 of these NMOS transistors, because the source resistance is not connected, between the gate and source each M so that the voltage V _GS21, V _GS22, V _GS30 equal
Drain currents I ₁₁ , I ₁₂ , and I ₃₀ flow through the OS transistor. The drain currents of these MOS transistors Q ₂₁ , Q ₂₂ , and Q ₃₀ have gate lengths L ₂₁ , L ₂₂ , and L ₃₀ and gate widths W ₂₁ , W ₂₂ , and W ₃₀ , respectively, and the threshold voltage V _THO is If both transistors are equal, I ₁₁ = (I ₃₀ × W ₂₁ × L ₃₀ ) / (L ₂₁ × W ₃₀ ), I ₁₂ = (I ₃₀ × W ₂₂ × L ₃₀ ) / (L ₂₂ × W ₃₀ ). These drain currents I ₁₁ and I ₁₂ are the second P
The drain current is supplied to the MOS transistors Q ₁₁ and Q ₁₂ .

Now, according to the input digital signal, the switch s
Any one of w _{1 to} sw ₇ is, for example, a switch sw ₁ , sw ₃ ,
When sw ₅ and sw ₆ is that it has turned on, MOS transistors Q _1, Q ₃ via the switches sw _1, sw ₃ that the on
Between the gate and the V _DD 1 a, the voltage drop due to the resistance R ₁₁ of the drain current I ₁₁ supplied to the MOS transistor Q ₁₁ (I
₁₁ × R ₁₁₎ a constant gate voltage equal to a value obtained by adding the gate-source voltage _{V GS11 (V G11 = I 11} × R 11 + V
_GS11 ) is applied. Then, the MOS transistor Q ₁₁ , the source resistance R _11, and the MOS transistors Q ₁ and Q ₃ ,
Due to the current mirror circuit 11 composed of the source resistors R ₁ and R ₃ , drain currents I ₁ and I ₃ having values shown in the following equations flow through the MOS transistors Q ₁ and Q ₃ . I ₁ = (V _G11 −V _GS11 ) / R ₁ = I ₁₁ × R ₁₁ / R ₁ , I ₃ =
I ₁₁ × R ₁₁ / R ₃

On the other hand, the voltage due to the resistance R ₁₂ of the drain current I ₁₂ supplied to the MOS transistor Q ₁₂ is applied between the gates of the MOS transistors Q ₅ and Q ₆ and V _DD 1 via the switches sw ₅ and sw ₆ which are turned on. A constant gate voltage (V _G12 = I ₁₂ × R ₁₂ + V _GS12 ) equal to the sum of the drop (I ₁₂ × R ₁₂ ) and the gate-source voltage V _GS12 is applied.
Then, the MOS transistor Q ₁₂ , the source resistances R ₁₂ and M
Due to the current mirror circuit 12 composed of the OS transistors Q ₅ and Q ₆ and the source resistors R ₅ and R ₆ , drain currents I ₅ and I ₆ having the values shown in the following equations flow through the MOS transistors Q ₅ and Q _6. . _{I 5 = (V G -V GS12} ) / R 5 = I 12 × R 12 / R 5, I 6 = I
₁₂ x R ₁₂ / R ₆

The output current I _out is then I _out = I ₁ + I ₃ + I ₅ + I ₆ = I ₁₁ × R ₁₁ × (1 / R ₁ + 1 / R ₃ ) + I ₁₂ × R ₁₂ × (1 / R ₅ +1 / R ₆ ) = (1 + 4 + 16 + 32) × I ₁ = 53I ₁ , and this output current I _out flows to the output resistor 4, and the output voltage obtained by adding the voltage drop thereof to V _REF is the output terminal O.
Output to UT. MO Thus, corresponding to the switch sw ₁ to SW ₇ is turned on in response to the input digital signal
Drain current I ₁ ~I ₇ flowing to the S transistor Q ₁ ~Q ₇
Are added and flow to the output resistor 4, and the analog output voltage corresponding to the input digital signal is taken out from the output terminal OUT.

As described above, in this embodiment, the first
Since the MOS transistors Q _{1 to} Q ₇ are divided into two sets and separate current mirror circuits are formed respectively,
It is not necessary to make the gate voltage between the gate of the transistor and V _DD1 equal, and therefore, the voltage drop due to each source resistance, the gate-source voltage of each MOS transistor, the source resistance value and the gate length should be equal only within each group. , The gate width may be adjusted, and the first set 1 on the LSB side
1 and the second set 12 on the MSB side can be adjusted to their own values.

The current addition type D / A converter has a switch sw.
Is turned on, the current flows into the resistor 4, and a voltage value is output to the output OUT. Therefore, the accuracy of the D / A conversion linearity greatly affects the accuracy of the MSB side, which has a large current value. That is, the circuit configuration is such that the error of the current mirror circuit on the MSB side is reduced. An equation representing an error of the current mirror circuit having a resistance on the source side will be described with reference to FIG. In FIG. 2, Q _a is a constant current driving PMOS transistor, Q _b is a PMOS transistor that forms a current mirror circuit with this MOS transistor Q _a , D is a drain, S is a source, G is a gate, and R is a gate.
_S is a source resistance, and both MOS transistors Q _a and Q _b have the same resistance value. I _ref is the drive reference current of the constant current source 3, I _{o ut} is the output current.

Now, the gate-source voltages of the MOS transistors Q _a and Q _b are V _GSa and V _GSb , the conductance is β _a ,
If β _b and the threshold voltages are V _THOa and V _THOb , then V _GSa +
R _S × I _ref = V _GSb + R _S × I _out , therefore V _GSb −V _GSa + R _S (I _out −I _ref ) = 0.

[Equation 2] β _a = β, β _b = β + Δβ, I _ref = I, I _out = I + Δ
I, V _GSa = V _GS , V _THOa = V _THO , V _THOb = V _THO + Δ
If you _say V _THO

(Equation 3) Therefore, the current error in the current mirror circuit with the source resistor connected is

(Equation 4) If Δβ and ΔV _THO are independent elements,

(Equation 5) Becomes

This equation (3) is an equation representing the error of the current mirror circuit. From the equation (3), the larger the voltage value of R _S × I _ref , that is, the voltage applied across the source resistance R _S is |
It can be seen that ΔI _out / I _out | becomes small and the accuracy of the current mirror circuit becomes large. In this embodiment, as described above, R ₁₁ × I ₁₁ <R ₁₂ × I ₁₂ , that is, the voltage drop of the source resistance of the second set 12 on the MSB side is the first on the LSB side.
Since it is set to be larger than that of the set 11 of
The error of the SB side current mirror circuit is reduced. Further, in the first set 11 on the LSB side, the source resistances R _{1 to} R ₃ can be set smaller than before, and if the width of the resistance is constant, the length can be shortened and the area can be reduced accordingly.

Further, the gate lengths L _{4 to} L ₇ of the MOS transistors Q _{4 to} Q ₇ of the second set 12 on the MSB side are the gate lengths of the MOS transistors Q _{1 to} Q ₃ of the first set 11 on the LSB side. Since it is set to be shorter than L _{1 to} L ₃ , (1)
In the formula, the same current I _D flows even when the gate-source voltage V _GS is constant, but the MOS transistors of the second set 12 are more than those when the gate lengths of the first and second sets are equal. it is possible to reduce the gate width W ₄ to _W-7 for Q ₄ to Q _7.

Further, the gate-source voltages V _{GS4 to} V _GS7 of the MOS transistors Q _{4 to} Q ₇ of the second set 12 are the first
Since it is set to be higher than the gate-source voltages V _{GS1 to} V _GS3 of the MOS transistors Q _{1 to} Q ₃ of the set 11 of FIG. 11, the same current I _D flows even if the gate length L is constant in the equation (1). In comparison with the case where the gate-source voltage V _GS is made equal in the first and second groups, the MO of the second group 12 is
It is possible to reduce the gate width _W 4 to _W-7 of S transistor Q ₄ to Q _7.

As described above, the gate length of the MOS transistor of the second set 12 on the MSB side is set to the first set 1 on the LSB side.
Since the gate-source voltage of the MOS transistors of the second set 12 is shorter than that of the first set 11 and is set to be larger than that of the first set 11, the second set 12 is set as described above.
It becomes possible to remarkably reduce the gate width of the MOS transistors Q _{4 to} Q ₇ . Therefore, the gate area on the MSB side, which occupies a large area in the layout of the MOS transistor, can be reduced. And the LSB
Since the gate lengths L _{1 to} L ₃ and the gate widths W _{1 to} W ₃ of the MOS transistors Q _{1 to} Q ₃ of the first set 11 on the side are set to be larger than those in the conventional case, the setting accuracy is increased accordingly and variation is prevented. You can

Embodiment 2 FIG. FIG. 3 is a circuit diagram showing a second embodiment of the present invention. In the figure, 1 is V _DD which constitutes a second potential source, 2 is GND which constitutes a first potential source, and 3
Is a constant current source, 4 is an output resistance, and Q _{1 to} Q ₇ are D with 7 bits.
NMOS which is the first MOS transistor for A / A conversion
The transistors R _{1 to} R ₇ are MOS transistors Q _{1 to} Q _7.
Source resistance, sw _{1 to} sw ₇ are input digital open / close switches, OUT is an output terminal, and V _REF is an input digital signal of 0.
The output voltage value at the time of, Q ₁₁ is the second MOS of the first set 11.
An NMOS transistor which is a transistor, R ₁₁ is a source resistance of this MOS transistor Q ₁₁ , a Q ₁₂ is an NMOS transistor which is a second MOS transistor of the second set 12, and a source resistance of this MOS transistor Q ₁₂ is R ₁₂ .

Q_{twenty one}Is an NMOS transistor Q₁₁Dray of
And V_DDA third MOS transistor connected in series between 1 and 2.
A PMOS transistor, Q_{twenty two}Is an NMOS tiger
Transistor Q₁₂Drain and V_DDConnected in series between 1
Third MOS transistor, PMOS transistor
Ta, Q₃₀Are these PMOS transistors Q_{twenty one}, Q_{twenty two}When
A current mirror circuit is configured and the gate and drain are short-circuited
And the source is V_DD1, the drain is through the constant current source 3
GND2, the gate is a PMOS transistor Q _{twenty one}, Q
_{twenty two}MOS transistor connected to each gate
It is a PMOS transistor that is a star. That is, this fruit
The implementation mode is the polarity of each MOS transistor.
Which is the reverse of that of Embodiment 1._REFIs V
_DDEffective when the value is close to.

I _{1 to} I ₇ , I ₁₁ , I ₁₂ , and I ₃₀ are the drain currents of the MOS transistors Q _{1 to} Q ₇ , Q ₁₁ , Q ₁₂ , and Q ₃₀ , respectively, and the resistors R _{1 to} R ₇ , The relationship with R ₁₁ and R ₁₂ is the same as in Embodiment 1. That is, also in the second embodiment, the voltage drop of the source resistance in each set is the same, and the voltage drop of the source resistance of the first set 11 is equal to the second set 1.
It is set to be smaller than that of 2. And
The gate lengths of the MOS transistors in each set are equal, and the gate length of the first set 11 is set to be longer than that of the second set 12, and the gate-source voltage of the MOS transistors in each set is further set. Are set equal to each other, and the gate-source voltage of the first set 11 is set to be smaller than that of the second set 12. Therefore, the operation and effect are completely the same as those of the embodiment, and the description thereof will be omitted.

Embodiment 3. FIG. 4 is a circuit diagram showing a third embodiment of the present invention. In the figure, 1 is V _DD which constitutes a first potential source, 2 is GND which constitutes a second potential source, and 3
Is a constant current source, 4 is an output resistance, and Q _{1 to} Q ₉ are D with 9 bits.
PMOS which is the first MOS transistor for A / A conversion
Transistors R _{1 to} R ₉ are MOS transistors Q _{1 to} Q ₉
Source resistance, sw _{1 to} sw ₉ are input digital open / close switches, OUT is an output terminal, and V _REF is an input digital signal of 0.
The output voltage value at the time of, Q ₁₁ is the second MOS of the first set 11.
NMOS transistor is a transistor, R ₁₁ is the source resistance of the MOS transistors Q _11, Q ₁₂ are PMOS transistors, R ₁₂ source resistance of the MOS transistor Q ₁₂ is a second MOS transistor of the second set 12, Q ₁₃ Is a PMOS transistor that is the second MOS transistor of the third set 13, R ₁₃ is the source resistance of this MOS transistor Q ₁₃ .

Q ₂₁ is an NMOS transistor which is a third MOS transistor connected in series between the drain of the PMOS transistor Q ₁₁ and V _DD 1, and Q ₂₂ is in series between the drain of the PMOS transistor Q ₁₂ and V _DD 1. NMOS transistor is a third MOS transistor connected, the drain of Q ₂₃ are PMOS transistors Q ₁₃ and V _DD
An NMOS transistor Q ₃₀ , which is a third MOS transistor connected in series between 1 and 1, constitutes a current mirror circuit together with these NMOS transistors Q ₂₁ , Q ₂₂ , and Q _{23. The} gate and drain are short-circuited and the source is For V _DD 1,
The drain is connected to GND2 via the constant current source 3, and the gate is connected to P
An NMOS, which is a fourth MOS transistor connected to the gates of the MOS transistors Q ₂₁ , Q ₂₂ , and Q ₂₃ , respectively.
It is a transistor.

Each of I _{1 to} I ₉ , I ₁₁ , I ₁₂ , I ₁₃ , and I ₃₀ is M.
The drain currents of the OS transistors Q _{1 to} Q ₉ , Q ₁₁ , Q ₁₂ , Q ₁₃ , and Q ₃₀ are: I ₁ / I ₂ = I ₂ / I ₃ = I ₃ / I ₄ = I ₄ / I ₅ = I ₅ / I ₆ =
Resistors R _{1 to} R ₉ are set to R ₁ × I ₁ = R ₂ × I ₂ = R for each set 11 and 12 so that I ₆ / I ₇ = I ₇ / I ₈ = I ₈ / I ₉ = 2. ₃ x I ₃ = R ₁₁ x I ₁₁ R ₄ x I ₄ = R ₅ x I ₅ = R ₆ x I ₆ = R ₁₂ x I ₁₂ R ₇ x I ₇ = R ₈ x I ₈ = R ₉ x I ₉ = R ₁₃ × I ₁₃ , that is, R ₁ / R ₂ = R ₂ / R ₃ = 1/2, R ₄ / R ₅ = R ₅ / R so that the voltage drop of the source resistance in each set becomes equal. ₆ = 1
/ 2, R ₇ / R ₈ = R ₈ / R ₉ = 1/2. And in this embodiment, R ₁₁ ×
I ₁₁ <R ₁₂ × I ₁₂ <R ₁₃ × I ₁₃ , that is, the voltage drop of the source resistance of the LSB side set is set to be smaller than that of the MSB side set.

Further, each set of MOS transistors Q₁~
Q₉, Q₁₁, Q₁₂, Q₁₃The gate length of L ₁~ L₉, L₁₁,
L₁₂, L₁₃, The gate width is W₁~ W₉, W₁₁, W₁₂, W₁₃When
If you do₁= L_Two= L_Three= L₁₁, L_Four= L_Five= L₆= L₁₂, L₇= L₈
= L₉= L₁₃, L₁₁> L₁₂> L₁₃ That is, the gate lengths of the MOS transistors in each set are equal.
The gate length of the pair on the LSB side to the pair on the MSB side.
Set to be longer than that.

Further, each of the MOS transistors Q _{1 to} Q ₉ ,
Gate-source voltages V _{GS1 to} V _GS9 , V _GS11 , V _GS12 , V _GS13 , V of Q ₁₁ , Q ₁₂ , Q ₁₃ , Q ₂₁ , Q ₂₂ , Q ₂₃ , and Q _{30.
GS21, V GS22, V GS23,} V GS30 the _{V GS1 = V GS2 = V GS3} = V GS11, V GS4 = V GS5 = V GS6 =
V _GS12 , V _GS7 = V _GS8 = V _GS9 = V _GS13 , V _GS21 = V
_GS22 = the _{V GS23 = V GS30, V GS11} <V GS12 <V GS13, i.e., equal to the gate-source voltage of the MOS transistor constituting the same current source circuit, and, L
The gate-source voltage of the SB side set is set to be lower than that of the MSB side set. As a result, the gate widths W _{1 to} W ₉ of the first MOS transistors Q _{1 to} Q ₉ are W ₁ / W ₂ = W ₂ / W ₃ = 1/2, W as is clear from the equation (1). ₄ / W ₅ = W ₅ / W ₆ = 1
/ 2, the _{W 7 / W 8 = W 8} / W 9 = 1/2. However, the set _{W 3 / W 4> W 6} / W 7> 1/2 so as.

Next, the operation will be described. Third NMOS
The transistors Q ₂₁ , Q ₂₂ , Q ₂₃ and the fourth NMOS transistor Q ₃₀ form a current mirror circuit,
Gate and the gate voltage between GND2 of these NMOS transistors, because the source resistance is not connected, the gate-source voltage _{V GS21, V GS22, V GS23} , drains each MOS transistor to V _GS30 equals current I _11,
I ₁₂ , I ₁₃ , and I ₃₀ flow. These drain currents are
The gate length of each MOS transistor Q ₂₁ , Q ₂₂ , Q ₂₃ , Q ₃₀ is L ₂₁ , L ₂₂ , L ₂₃ , L ₃₀ , and the gate width is W ₂₁ , W ₂₂ ,
Assuming that W ₂₃ and W ₃₀ and the threshold voltage V _THO is the same for all transistors, I ₁₁ = (I ₃₀ × W ₂₁ × L ₃₀ ) / (L ₂₁ × W ₃₀ ), I ₁₂ = (I ₃₀ × W ₂₂ × L ₃₀ ) / (L ₂₂ × W ₃₀ ) I ₁₃ = (I ₃₀ × W ₂₃ × L ₃₀ ) / (L ₂₃ × W ₃₀ ). These drain currents I ₁₁ , I ₁₂ and I ₁₃ are supplied to the second PMOS transistors Q ₁₁ , Q ₁₂ and Q ₁₃ as drain currents.

Now, according to the input digital signal, the switch s
Any one of w _{1 to} sw ₉ is, for example, a switch sw ₁ , sw ₃ ,
When sw ₅ and sw ₇ is that it has turned on, MOS transistors Q _1, Q ₃ via the switches sw _1, sw ₃ that the on
Between the gate and the V _DD 1 a, the voltage drop due to the resistance R ₁₁ of the drain current I ₁₁ supplied to the MOS transistor Q ₁₁ (I
₁₁ × R ₁₁₎ a constant gate voltage equal to a value obtained by adding the gate-source voltage _{V GS11 (V G11 = I 11} × R 11 + V
_GS11 ) is applied. Then, the MOS transistor Q ₁₁ , the source resistance R _11, and the MOS transistors Q ₁ and Q ₃ ,
Due to the current mirror circuit 11 composed of the source resistors R ₁ and R ₃ , drain currents I ₁ and I ₃ having values shown in the following equations flow through the MOS transistors Q ₁ and Q ₃ . I ₁ = (V _G11 −V _GS11 ) / R ₁ = I ₁₁ × R ₁₁ / R ₁ , I ₃ =
I ₁₁ × R ₁₁ / R ₃

In addition, M is turned on via the switch sw ₅ which is turned on.
Between the gate of the OS transistor Q ₅ and V _DD 1, the resistance R of the drain current I ₁₂ supplied to the MOS transistor Q _12
A constant gate voltage (V) equal to a value obtained by adding the voltage drop (I ₁₂ × R ₁₂ ) due to ₁₂ and the gate-source voltage V _{GS12.
G12 = I 12 × R 12 +} V GS12) is applied. And M
Due to the current mirror circuit 12 including the OS transistor Q ₁₂ , the source resistance R ₁₂ , the MOS transistor Q ₅ , and the source resistance R ₅ , a drain current I ₅ having a value represented by the following equation flows through the MOS transistor Q ₅ . _{I 5 = (V G -V GS12} ) / R 5 = I 12 × R 12 / R 5

Further, a MOS transistor Q ₇ is connected between the gate of the MOS transistor Q ₇ and V _DD 1 via the switch sw ₇ which is turned on.
A constant gate voltage (VG ₁₃ = I ₁₃ ×) which is equal to the sum of the voltage drop (I ₁₃ × R ₁₃ ) of the drain current I ₁₃ supplied to the transistor Q _{13 due} to the resistance R ₁₃ and the gate-source voltage V _GS13. R ₁₃ + V _GS13 ) is applied. Then, the MOS transistor Q ₁₃ , the source resistance R ₁₃ and the MOS
Due to the current mirror circuit 13 composed of the transistor Q ₇ and the source resistance R ₇ , a drain current I ₇ having a value shown in the following equation flows through the MOS transistor Q ₇ . _{I 7 = (V G -V GS13} ) / R 7 = I 13 × R 13 / R 7

Therefore, the output current I _out is I _out = I ₁ + I ₃ + I ₅ + I ₇ = I ₁₁ × R ₁₁ × (1 / R ₁ + 1 / R ₃ ) + I ₁₂ × R ₁₂ × 1 / R ₅ + I ₃ × R ₁₃ / R ₇ = (1 + 4 + 16 + 64) × I ₁ = 85I ₁ , and this output current I _out flows to the output resistor 4, and the output voltage obtained by adding the voltage drop thereof to V _REF is the output terminal O.
Output to UT. In this way, the MO corresponding to the switches sw _{1 to} sw ₉ turned on according to the input digital signal.
Drain current I ₁ ~I ₉ flowing to the S transistor Q ₁ ~Q ₉
Are added and flow to the output resistor 4, and the analog output voltage corresponding to the input digital signal is taken out from the output terminal OUT.

As described above, in this embodiment, the first
Since the MOS transistors Q _{1 to} Q ₉ are divided into three sets and different current mirror circuits are formed respectively,
It is not necessary to make the gate voltage between the gate of the transistor and V _DD1 equal, and therefore, the voltage drop due to each source resistance, the gate-source voltage of each MOS transistor, the source resistance value and the gate length should be equal only within each group. , The gate width may be adjusted, and the first set 1 on the LSB side
It is possible to adjust the first and second sets 12 and the third set 13 on the MSB side to their own values.

Also in this embodiment, as described above, R ₁₁ ×
I ₁₁ <R ₁₂ × I ₁₂ <R ₁₃ × I ₁₃ , that is, the voltage drop of the source resistance of the MSB side set is set to be larger than that of the LSB side set, so that the MSB side current mirror circuit. Error becomes smaller. Further, in the LSB side set, the source resistance can be set smaller than in the conventional case, and if the width of the resistance is constant, the length can be shortened and the area can be reduced accordingly.

Further, since the gate length L of the MOS transistors on the MSB side is set to be shorter than that on the LSB side, the same current I _D flows even when the gate-source voltage V _GS is constant. However, it is possible to reduce the gate width W of the MOS transistors of the group on the MSB side, as compared with the case where the gate lengths L of all the MOS transistors are made equal.

Furthermore, since the gate-source voltage V _GS of the MOS transistors on the MSB side is set to be higher than that on the LSB side, even if the gate length L is constant, the same current I _D flows. , Compared with the case where the gate-source voltage V _GS is made equal in all MOS transistors,
It is possible to reduce the gate width W of the MOS transistors on the SB side.

As described above, the gate length of the MOS transistor on the MSB side is shorter than that on the LSB side, and M
Set the gate-source voltage of the MOS transistor on the SB side to L
Since it is made larger than that on the SB side, the gate width of the MOS transistor on the MSB side can be significantly reduced as described above. Therefore, the gate area on the MSB side, which occupies a large area in the layout of the MOS transistor, can be reduced. And LS
In the MOS transistor on the B side, the gate length L and the gate width W are set to be larger than those in the related art, so that the setting accuracy can be increased and the variation can be prevented.

In the third embodiment, the first and second
Of the MOS transistors Q _{1 to} Q ₉ , Q ₁₁ , Q ₁₂ , and Q ₁₃
As the MOS transistors, the third and fourth MOS transistors Q ₂₁ , Q ₂₂ , Q ₂₃ , and Q ₃₀ are NMOS transistors. However, as in the second embodiment, the first and second MO transistors are used.
The S transistor is an NMOS transistor, and the third and fourth
The MOS transistor may be a PMOS transistor. Also, the case of dividing the aspect 3 of this embodiment the first MOS transistor Q ₁ to Q ₉ in three sets, it is also possible to divide further four or more when the number of input bits is increased.

[0052]

According to the present invention, a predetermined number of series circuits of a first MOS transistor and a source resistance are connected in parallel between the first potential source and the output terminal, and the first MOS transistor and the gate of each first MOS transistor are connected in parallel. A predetermined gate voltage is applied to the first potential source via each switch that opens and closes according to an input digital signal, and the sum of the switch-on first transistor currents is taken out from the output terminal. In the current addition type digital-analog conversion circuit described above, the series circuit group of the first MOS transistor and the source resistance is divided into a plurality of groups, and each group has a first MOS transistor and a current mirror circuit of each group. Make up these first
Second MOS transistor whose gate and drain are short-circuited between the gate voltage application terminal of the MOS transistor and the first potential source
A series circuit of a transistor and a source resistance is connected, and a third MOS transistor having a polarity opposite to that of each of the first and second MOS transistors between the drain and the second potential source of the second MOS transistor of each set. To form a current mirror circuit with the third MOS transistor of each set, the source having the same polarity as the third MOS transistor, the source being the second potential source, and the drain being the constant current source. Since the fourth MOS transistor connected to the first potential source and having the gate and the drain short-circuited and connected to the gates of the third MOS transistors in the entire set is provided, the voltage drop due to each source resistance, The gate-source voltage of each MOS transistor can be adjusted independently by the current mirror circuit of the LSB side and the current mirror circuit of the MSB side. Whereby the source resistance, the gate length, by adjusting the gate width and the like to each own value,
There is an effect that the accuracy is high and the pattern layout area can be reduced.

Further, in the above-mentioned device, the voltage between the gate of the MOS transistor of the divided upper bit side (MSB side) and the first potential source is set to the lower bit side (LSB).
Since it is set to be larger than that of the (2) side), the error of the current mirror circuit on the MSB side, in which the precision of the variation is largely involved, is reduced, and the precision is increased accordingly.

Further, in the above-mentioned one, the source resistance of each of the divided first MOS transistor and the second MOS transistor and the magnitude of the voltage drop due to the current flowing therethrough are made equal to each other, and Since the voltage drop of the MSB side set is made larger than that of the LSB side set, the accuracy of the MSB side current mirror circuit is increased and the source resistance value of the LSB side MOS transistor is set small. If the width of the resistor is constant, the length can be shortened, and the pattern layout area can be reduced accordingly.

Further, in the above-mentioned one, the gate lengths of the first MOS transistor and the second MOS transistor of each divided set are made equal to each other, and
Since the gate length of the group on the B side is set to be shorter than the gate length of the group on the LSB side, in the MOS transistor on the MSB side, it is possible to reduce the gate width to allow the same drain current to flow. The layout area becomes smaller, and in the MOS transistor of the LSB side, the gate length can be set longer than before, and the gate width can be set large to allow the same drain current to flow. There is an effect that can be.

Furthermore, the first MO of each divided set
The gate-source voltage of the S transistor and the second MOS transistor is made equal for each group, and the gate-source voltage of the group on the MSB side is set to be higher than the gate-source voltage of the group on the LSB side. Therefore, the gate width of the MOS transistor on the MSB side is narrower than the conventional one, and
Since it can be set wide on the B side, the pattern layout area can be reduced in the MOS transistor on the MSB side that occupies a large pattern layout area, and the MOS transistor on the LSB side can be reduced.
The transistor has the effect of increasing the setting accuracy and preventing variations.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram for explaining the operation of the first embodiment.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing a third embodiment of the present invention.

FIG. 5 is a circuit diagram showing an example of a conventional current addition type D / A converter.

FIG. 6A is a plan view showing a configuration and a mask pattern of a PMOS transistor. (B) is a sectional view thereof.

[Explanation of symbols]

1 DC power supply (first and second potential sources), 2 ground point (second and first potential sources), 3 constant current source, 4 output resistance, 1
1 1st set, 12 2nd set, 13 3rd set, Q ₁
To Q ₉ first MOS transistor, Q ₁₁ , Q ₁₂ , Q ₁₃
Second MOS transistor, Q ₂₁ , Q ₂₂ , Q ₂₃ Third
MOS transistor, Q ₃₀ fourth MOS transistor, R _{1 to} R ₉ , R ₁₁ , R ₁₂ , R ₁₃ source resistance, sw ₁
~ Sw ₉ switch, OUT output terminal.

Claims (5)

[Claims] 1. A first M is provided between the first potential source and the output terminal.
A predetermined number of series circuits of an OS transistor and a source resistor are connected in parallel, and a switch that opens and closes according to an input digital signal is provided between the gate of each of the first MOS transistors and the first potential source. In the current addition type digital-analog conversion circuit, in which a predetermined gate voltage is applied to extract the sum of the switch-on first transistor currents from the output terminal, the first MOS transistor and the source resistance are connected in series. The circuit group is divided into a plurality of groups, and each group forms a current mirror circuit with each first MOS transistor of each group, and between the gate voltage application terminal of these first MOS transistors and the first potential source. Is connected to a series circuit of a source resistance and a second MOS transistor whose gate and drain are short-circuited, and the second MOS transistor of each set is connected. Drain and said respective first between the second potential source of register, a third MOS transistor of the second MOS transistor and the opposite polarity connected, the third of these each set
MOS transistor and current mirror circuit,
The same polarity as those of the third MOS transistor, the source is connected to the second potential source, the drain is connected to the first potential source via a constant current source, and the gate and the drain are short-circuited to form the whole set. A current addition type digital-analog conversion circuit characterized in that a fourth MOS transistor connected to the gate of the third MOS transistor is provided. 2. The second M of the divided upper bit side set
The voltage between the gate of the OS transistor and the first potential source is
2. The current addition type digital-analog conversion circuit according to claim 1, wherein the voltage is higher than the voltage between the gate and the first potential source of the second MOS transistor of the set on the lower bit side. 3. The source resistance of each of the divided first and second MOS transistors and the magnitude of the voltage drop due to the current flowing through the first and second MOS transistors are made equal to each other, and the upper bit side is set. 2. The current addition type digital-analog conversion circuit according to claim 1, wherein the voltage drop of the above is set to be larger than the voltage drop of the set on the lower bit side. 4. The gate lengths of the first MOS transistor and the second MOS transistor of each divided set are made equal to each other, and the gate length of the set on the upper bit side is set to the set on the lower bit side. 2. The current adding type digital-analog conversion circuit according to claim 1, wherein the gate length is shorter than the gate length. 5. The gate-source voltage determined by the gate length, the gate width and the drain current of each of the divided first MOS transistor and second MOS transistor is equalized for each group, and the upper bit side 2. The current addition type digital-analog conversion circuit according to claim 1, wherein the gate-source voltage of the group is set to be higher than the gate-source voltage of the group on the lower bit side.