JPH02202227A - D-a converter - Google Patents
D-a converterInfo
- Publication number
- JPH02202227A JPH02202227A JP2134189A JP2134189A JPH02202227A JP H02202227 A JPH02202227 A JP H02202227A JP 2134189 A JP2134189 A JP 2134189A JP 2134189 A JP2134189 A JP 2134189A JP H02202227 A JPH02202227 A JP H02202227A
- Authority
- JP
- Japan
- Prior art keywords
- resistance
- converter
- section
- normally closed
- resistance value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 6
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Landscapes
- Analogue/Digital Conversion (AREA)
Abstract
Description
【発明の詳細な説明】
［概要］
Ｒ−２Ｒはしご形抵抗回路を用いたＤ−Ａ変換器に関し
、
多数ビットのデジタル信号をアナログ信号に変換するの
に適したＲ−２Ｒはしご形抵抗回路を用いたＤ−Ａ変換
器を提供することことを目的とし、Ｒ−２Ｒはしご形抵
抗回路の２Ｒ抵抗部に、入力デジタル信号に応じて切換
えられる切換スイッチが直列に挿入されたＤ−Ａ変換器
において、前記Ｒ−２Ｒはしご形抵抗回路のＲ抵抗部に
、抵抗値補正用の常閉スイッチが直列に挿入され、前記
２Ｒ抵抗部の抵抗の抵抗値と前記切換スイッチの抵抗値
の合計値が、前記Ｒ抵抗部の抵抗の抵抗値と前記常閉ス
イッチの抵抗値の合計値のほぼ２倍であるように構成す
る。[Detailed Description of the Invention] [Summary] Regarding a D-A converter using an R-2R ladder resistor circuit, the present invention relates to a D-A converter using an R-2R ladder resistor circuit suitable for converting a multi-bit digital signal into an analog signal. A D-A converter in which a changeover switch that is switched according to an input digital signal is inserted in series in the 2R resistance section of an R-2R ladder resistance circuit. In this case, a normally closed switch for resistance value correction is inserted in series with the R resistance part of the R-2R ladder type resistance circuit, and the total value of the resistance value of the resistor of the 2R resistance part and the resistance value of the changeover switch is , the resistance value of the resistor of the R resistance section and the resistance value of the normally closed switch are approximately twice the sum of the resistance values.
［産業上の利用分野］
本発明はＲ−２Ｒはしご形抵抗回路を用いたＤ−Ａ変換
器に関する。[Industrial Application Field] The present invention relates to a DA converter using an R-2R ladder resistance circuit.
［従来の技術］
従来のＲ−２Ｒはしご形抵抗回路を用いたＤ−Ａ変換器
の一例を第６図に示す。[Prior Art] FIG. 6 shows an example of a DA converter using a conventional R-2R ladder resistance circuit.
入力電圧■、Ｎは、Ｒ−２Ｒはしご形抵抗回路の初段の
Ｒ抵抗部と２Ｒ抵抗部の接続点に入力される。Ｒ−２Ｒ
はしご形抵抗回路の各２Ｒ抵抗部には、変換されるべき
デジタル信号のビット信号８１〜Ｂｎに応じて切換えら
れる切換スイッチＳＷ１〜ＳＷｎが直列に挿入されてい
る。切換スイッチＳＷ１〜Ｓ Ｗ ｎは、ビット信号８
１〜Ｂｎに応じて、各２Ｒ抵抗部の抵抗２Ｒをオペアン
プＯＰの正入力端に接続するか負入力端に接続するかを
切換えるものである。すなわち、切換スイッチＳＷ１〜
ＳＷｎの端子ｔ ａ １〜ｔ ａ ｎは各抵抗２Ｒに接
続され、端子ｔｂｌ〜ｔｂｎは共通接続されて接地され
ると共にオペアンプＯＰの正入力端に接続され、端子ｔ
ｃｌ〜ｔｃｎは共通接続されてオペアンプｏＰの負入力
端に接続されている。Ｒ−２Ｒはしご形抵抗回路の最終
段の２Ｒ抵抗部は常閉スイッチＳＷｎ＋１を介して接地
されると共にオペアンプＯＰの正入力端に接続されてい
る。オペアンプＯＰの負入力端と出力端間には抵抗Ｒが
挿入されている。アナログ変換された出力電圧Ｖ０１Ｊ
ＴはオペアンプＯＰから出力される。The input voltages (1) and N are input to the connection point between the first-stage R resistance section and the 2R resistance section of the R-2R ladder resistance circuit. R-2R
Changeover switches SW1 to SWn, which are switched according to bit signals 81 to Bn of the digital signal to be converted, are inserted in series in each 2R resistance section of the ladder type resistance circuit. Changeover switches SW1 to SWn are bit signals 8
1 to Bn, it is switched whether the resistor 2R of each 2R resistance section is connected to the positive input terminal or the negative input terminal of the operational amplifier OP. That is, selector switch SW1~
The terminals t a 1 to t a n of SWn are connected to each resistor 2R, and the terminals tbl to tbn are commonly connected and grounded, and are also connected to the positive input terminal of the operational amplifier OP, and the terminal t
cl to tcn are commonly connected and connected to the negative input terminal of the operational amplifier oP. The final stage 2R resistance section of the R-2R ladder resistance circuit is grounded via a normally closed switch SWn+1 and connected to the positive input terminal of the operational amplifier OP. A resistor R is inserted between the negative input terminal and the output terminal of the operational amplifier OP. Analog converted output voltage V01J
T is output from the operational amplifier OP.
アナログ信号に変換されるべきデジタル信号の各ビット
に応じて切換スイッチＳＷＩ〜Ｓ Ｗ ｎ 全切換える
０例えば、デジタル信号が「１１１・・・１」であれば
、切換スイッチＳＷＩ、ＳＷ２、ＳＷ３、・・・、Ｓ
Ｗ ｎの端子ｔａｌ、ｔａ２、ｔ ａ ３、−・ｔａｎ
が端子ｔｃｌ 〜ｔｃ２、ｔｃ３、−・−ｔｃｎに接続
されるように切換える。このようにすることによりオペ
アンプＯＰからデジタル信号に応じたアナログ信号■。Depending on each bit of the digital signal to be converted into an analog signal, the changeover switches SWI to SW n all switch to 0. For example, if the digital signal is "111...1", the changeover switches SWI, SW2, SW3, . ..., S
W n terminals tal, ta2, ta 3, -・tan
are connected to terminals tcl to tc2, tc3, ---tcn. By doing this, an analog signal (■) corresponding to the digital signal from the operational amplifier OP is generated.
υ↑が出力端から出力される。υ↑ is output from the output terminal.
Ｒ−２Ｒはしご形抵抗回路を用いた従来のＤ−Ａ変換器
の他の例を第７図に示す、この例では切換スイッチＳ
Ｗ １〜Ｓ Ｗ ｎの端子ｔｂ１〜ｔｂｎは接地され、
端子ｔｅｌ〜ｔｃｎは入力電圧■、が入力する入力端に
接続されている。オペアンプＯＰの正入力端は接地され
、負入力端はＲ−２Ｒはしご形抵抗回路の最終段のＲ抵
抗部に接続されている。オペアンプＯＰの負入力端と出
力端間には抵抗ＲＦが挿入されている。Another example of a conventional D-A converter using an R-2R ladder resistance circuit is shown in FIG.
Terminals tb1 to tbn of W1 to SWn are grounded,
The terminals tel to tcn are connected to an input terminal to which an input voltage . The positive input terminal of the operational amplifier OP is grounded, and the negative input terminal is connected to the final stage R resistance section of the R-2R ladder resistance circuit. A resistor RF is inserted between the negative input terminal and output terminal of the operational amplifier OP.
このＤ−Ａ変換器においても、アナログ信号に変換され
るべきデジタル信号の各ビットに応じて切換スイッチＳ
ＷＩ〜Ｓ Ｗ ｎを切換えると、オペアンプＯＰからデ
ジタル信号に応じたアナログ信号Ｖ。ＬＩＴが出力端か
ら出力される。In this D-A converter as well, the changeover switch S is set according to each bit of the digital signal to be converted into an analog signal.
When WI to S W n are switched, an analog signal V corresponding to the digital signal from the operational amplifier OP is generated. LIT is output from the output end.
［発明が解決しようとする課題］
しかしながら、これら従来のＤ−Ａ変換器の場合、ビッ
ト数が多くなると製造が困難になるという問題があった
。[Problems to be Solved by the Invention] However, in the case of these conventional D-A converters, there is a problem in that as the number of bits increases, manufacturing becomes difficult.
例えば第６図のＤ−Ａ変換器の場合で説明すると、デジ
タル信号が正しくアナログ信号に変換されるためには、
Ｒ−２Ｒはしご形抵抗回路として正しく動作しなければ
ならないが、そのためには、各２Ｒ抵抗部の抵抗２Ｒの
端子、すなわち、各切換スイッチＳＷ１〜ＳＷｎの端子
ｔａ１〜ｔａｎの電位が一定でなければならない、今、
入力端子■、から電流ｌが流れ込んだとすると、第１段
のＲ抵抗部及び２Ｒ抵抗部にはそれぞれ電流ｉ ／ ２
が流れ、第２段のＲ抵抗部及び２Ｒ抵抗部にはそれぞれ
電流ｉ／２２が流れ、第３段のＲ抵抗部及び２Ｒ抵抗部
にはそれぞれ電流ｉ／２３が流れ、・・・、第ｎ段のＲ
抵抗部及び２Ｒ抵抗部にはそれぞれ電流ｌ／２１が流れ
る。各切換スイッチＳＷＩ〜Ｓ Ｗ ｎの端子ｔａｌ〜
ｊａｎの電位を一定にするために、切換スイッチＳＷＩ
〜Ｓ Ｗ ｎの端子間の抵抗の比を調節する。すなわち
、切換スイッチＳＷ１〜ＳＷｎの抵抗をｒ １〜ｒ ｎ
とすると、ｒ Ｉ Ｘ ｉ ／ ２ ＝ ｒ ２ Ｘ
ｉ ／ ２２＝ ｒ ３ Ｘ ｉ ／ ２ ’
＝ ｒ ｎ Ｘ ｉ ／ ２ ”
なる式が成立するように抵抗ｒ１〜ｒｎの比を次のごと
く調節しなければならなかった。For example, in the case of the D-A converter shown in Figure 6, in order for a digital signal to be correctly converted into an analog signal,
The R-2R ladder resistance circuit must operate correctly, but in order to do so, the potentials of the terminals of the resistor 2R in each 2R resistance section, that is, the terminals ta1 to tan of the changeover switches SW1 to SWn, must be constant. Not now,
Assuming that a current l flows into the input terminal ■, the current i/2 flows into the R resistance section and the 2R resistance section of the first stage, respectively.
flows, current i/22 flows through the R resistance section and 2R resistance section of the second stage, current i/23 flows through the R resistance section and 2R resistance section of the third stage, and so on. n stage R
A current 1/21 flows through each of the resistance section and the 2R resistance section. Terminal tal of each changeover switch SWI~SWn
In order to keep the potential of jan constant, selector switch SWI
~Adjust the ratio of resistances between the terminals of S W n. That is, the resistances of the changeover switches SW1 to SWn are r1 to rn
Then, r I X i / 2 = r 2
The ratio of the resistors r1 to rn had to be adjusted as follows so that the following formula holds: i/22=r3Xi/2'=rnXi/2''.
ｒｌ：ｒ２：ｒ３： ・・・： ｒｎ
＝１：２：２２ ： ・・・＝２１１−１このようにＲ
−２Ｒはしご形抵抗回路として正しく動作させるために
は、切換スイッチＳＷＩ〜ＳＷｎの抵抗ｒ１〜ｒｎを後
段になるほど２の指数倍で増加させなければならない、
このためＤ−Ａ変換器のビット数が多くなると後段の切
換スイッチの抵抗が極めて大きくなるという問題があっ
た０例えば１６ビツトのＤ−Ａ変換器の場合、スイッチ
５Ｗ１６の抵抗ｒ１６は、スイッチＳＷＩの抵抗ｒ１の
２”（＝３２７６８倍）にもなってしまう、特にＤ−Ａ
変換器を半導体装置として構成する場合、後段の切換ス
イッチに必要な面積が非常に大きくなってしまい、実現
不可能になるという問題があった。rl:r2:r3: ...: rn =1:2:22: ...=211-1 Like this R
- In order to operate correctly as a 2R ladder resistance circuit, the resistances r1 to rn of the changeover switches SWI to SWn must be increased by an exponential factor of 2 toward the later stages.
For this reason, as the number of bits in the D-A converter increases, there is a problem that the resistance of the changeover switch in the subsequent stage becomes extremely large.For example, in the case of a 16-bit D-A converter, the resistor r16 of switch 5W16 is The resistance r1 becomes 2" (=32768 times), especially for D-A.
When the converter is configured as a semiconductor device, there is a problem in that the area required for the subsequent changeover switch becomes extremely large, making it impossible to implement.
本発明は上記事情を考慮してなされたもので、多数ビッ
トのデジタル信号をアナログ信号に変換するのに適した
Ｒ−２Ｒはしご形抵抗回路を用いたＤ−Ａ変換器を提供
することを目的とする。The present invention has been made in consideration of the above circumstances, and an object of the present invention is to provide a D-A converter using an R-2R ladder resistor circuit suitable for converting a multi-bit digital signal into an analog signal. shall be.
［課題を解決するための手段］
上記目的は、Ｒ−２Ｒはしご形抵抗回路の２Ｒ抵抗部に
、入力デジタル信号に応じて切換えられる切換スイッチ
が直列に挿入されたＤ−Ａ変換器において、前記Ｒ−２
Ｒはしご形抵抗回路のＲ抵抗部に、抵抗値補正用の常閉
スイッチが直列に挿入され、前記２Ｒ抵抗部の抵抗の抵
抗値と前記切換スイッチの抵抗値の合計値が、前記Ｒ抵
抗部の抵抗の抵抗値と前記常閉スイッチの抵抗値の合計
値のほぼ２倍であることを特徴とするＤ−Ａ変換器によ
って達成される。[Means for Solving the Problem] The above object is to provide a D-A converter in which a changeover switch that is switched in accordance with an input digital signal is inserted in series in the 2R resistance section of the R-2R ladder resistance circuit. R-2
A normally closed switch for resistance value correction is inserted in series with the R resistance part of the R ladder type resistance circuit, and the sum of the resistance value of the resistor of the 2R resistance part and the resistance value of the changeover switch is the sum of the resistance values of the resistance of the 2R resistance part and the resistance value of the changeover switch. This is achieved by a D-A converter characterized in that the resistance value is approximately twice the sum of the resistance value of the resistor and the resistance value of the normally closed switch.
［作用］
本発明によれば、Ｒ−２Ｒはしこ形抵抗回路のＲ抵抗部
に、抵抗値補正用の常閉スイッチを直列に挿入し、２Ｒ
抵抗部の抵抗の抵抗値と切換スイッチの抵抗値の合計値
が、Ｒ抵抗部の抵抗の抵抗値と常閉スイッチの抵抗値の
合計値のほぼ２倍であるようにしているので、切換スイ
ッチや常閉スイッチも含めて抵抗値がＲ−２Ｒはしご形
抵抗回路として構成している。[Function] According to the present invention, a normally closed switch for resistance value correction is inserted in series with the R resistance part of the R-2R wedge-shaped resistance circuit, and the 2R
The total value of the resistance value of the resistor in the resistor section and the resistance value of the changeover switch is approximately twice the total value of the resistance value of the resistor in the R resistance section and the resistance value of the normally closed switch, so the changeover switch It is constructed as a ladder-type resistance circuit with a resistance value of R-2R, including the normally closed switch.
［実施例］
本発明の第１の実施例によるＤ−Ａ変換器を第１図に示
す０本実施例は第６図に示す従来のＤ−Ａ変換器に本発
明を適用したものである。第６図に示す従来のＤ−Ａ変
換器と同一の構成要素には同一の符号を付して説明を省
略又は簡略にする。[Embodiment] A D-A converter according to a first embodiment of the present invention is shown in FIG. 1. This embodiment is an application of the present invention to a conventional D-A converter shown in FIG. . Components that are the same as those of the conventional DA converter shown in FIG. 6 are denoted by the same reference numerals, and description thereof will be omitted or simplified.
本実施例ではＲ−２Ｒはしご形抵抗回路の各Ｒ抵抗部に
抵抗値補正用の常閉スイッチ５ＷＣ１〜５ＷＣｎを設け
る。そして、２Ｒ抵抗部の切換スイッチＳＷＩ〜Ｓ Ｗ
ｎまで含めた抵抗値が、Ｒ抵抗部の常閉スイッチ５Ｗ
Ｃ１〜５ＷＣｎまで含めた抵抗値の２倍になるようにす
る。In this embodiment, normally closed switches 5WC1 to 5WCn for resistance value correction are provided in each R resistance section of the R-2R ladder resistance circuit. Then, selector switches SWI to S W of the 2R resistance section
The resistance value including up to n is the normally closed switch 5W of the R resistance part.
Make it twice the resistance value including C1 to 5WCn.
常閉スイッチ５ＷＣ１〜５ＷＣｎの抵抗値をｒ、切換ス
イッチＳＷ１〜Ｓ Ｗ ｎ及び常閉スイッチＳＷｎ＋１
の抵抗値を２ｒにすると、２Ｒ抵抗部の全抵抗１ｉ２Ｒ
＋２ｒがＲ抵抗部の全抵抗値Ｒ７ｔ−ｒの２倍になり、
スイッチまで含めて考えればＲ−２Ｒはしご形抵抗回路
として正しく構成される。The resistance value of the normally closed switches 5WC1 to 5WCn is r, the changeover switches SW1 to SWn and the normally closed switch SWn+1
If the resistance value of is set to 2r, the total resistance of the 2R resistance part is 1i2R
+2r is twice the total resistance value R7t-r of the R resistance section,
If the switch is included, it is correctly configured as an R-2R ladder resistance circuit.
また、オペアンプＯＰの負入力端と正入力端間に挿入さ
れた抵抗Ｒにも抵抗値補正用の抵抗ｒの常閉スイッチＳ
ＷＣを直列に挿入する。In addition, a normally closed switch S of a resistor r for resistance value correction is also connected to the resistor R inserted between the negative input terminal and the positive input terminal of the operational amplifier OP.
Insert WC in series.
このように本実施例によれば、ビット数が増えてもビッ
ト数に比例してＤ−Ａ変換器が太き（なるだけであるの
で、多ビツト用のＤ−Ａ変換器でも容易に実現できる。In this way, according to this embodiment, even if the number of bits increases, the D-A converter becomes thicker in proportion to the number of bits, so it can be easily realized even in a multi-bit D-A converter. can.
本実施例の具体例を第２図に示す、この具体例では第３
図に示すようにＰＭＯＳＦＥＴとＮＭＯ３ＦＥＴを並列
接続したトランスファーゲートによりスイッチを構成し
ている。A specific example of this embodiment is shown in FIG.
As shown in the figure, the switch is configured by a transfer gate in which a PMOSFET and an NMO3FET are connected in parallel.
２Ｒ抵抗部の切換スイッチＳＷＩ〜ＳＷｎは、ＰＭＯＳ
ＦＥＴとＮＭＯ３ＦＥＴが並列接続されたト・ランスフ
ァーゲートＧ Ｔ １ ａ〜ＧＴｎａ、ＧＴｌｂ〜ＧＴ
ｎｂで構成される。トランスファーゲートＧＴ１ａ〜Ｇ
Ｔｎａは、オペアンプｏｐの正入力端に接続され、トラ
ンスファーゲートＧＴ１ｂ〜ＧＴｎｂは、オペアンプｏ
Ｐの負入力端に接続される。入力デジタル信号のビット
信号８１〜Ｂｎは、トランスファーゲートＧＴ１ａ〜Ｇ
ＴｎａのＰＭｏＳＦＥＴのゲートとトランスファーゲー
トＧＴ１ｂ〜ＧＴｎｂのＮＭＯ３ＦＥＴのゲートには、
直接入力され、トランスファーゲートＧＴ１ａ〜ＧＴｎ
ａのＮＭＯ３ＦＦ、Ｔのゲートとトランス７ｙ−ゲート
ＧＴ１ｂ 〜ＧＴｎｂのＰＭｏＳＦＥＴのゲートには、
インバータＩＮＩ〜ＩＮｎにより反転されて入力される
。The changeover switches SWI to SWn of the 2R resistance section are PMOS
Transfer gates GT1a~GTna, GTlb~GT in which FET and NMO3FET are connected in parallel
Consists of nb. Transfer gate GT1a~G
Tna is connected to the positive input terminal of operational amplifier op, and transfer gates GT1b to GTnb are connected to operational amplifier o
Connected to the negative input terminal of P. Bit signals 81 to Bn of the input digital signal are transferred to transfer gates GT1a to G
At the gate of PMoSFET of Tna and the gate of NMO3FET of transfer gates GT1b to GTnb,
directly input to transfer gates GT1a to GTn
NMO3FF of a, gate of T and gate of PMoSFET of transformer 7y-gate GT1b ~ GTnb,
The signal is inverted by inverters INI to INn and inputted.
ビット信号Ｂ１〜ＢｎがＶｅｅであると、トランスファ
ーゲートＧＴ １ ａ〜ＧＴ ｎ ａのＰＭｏＳＦＥＴ
とＮＭＯ３ＦＥＴは共にオフで、トランスファーゲート
ＧＴ１ｂ〜ＧＴｎｂのＰＭｏＳＦＥＴとＮＭＯ３ＦＥＴ
は共にオンとなり、２Ｒ抵抗部がオペアンプＯＰの負入
力端に接続される。逆に、と、ット信号Ｂ１〜ＢｎがＶ
ｃｃであると、トランスファーゲートＧＴ１ａ〜ＧＴｎ
ａのＰＭｏＳＦＥＴとＮＭＯ３ＦＥＴは共にオンで、ト
ランスファーゲートＧＴ１ｂ〜ＧＴｎｂのＰＭＯ３ＦＦ
、ＴとＮＭＯ３ＦＥＴは共にオフとなり、２Ｒ抵抗部が
オペアンプＯＰの正入力端に接続される。When the bit signals B1 to Bn are Vee, the PMoSFETs of the transfer gates GT 1 a to GT na
and NMO3FET are both off, and PMoSFET and NMO3FET of transfer gates GT1b to GTnb are off.
are both turned on, and the 2R resistance section is connected to the negative input terminal of the operational amplifier OP. Conversely, the cut signals B1 to Bn are V
cc, transfer gates GT1a to GTn
PMoSFET and NMO3FET of a are both on, and PMO3FF of transfer gates GT1b to GTnb
, T and NMO3FET are both turned off, and the 2R resistance section is connected to the positive input terminal of the operational amplifier OP.
Ｒ抵抗部の常閉スイッチ５ＷＣＩ〜５ＷＣｎと、最終段
の２Ｒ抵抗部の常閉スイッチＳＷｎ÷１と、オペアンプ
ＯＰの負入力端と正入力端間の常閉スイッチＳＷＣもＰ
ＭｏＳＦＥＴとＮＭＯ３ＦＥＴが並列接続されたトラン
スファーゲートＧＴ１ｃ〜ＧＴｎｃにより構成される。The normally closed switches 5WCI to 5WCn in the R resistance section, the normally closed switch SWn÷1 in the 2R resistance section in the final stage, and the normally closed switch SWC between the negative input terminal and positive input terminal of the operational amplifier OP are also connected to P.
It is composed of transfer gates GT1c to GTnc in which MoSFET and NMO3FET are connected in parallel.
ＰＭｏＳＦＥＴのゲートにはＶｅｅが、ＮＭＯ８ＦＥＴ
のゲートにはＶｃｃが入力されて常に閉じている。Vee is on the gate of PMoSFET, NMO8FET
Vcc is input to the gate and it is always closed.
トランスファーゲートを構成するＰＭｏＳＦＥＴとＮＭ
Ｏ３ＦＥＴの面積を調整することにより、２Ｒ抵抗部の
切換スイッチＳＷＩ〜Ｓ Ｗ ｎのオン抵抗を常閉スイ
ッチ５ＷＣ１〜５ＷＣｎ、ＳＷＣのオン抵抗の２倍にな
るようにする。PMoSFET and NM that make up the transfer gate
By adjusting the area of the O3FET, the on-resistance of the changeover switches SWI to SWn of the 2R resistance section is made to be twice the on-resistance of the normally closed switches 5WC1 to 5WCn and SWC.
このようにスイッチにトランスファーゲートを用いても
本実施例のようにオン抵抗を大きくする必要がないので
、寄生容量を小さく構成でき、リンギングが小さくセト
リングタイムが短くできる。Even if a transfer gate is used as a switch in this way, there is no need to increase the on-resistance as in this embodiment, so the parasitic capacitance can be configured to be small, ringing is small, and settling time can be shortened.
また、スイッチにＰＭｏＳＦＥＴとＮＭＯ３ＦＥＴを並
列接続したトランスファーゲートを用いなので、第３図
に示すようにゲートへの入力電圧によるオン抵抗の変動
が少なく精度のよいＤ−Ａ変換が行える。Further, since a transfer gate in which a PMoSFET and an NMO3FET are connected in parallel is used as a switch, as shown in FIG. 3, there is little variation in on-resistance due to the input voltage to the gate, and highly accurate D-A conversion can be performed.
本発明の第２の実施例によるＤ−Ａ変換器を第４図に示
す。本実施例は第７図に示す従来のＤ−Ａ変換器に本発
明を適用したものである。第７図に示す従来のＤ−Ａ変
換器及び第１図に示す第１の実施例のＤ−Ａ変換器と同
一の構成要素には同一の符号を付して説明を省略又は簡
略にする。A DA converter according to a second embodiment of the present invention is shown in FIG. In this embodiment, the present invention is applied to the conventional DA converter shown in FIG. Components that are the same as those of the conventional D-A converter shown in FIG. 7 and the D-A converter of the first embodiment shown in FIG. .
本実施例のＤ−Ａ変換器のＲ−２Ｒはしご形抵抗回路は
第１の実°施例のＲ−２Ｒはしこ形抵抗回路と同様に、
各Ｒ抵抗部に抵抗値補正用の常閉スイッチ５ＷＣ１〜５
ＷＣｎを設けると共に、第１段の前に設けられた２Ｒ抵
抗部にも常閉スイッチＳＷＯを設け、２Ｒ抵抗部の切換
スイッチＳＷＩ〜Ｓ Ｗ ｎまで含めた抵抗値が、Ｒ抵
抗部の常閉スイッチ５ＷＣＩ〜５ＷＣｎまで含めた抵抗
値の２倍になるようにする。The R-2R ladder resistance circuit of the DA converter of this embodiment is similar to the R-2R ladder resistance circuit of the first embodiment.
Normally closed switch 5WC1-5 for resistance value correction in each R resistance part
WCn is provided, and a normally closed switch SWO is also provided in the 2R resistor section provided before the first stage, so that the resistance value including the changeover switches SWI to S Wn of the 2R resistor section is equal to the normally closed switch of the R resistor section. The resistance value should be twice the resistance value including switches 5WCI to 5WCn.
オペアンプＯＰの負入力端と正入力端間に挿入された抵
抗Ｒ２にも抵抗値補正用の抵抗Ｒ，−ｒ／Ｒの常閉スイ
ッチＳＷＣを直列に挿入する。A normally closed switch SWC of resistance value correction resistors R and -r/R is also inserted in series with the resistor R2 inserted between the negative input terminal and the positive input terminal of the operational amplifier OP.
本実施例の具体例を第５図に示す、この具体例でも第３
図に示すＰＭｏＳＦＥＴとＮＭＯ３ＦＥＴを並列接続し
たトランスファーゲートによりスイッチを構成したもの
であり、第２図に示す第１の実施例の具体例と同様であ
るので詳細な説明を省略する。A specific example of this embodiment is shown in FIG.
The switch is constituted by a transfer gate in which the PMoSFET and NMO3FET shown in the figure are connected in parallel, and since it is the same as the specific example of the first embodiment shown in FIG. 2, detailed explanation will be omitted.
［発明の効果］
以上の通り、本発明によれば、Ｒ−２Ｒはしご形抵抗回
路のＲ抵抗部に、抵抗値補正用の常閉スイッチを直列に
挿入し、２Ｒ抵抗部の抵抗の抵抗値と切換スイッチの抵
抗値の合計値が、Ｒ抵抗部の抵抗の抵抗値と常閉スイッ
チの抵抗値の合計値のほぼ２倍であるようにしているの
で、切換スイッチや常閉スイッチも含めて抵抗値がＲ−
２Ｒはしこ形抵抗回路として構成できる。したがって、
ビット数が増えてもビット数に比例して回路が大きくな
るだけであり容易に実現できる。[Effects of the Invention] As described above, according to the present invention, a normally closed switch for resistance value correction is inserted in series with the R resistance section of the R-2R ladder resistance circuit, and the resistance value of the resistance of the 2R resistance section is adjusted. The total resistance value of the changeover switch and the changeover switch is approximately twice the sum of the resistance value of the resistance of the R resistance part and the resistance value of the normally closed switch, so the changeover switch and the normally closed switch are included. The resistance value is R-
2R can be constructed as a wedge-shaped resistance circuit. therefore,
Even if the number of bits increases, the circuit will simply become larger in proportion to the number of bits, so it can be easily realized.
第１図は本発明の第１の実施例によるＤ−Ａ変換器の回
路図、
第２図は同Ｄ−Ａ変換器の具体例の回路図、第３図は同
Ｄ−Ａ変換器に用いるトランスファーゲートのオン抵抗
特性を示すグラフ、第４図は本発明の第２の実施例によ
るＤ−Ａ変換器の回路図、
第５図は同Ｄ−Ａ変換器の具体例の回路図、第６図、第
７図は従来のＤ−Ａ変換器の回路図である。
図において、
ＳＷＩ〜ＳＷｎ・・・切換スイッチ
５ＷＣ１〜５ＷＣｎ、ＳＷＣ，ＳＷｎ＋１ 、ＳＷＯ・
・・常閉スイッチ
ＯＰ・・・オペアンプ
ＧＴ １ ａ〜ＧＴ １ ｂ、 ＧＴ １ ｂ 〜ＧＴ
ｎ ｂ、 ＧＴｌｃｚＧＴｎｃ・・・トランスファーゲ
ートトランスファーケートのオン″！Ａ机符性充示彷グ
ラフ第３図Fig. 1 is a circuit diagram of a D-A converter according to a first embodiment of the present invention, Fig. 2 is a circuit diagram of a specific example of the D-A converter, and Fig. 3 is a circuit diagram of a specific example of the D-A converter. A graph showing the on-resistance characteristics of the transfer gate used, FIG. 4 is a circuit diagram of a D-A converter according to the second embodiment of the present invention, and FIG. 5 is a circuit diagram of a specific example of the same D-A converter. FIGS. 6 and 7 are circuit diagrams of conventional DA converters. In the figure, SWI~SWn... changeover switches 5WC1~5WCn, SWC, SWn+1, SWO・
...Normally closed switch OP...Operational amplifier GT1a~GT1b, GT1b~GT
n b, GTlczGTnc...Transfer gate transfer gate ON''!
Claims (1)
ジタル信号に応じて切換えられる切換スイッチが直列に
挿入されたＤ−Ａ変換器において、 前記Ｒ−２Ｒはしご形抵抗回路のＲ抵抗部に、抵抗値補
正用の常閉スイッチが直列に挿入され、前記２Ｒ抵抗部
の抵抗の抵抗値と前記切換スイッチの抵抗値の合計値が
、前記Ｒ抵抗部の抵抗の抵抗値と前記常閉スイッチの抵
抗値の合計値のほぼ２倍であることを特徴とするＤ−Ａ
変換器。 ２、請求項１記載のＤ−Ａ変換器において、前記切換ス
イッチ及び常閉スイッチは、並列接続されたＰＭＯＳＦ
ＥＴとＮＭＯＳＦＥＴを有するトランスファーゲートで
あることを特徴とするＤ−Ａ変換器。[Claims] 1. In a D-A converter in which a changeover switch that is switched according to an input digital signal is inserted in series in the 2R resistance section of the R-2R ladder resistance circuit, the R-2R ladder resistance circuit has the following features: A normally closed switch for resistance value correction is inserted in series with the R resistance section of the resistance circuit, and the total value of the resistance value of the resistor of the 2R resistance section and the resistance value of the changeover switch is equal to the resistance value of the resistance of the R resistance section. A D-A characterized in that the resistance value is approximately twice the sum of the resistance value and the resistance value of the normally closed switch.
converter. 2. In the D-A converter according to claim 1, the changeover switch and the normally closed switch are PMOSFs connected in parallel.
A DA converter characterized in that it is a transfer gate having an ET and an NMOSFET.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2134189A JPH02202227A (en) | 1989-01-31 | 1989-01-31 | D-a converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2134189A JPH02202227A (en) | 1989-01-31 | 1989-01-31 | D-a converter |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02202227A true JPH02202227A (en) | 1990-08-10 |
Family
ID=12052403
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2134189A Pending JPH02202227A (en) | 1989-01-31 | 1989-01-31 | D-a converter |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02202227A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0663108A (en) * | 1992-08-25 | 1994-03-08 | Sani Clean Nagano:Kk | Movable device using ultraviolet lamp for sterilizing and dixinfecting floor of room and corridor |
| US6778120B2 (en) | 2002-01-28 | 2004-08-17 | Sharp Kabushiki Kaisha | D/A converter circuit, and portable terminal device and audio device using the D/A converter circuit |
| KR100681685B1 (en) * | 2004-12-30 | 2007-02-09 | 동부일렉트로닉스 주식회사 | Repairable Digital-Analog Converter |
| JP2011029417A (en) * | 2009-07-27 | 2011-02-10 | Fujitsu Semiconductor Ltd | Semiconductor device |
-
1989
- 1989-01-31 JP JP2134189A patent/JPH02202227A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0663108A (en) * | 1992-08-25 | 1994-03-08 | Sani Clean Nagano:Kk | Movable device using ultraviolet lamp for sterilizing and dixinfecting floor of room and corridor |
| US6778120B2 (en) | 2002-01-28 | 2004-08-17 | Sharp Kabushiki Kaisha | D/A converter circuit, and portable terminal device and audio device using the D/A converter circuit |
| KR100681685B1 (en) * | 2004-12-30 | 2007-02-09 | 동부일렉트로닉스 주식회사 | Repairable Digital-Analog Converter |
| JP2011029417A (en) * | 2009-07-27 | 2011-02-10 | Fujitsu Semiconductor Ltd | Semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3099026B2 (en) | Integrated circuit having D / A converter, digital to analog converter and method | |
| US6414616B1 (en) | Architecture for voltage scaling DAC | |
| US6380877B2 (en) | Method and apparatus for digital to analog converters with improved switched R-2R ladders | |
| JP3967774B2 (en) | Improved switch architecture for R / 2R digital-to-analog converters | |
| US5047665A (en) | Low noise, low offset, high speed CMOS differential amplifier | |
| GB2258779A (en) | Fet differential amplifier with output offset correction. | |
| US5446455A (en) | Auto-calibrated current-mode digital-to-analog converter and method therefor | |
| EP0325378B1 (en) | Digital-to-analog converter | |
| US4958155A (en) | Ultra fast digital-to-analog converter with independent bit current source calibration | |
| JPH0454407B2 (en) | ||
| EP1465347B1 (en) | Monotonic precise current DAC | |
| US4634993A (en) | High gain, low drift operational amplifier for sample and hold circuit | |
| US5894281A (en) | Digital-to-analog converter utilizing MOS transistor switching circuit with accompanying dummy gates to set same effective gate capacitance | |
| JP3099717B2 (en) | D / A conversion circuit | |
| US4635038A (en) | CMOS-transistor-based digital-to-analog converter | |
| US5055847A (en) | Differential sensing current-steering analog-to-digital converter | |
| JPH0377430A (en) | D/a converter | |
| US4837572A (en) | Digital-to-analog converter | |
| KR20020059803A (en) | Digital-to-analog converter | |
| US4567463A (en) | Circuit for improving the performance of digital to analog converters | |
| JPH02202227A (en) | D-a converter | |
| US4811017A (en) | Digital-to-analog converter | |
| JP2000323991A (en) | Voltage generating circuit and d/a converting circuit | |
| US6104330A (en) | Digital to analogue and analogue to digital converters | |
| JPH1065542A (en) | A/d converter circuit |