JPH0918513A - Data communication method - Google Patents

Abstract

PURPOSE: To provide a data communication method which enables a communication device, which has only a bit synchronizing circuit, to send and receive asynchronous and character-synchronous data. CONSTITUTION: This method includes a step wherein a dummy frame 405 of dummy bit synchronism is added to the head of asynchronous or character- synchronous data on a transmission side and the data are transmitted, a step wherein the dummy frame 405 of bit synchronism is detected on a reception side, and a step wherein when the dummy frame 405 of bit synchronism is detected, bit-synchronous data in a following idle period 408 are received as asynchronous data or character-synchronous data 406.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to all communication systems from a local area network to a wide area network, and more particularly to electronic notebooks, personal computers, workstations, office processors, large computers, POS (Point Of Sales), ECR ( Electronic C
ash Register), sequencer, etc.

[0002]

2. Description of the Related Art As a communication method for performing conventional character synchronous communication and bit synchronous communication by a single data communication device, for example, Japanese Patent Laid-Open No. 62-36935 is known.
Is disclosed in Japanese Patent Publication No. What is disclosed in this publication is a device having both a character synchronizing circuit and a frame synchronizing circuit, which is equipped with a synchronizing code detecting circuit and a synchronizing method instruction register, and the synchronizing code detecting circuit allows the partner device to determine which one of the synchronizing signals is received. According to the method, it is determined whether or not the signal is transmitted, and the synchronous method instruction register automatically switches to the corresponding synchronous method receiving circuit.

[0003]

As described above, in the communication method in which the conventional character synchronization type communication and bit synchronization type communication are performed by one data communication device, both the character synchronization circuit and the bit synchronization circuit are used. There was a problem that was required.

Therefore, in the data communication method according to the first aspect, even a communication device having only a bit synchronization circuit (synonymous with a frame synchronization circuit) transmits not only bit synchronization communication data but also start / stop synchronization and character synchronization communication. An object of the present invention is to provide a data communication method capable of transmitting and receiving data at high speed.

A data communication method according to a second aspect is the data communication method according to the first aspect, wherein when the data of bit synchronization in the idle section is received as data of start-stop synchronization or data of character synchronization, start-stop synchronization is performed. It is an object of the present invention to provide a data communication method capable of knowing the end of a packet of data of a character or data of character synchronization.

According to a third aspect of the data communication method of the present invention, in the data communication method of the first aspect, when bit synchronization data in an idle section is received as start-stop synchronization data, each data starts in start-stop synchronization. It is an object of the present invention to provide a data communication method that can easily decode the start-stop synchronization data from the data received as the bit synchronization by starting the bit but removing it.

According to a fourth aspect of the present invention, in the data communication method according to the first aspect, the bit synchronization data in the idle section is received when it is received as start-stop synchronization data or character synchronization data. An object of the present invention is to provide a data communication method capable of easily decoding received start-stop synchronization data or character-synchronization data even if the character length of bit-synchronization data is different from the start-stop synchronization character length or the character synchronization character length. And

According to a fifth aspect of the data communication method of the present invention, in the data communication method of the fourth aspect, when bit synchronization data in the idle section is received as start / stop synchronization data, it is received as start / stop synchronization data. An object of the present invention is to provide a data communication method capable of easily decoding received start-stop synchronization data by detecting a start bit even when the character length of the bit-start synchronization data is different from the start-stop synchronization character length.

According to a sixth aspect of the data communication method of the present invention, in the data communication method according to the fourth aspect, the bit received as the start / stop synchronization data when the bit synchronization data in the idle section is received as the start / stop synchronization data. An object of the present invention is to provide a data communication method capable of easily decoding received character-synchronized data by detecting a synchronous character even when the character length of the synchronized data is different from the character length of the start-stop synchronization.

[0010]

A data communication method according to claim 1 of the present application is a communication method for transmitting and receiving communication data of start-stop synchronization or character synchronization by a communication device having only a bit synchronization circuit, In the step of adding a packet of dummy bit synchronization to the beginning of the data of start-stop synchronization or the data of character synchronization,
The receiving side includes a step of detecting a bit synchronization packet, and a step of receiving the bit synchronization data in the idle period thereafter when the bit synchronization packet is detected as start-stop synchronization data or character synchronization data. Characterize.

A data communication method according to a second aspect is the data communication method according to the first aspect, in which the transmitting side
A step of adding and transmitting a dummy bit synchronization packet also after the start-stop synchronization data or the character synchronization data; and the dummy bit added after the start-stop synchronization data or the character synchronization data at the receiving side A step of detecting a synchronization packet and determining the end of the start-stop synchronization data or the character synchronization data.

A data communication method according to a third aspect is the data communication method according to the first aspect, wherein the dummy bit synchronization packet and the start-stop packet are transmitted and received on the transmitting side when transmitting / receiving start-stop synchronization communication data. A step of adding ((character length of bit synchronization) -1) bits of dummy data to the synchronization data and transmitting, and a step of transmitting the transmission / reception of the start / stop synchronization on the receiving side ((bit (Character length of synchronization) -1) receiving dummy data of 1 bit and data of bit synchronization subsequent to the data corresponding to a start bit of start-up synchronization that follows thereafter as data of start-stop synchronization.

A data communication method according to a fourth aspect is the data communication method according to the first aspect, wherein the character length of the bit-synchronized data received as start-stop synchronization data or character-synchronization data on the receiving side. Is different from the character length of the start-stop synchronization or the character length of the character synchronization, each received data of the bit synchronization is decomposed / combined in a bit unit to obtain a predetermined value equal to the character length of the start-stop synchronization or the character length of the character synchronization. Reconstructing into a character having a character length of.

A data communication method according to a fifth aspect is the data communication method according to the fourth aspect, wherein each reception data of the bit synchronization is transmitted in bit units on the receiving side when transmitting / receiving the start / stop synchronization communication data. By reconstructing into a character of start / stop synchronization having a predetermined character length equal to the character length of start / stop synchronization by detecting the start bit of start / stop synchronization data, and then decoding the start / stop synchronization data. Is further included.

A data communication method according to a sixth aspect is the data communication method according to the fourth aspect, wherein each of the bit-synchronized received data is transmitted in bit units on the receiving side when transmitting / receiving character-synchronized communication data. By reconstructing into a character-synchronized character having a predetermined character length equal to the character-synchronized character length by decomposing / combining with, and detecting a character-synchronous data synchronous character, and then decoding the character-synchronous data. Is further included.

[0016]

In the data communication method according to claim 1,
On the sending side, a dummy bit-sync packet is added to the beginning of the start-stop synchronization or character-sync data, and on the receiving side, a bit-sync packet is detected. When a bit-sync packet is detected, the bits in the subsequent idle intervals are detected. The synchronization data is received as start-stop synchronization data or character synchronization data.

Therefore, the communication device having only the bit synchronization circuit can transmit and receive not only the bit synchronization communication data but also the start-stop synchronization and character synchronization communication data at high speed.

In the data communication method described in claim 2, in addition to the operation of the invention described in claim 1, a dummy bit synchronization packet is added after the start-stop synchronization or character synchronization data on the transmitting side. At the receiving side, a dummy bit synchronization packet added after the start-stop synchronization data or the character synchronization data is detected to determine the end of the start-stop synchronization data or the character synchronization data.

Therefore, when the bit synchronization data in the idle section is received as the start-stop synchronization data or the character synchronization data, it is possible to know the end of the packet of the start-stop synchronization data or the character synchronization data.

In the data communication method according to a third aspect of the present invention, in addition to the operation of the first aspect of the present invention, a dummy bit synchronization packet and the start-stop packet are transmitted and received on the transmitting side when transmitting / receiving start-stop synchronization communication data. ((Bit synchronization character length) -1) bits of dummy data are added to the synchronization data and transmitted, and at the reception side, ((bit synchronization character length) -1) bits of dummy data and The data corresponding to the start bit of the start-stop synchronization and the following are discarded, and the data of the subsequent bit synchronization is received as the start-stop synchronization data.

Therefore, when the data of bit synchronization in the idle section is received as the data of the start / stop synchronization in claim 1, since each data starts from the start bit in the start / stop synchronization, the data received as the bit synchronization is removed by removing the start bit. It is possible to easily decipher the start-stop synchronization data.

In the data communication method described in claim 4, in addition to the operation of the invention described in claim 1, the character length of the bit synchronization data received as start-stop synchronization data or character synchronization data on the receiving side. Is different from the character length of the start-stop synchronization or the character length of the character synchronization, each received data is decomposed / combined bit by bit to make the bit-synchronized data equal to the character length of the start-stop synchronization or the character length of the character synchronization. To the character length of.

Therefore, when the bit synchronization data in the idle section is received as start / stop synchronization data or character synchronization data, the character of the bit synchronization data received as start / stop synchronization data or character synchronization data. Even when the length is different from the character length in the start-stop synchronization or the character length in the character-sync, the received start-stop synchronization data or the character-sync data can be easily decoded.

In the data communication method according to the fifth aspect, in addition to the effect of the invention according to the fourth aspect, each reception data is decomposed / bit by bit on the reception side when transmitting / receiving start / stop synchronization communication data. By synthesizing, the data is reconstructed into a start-stop synchronization character having a predetermined character length equal to the start-stop synchronization character length, the start bit of the start-stop synchronization data is detected, and then the start-stop synchronization data is decoded.

Therefore, even when the bit synchronization data in the idle section is received as the start / stop synchronization data, the bit length of the bit synchronization data received as the start / stop synchronization data is different from the start / stop synchronization character length. By detecting the start bit, the received start-stop synchronization data can be easily decoded.

In the data communication method according to the sixth aspect, in addition to the operation of the invention according to the fourth aspect, each reception data is decomposed / bit by bit on the receiving side when transmitting / receiving character synchronization communication data. By synthesizing, it is reconstructed into a character-synchronized character having a predetermined character length equal to the character-synchronized character length, and after detecting the synchronous character of the character-synchronized data, the character-synchronized data is decoded.

Therefore, when the bit synchronization data in the idle section is received as the character synchronization data in claim 4, even if the character length of the bit synchronization data received as the character synchronization data is different from the character synchronization character length. , The received character synchronization data can be easily decoded by detecting the synchronization character.

[0028]

Embodiments of the present invention will be described in detail below with reference to the drawings.

[First Embodiment] An embodiment of claim 1 will be described with reference to FIGS. 1, 2, 3, 4, and 10.

First, in FIG. 10, a device 1001 includes a control device 1002, a storage device 1003 connected thereto, a temporary storage device 1004, an input device 1005, an output device 1006, a transmission device 1007, and a reception device 1008.
And a line interface 1009 connected to the transmitter 1007 and the receiver 1008. The line interface 1009 is connected to the line 1014.

First, at the time of transmission, the control device 1002
The information input from the input device 1005 or the information recorded in the storage device 1003 or the temporary storage device 1004 is sent as it is or after being converted as transmission data from the transmission device 1007 to the line 1014 via the line interface 1009. To do. At this time, the control device 1
002 is a temporary storage device 1004 depending on an instruction from the input device 1005 or a procedure recorded in the storage device 1003 or the temporary storage device 1004.
Work as a working place.

Next, at the time of reception, the control device 1002 transfers the data from the line 1014 to the line interface 100.
The data is directly or converted from the receiving device 1008 via 9 and recorded in the temporary storage device 1004 or output to the output device 1006, or some operation is performed based on these information. At this time, the control device 1002
Is an instruction from the input device 1005 or the storage device 10
03 or the instruction recorded in the temporary storage device 1004, the temporary storage device 1003 or the temporary storage device 1
Depending on the procedure recorded in 004, the above-described recording, output, or operation is performed using the temporary storage device 1004 as a work place in some cases.

In the above device, first, for each data of start-stop synchronization, character synchronization and bit synchronization,
This will be described with reference to FIG. In the case of start / stop synchronization 101, each data 1
10 starts with a 1-bit “0” start bit 104 and a 1-bit or more “1” stop bit 108.
Ends with. Between both bits, LSB (least significant bit) 10
There is a data bit 109 starting at 5 and ending at the MSB (most significant bit) 106, and one parity bit 107. The parity bit 107 may not be present. At the time of transmission, the transmitting device 1007 transmits the data bit 10
9 start bit 104 and stop bit 108
And the parity bit 107 are added to form transmission data, and the receiving device 1008 deletes the start bit 104, the stop bit 108, and the parity bit 107 from the reception data to form the data bit 109 when receiving.

For character sync 102, each data 114, 115, 116, 117 includes a data bit 113 beginning at the LSB 110 and ending at the MSB 111, and a parity bit 112 of one bit. The parity bit 112 may not be present. Data is synchronized with a predetermined pattern of one character or two or more SYN characters (same meaning as a synchronization character) 114, a packet starts with an STX character 115 and ends with an ETX character 117. S
Data 116 exists between the TX character 115 and the ETX character 117. Then, at the time of transmission, the transmitting device 1007 sets the data bit 113 to the parity bit 1
12 is added as transmission data, and the receiving device 1 is used at the time of reception.
008 deletes the parity bit 112 from the received data to form the data bit 113.

For bit sync 103, each packet begins with one or more opening flag characters 118 and ends with one or more closing flag characters 119. Data 120 exists between both characters, and one or more abort characters 121 exist after the closing flag character 119. When transmitting, the transmitting device 100
7 adds the opening flag character 118, the closing flag character 119 and the abort character 121 to the data 120 to make the transmission data, and the receiving device 1008 receives the opening flag character 118 and the closing character from the reception data at the time of reception.
Flag character 119 and abort character 12
1 and are deleted to make data 120.

Next, zero insertion and zero deletion of bit synchronization will be described with reference to FIG. This is because the bit pattern of the opening flag character and closing flag character is "01111110", and the bit pattern of the abort character is "11111111". Yes, zero insert works on send and zero delete works on receive. First, at the time of transmission, if there are 4 or less consecutive "1" s, it is transmitted as it is (204), and if it is 5 consecutive, then one "0" is inserted and transmitted (205, 206, 20).
7). As a result, on the line (202), one "0" is always transmitted after five "1" s in the data (212), and the opening flag character and the closing flag It can be distinguished from a character or an abort character. At the time of reception, if the number of consecutive "1" s is four or less, it is received as it is (217), and if it is five consecutive, the next "0" is deleted and received (213, 214, 215,
216, 218, 219, 220). Then, the transmitting device 1007 inserts this zero when transmitting, and the receiving device 1008 deletes this zero when receiving.

Next, a section in which the zero insertion and the zero deletion function and a section in which they do not function at the time of bit synchronization will be described with reference to FIG. Opening flag character 30
In the data 303 sandwiched between 2 and the closing flag character 304, zero insertion / zero deletion is performed (308). However, there is an idle section between the abort character 305 after the closing flag character 304 and the next opening flag character 307, and zero insertion / zero deletion is not performed on the data 306 (309).

From the above, the operation of the transmitting side will be described first with reference to FIGS. 4 and 10. First, at the time of transmission, the control device 1002
Is the information input from the input device 1005 or the information recorded in the storage device 1003 or the temporary storage device 1004 as it is, or converted as transmission data from the transmission device 1007 to the line interface 1009.
To the line 1014 via. At this time, the control device 1002 may change the temporary storage device 100 depending on the instruction from the input device 1005 or the procedure recorded in the storage device 1003 or the temporary storage device 1004.
4 is used as a work place.

The information transmitted here is the opening flag character 401, the dummy character 402,
Closing flag character 403, abort
It is a start-stop synchronization type or character synchronization type data frame 406 following the character 404, and is followed by a start-stop synchronization type or character synchronization type idle section 407.
Followed by

Similarly, the operation on the receiving side will be described with reference to FIGS. The control device 1002 directly or converts the data from the line 1014 from the receiving device 1008 via the line interface 1009, records the data in the temporary storage device 1004, outputs it to the output device 1006, or outputs these information. And perform some action. At this time, the control device 1002 displays the input device 1005.
From the storage device 1003 or the temporary storage device 1004.
Depending on the procedure stored in the temporary storage device 003 or the temporary storage device 1004, the above-described recording, output, or operation is performed using the temporary storage device 1004 as a work place in some cases.

The bit synchronization dummy frame 405 is read out from the information received here, and the bit synchronization idle section 40 following the abort character 404 is discarded.
The data frame 406 of start / stop synchronization or character synchronization included in 8 is set in the idle section 40 of bit synchronization.
Received as 8 data without deleting zero.

As described above, according to the first embodiment, the communication device having only the bit synchronization circuit transmits and receives not only the bit synchronization communication data but also the start-stop synchronization and character synchronization communication data at high speed. be able to.

[Second Embodiment] As an embodiment of the second aspect, a dummy bit synchronization packet is added to the beginning of the start-stop synchronization or character synchronization data as in the case of the first aspect of the invention. At the same time, an embodiment of a data communication method in which a dummy bit synchronization packet is added after the start-stop synchronization or character synchronization data and the end of the start-stop synchronization or character synchronization data is determined on the receiving side is shown in FIGS. explain.

First, at the time of transmission, the control device 1002 controls the information input from the input device 1005 or the storage device 1.
003 or the information recorded in the temporary storage device 1004 is sent as it is or after being converted as transmission data from the transmission device 1007 to the line 1014 via the line interface 1009. At this time, the control device 10
Reference numeral 02 denotes an instruction from the input device 1005 or the storage device 1.
003 or the procedure stored in the temporary storage device 1004, and depending on the procedure stored in the temporary storage device 1004, the temporary storage device 1004 operates as a work place in some cases.

The information transmitted here is the opening flag character 501, the dummy character 502, the closing flag character 503, the abort character 504, and the following start / stop synchronization type or character in FIG. A synchronous data frame 506, followed by an opening flag character 508, a dummy character 509, a closing flag character 510, and an abort character 511.

Next, at the time of reception, the control device 1002 transfers the data from the line 1014 to the line interface 100.
The data is directly or converted from the receiving device 1008 via 9 and is recorded in the temporary storage device 1004 or is output to the output device 1006, or some operation is performed by using this information. At this time, the control device 1002
Is an instruction from the input device 1005 or the storage device 10
03 or the instruction recorded in the temporary storage device 1004, the storage device 1003 or the temporary storage device 100
Depending on the procedure recorded in No. 4, the above-mentioned recording, output or operation is performed using the temporary storage device 1004 as a work place in some cases.

Here, the bit-synchronous opening dummy frame 505 is discarded from the information received in FIG. 5, and the start-stop or character-synchronous data frame 506 subsequent to the abort character 504 is closed after the bit-synchronization. -Receive data up to dummy frame 512 as data in bit synchronization idle section 507 without deleting zeros.

As described above, according to the second embodiment, when the bit synchronization data in the idle section is received as the start-stop synchronization data or the character synchronization data, the start-stop synchronization data or the character synchronization data packet is received. You can know the end of.

[Third Embodiment] As an embodiment of claim 3, as in the embodiment of claim 1, a dummy bit synchronization packet is added to the beginning of data of start-stop synchronization or character synchronization, and start-stop synchronization is performed. On the transmitting side when transmitting / receiving the communication data of (1), by adding dummy data of (bit synchronization character length-1) bits between the dummy bit synchronization packet and the start / stop synchronization data, An embodiment of a data communication method for removing the influence of a start bit of synchronous data is shown in FIGS. 6 and 1.
0 will be described.

To simplify the description, it is assumed that the character lengths of bit synchronization and start / stop synchronization are both 8 bits.

First, at the time of transmission, the control device 1002 controls the information input from the input device 1005 or the storage device 1.
003 or the information recorded in the temporary storage device 1004 is sent as it is or after being converted as transmission data from the transmission device 1007 to the line 1014 via the line interface 1009. At this time, the control device 10
Reference numeral 02 denotes an instruction from the input device 1005 or the storage device 1.
003 or a procedure recorded in the temporary storage device 1004, the temporary storage device 1004 operates as a work place in some cases.

The information transmitted here is the opening flag character 601, the dummy character 602, and the closing flag character 6 in FIG.
03, an abort character 604, 7-bit dummy data 605 following the abort character 604, and start / stop synchronization data 606 following the dummy data 605.

Next, at the time of reception, the control device 1002 transfers the data from the line 1014 to the line interface 100.
The data is directly or converted from the receiving device 1008 via 9 and recorded in the temporary storage device 1004 or output to the output device 1006, or some operation is performed based on these information. At this time, the control device 1002
Is an instruction from the input device 1005 or the storage device 10
03 or the instruction recorded in the temporary storage device 1004, the storage device 1003 or the temporary storage device 100
According to the procedure recorded in No. 4, the above-mentioned recording, output, or operation is performed using the temporary storage device 1004 as a work place in some cases.

Here, in FIG. 6, the opening dummy frame 612 of bit synchronization is read out from the received information and the 7-bit dummy data 605 is received. Start bit 607 at the beginning of synchronous data 606
And becomes 8 bits, which is regarded as one bit-synchronized character. Therefore, one character of the start / stop synchronization type data 606 is regarded by the LSB 608 as one character of bit synchronization and can be received as it is as data of bit synchronization.

As described above, according to the third embodiment, when the bit synchronization data in the idle section is received as the start / stop synchronization data, each data starts from the start bit in the start / stop synchronization. By doing so, the data of the start-stop synchronization can be easily decoded from the data received as the bit synchronization.

[Fourth Embodiment] As an embodiment of claim 4, as in the embodiment of claim 1, a dummy bit synchronization packet is added to the beginning of the data of start-stop synchronization or character synchronization, and start-stop synchronization is performed. 7 and FIG. 11 of the embodiment of the data communication method in which the received data can be decoded even when the character length of the bit-synchronized data received as the character data or the character-synchronized data is different from the character length of the start-stop synchronization or the character synchronization. , FIG. 12, FIG.
5, FIG. 16, FIG. 19, FIG. 20, and FIG.

First, in FIG. 19, the device 1901 includes a control device 1902, a storage device 1903 connected thereto, a temporary storage device 1904, an input device 1905, and an output device 1906.
It includes a transmitter 1907, a receiver 1908, and a line interface 1909 connected to the transmitter 1907 and the receiver 1908. The line interface 1909 is connected to the line 1914. The temporary storage device 1904 has a storage area A 1910 and a storage area B 1911.
And storage area C1912, storage area D1913, and variable "i"
Area 1915 for storing a variable, an area 1916 for storing a variable “j”, an area 1917 for storing a variable “m”, and an area 19 for storing a variable “n”.
18 inclusive.

In such a device 1901, the control device 1902 is recorded in the storage device 1903 or the temporary storage device 1904 according to an instruction from the input device 1905 or an instruction recorded in the storage device 1903 or the temporary storage device 1904. Depending on the procedure, the temporary storage device 1904 may operate as a work place in some cases. At this time, the control device 1902 directly or converts the information input from the input device 1905 or the information recorded in the storage device 1903 or the temporary storage device 1904 as transmission data from the transmission device 1907 via the line interface 1909. And sends it to the line 1914. The information transmitted here is the opening flag character 701, the dummy character 702, and the closing flag character 703 in FIG.
And the abort character 704, followed by start / stop synchronization or character synchronous data 706.

Next, referring to FIG. 19, on the reception side, the control device 1902 directly or converts the data from the line 1914 from the reception device 1908 via the line interface 1909, and stores it in the temporary storage device 1904. The data is recorded or output to the output device 1906, or some operation is performed based on the information. At this time, the control device 1902 uses the instruction from the input device 1905 or the instruction recorded in the storage device 1903 or the temporary storage device 1904, and according to the procedure recorded in the storage device 1903 or the temporary storage device 1904, in some cases, the temporary storage. The above-described recording, output, or operation is performed using the device 1904 as a work place.

Here, in FIG. 7, the opening dummy frame 70 for bit synchronization is received from the received information.
9 is read and discarded, and the start-stop synchronization or character-synchronized data 706 that follows is processed in the following method.

First, the processing when the character length of the received bit-synchronized data is shorter than the character length of the start-stop synchronization or the character synchronization will be described.

Referring to FIG. 20, line 1 in FIG.
The original j-th 8-bit data 1141 received from the receiving device 1908 from the receiving device 1908 via the line interface 1909 as data in the idle period of bit synchronization.
Are n (j + 1) -8j bits of data 1143 and (j
+1) · 8-n (j + 1) -bit data 1144.

Here, "n" 1918 is a character length for start-stop synchronization and character synchronization. The former divided data is shifted by 8j-nj bits 1145 in the MSB direction, and the latter divided data is n (j +) in the LSB direction.
1) -8j bits are shifted by 1147. The former data thus shifted is the data 1146, and the latter data is the data 1148. Here, the j-th latter data 1148 and the j + 1-th former data 1146 are combined to form a new n-bit data 115.
0 is made.

Specifically, referring to FIG. 11, the 0th to 4th original data received from the receiving apparatus 1908 from the line 1914 via the line interface 1909 in FIG. 8-bit data 1101, 1111, 1121, and 1
Regarding 131, data 1101 is divided into n-bit data 1103 and 8-n-bit data 1104, and data 1111 is n- (8-n) = 2n.
-8-bit data 1113 and 8- (2n-8) = 2
The data 1121 is divided into 8-2n-bit data 1114, and n- (2 · 8-2n) = 3n−2 · for the data 1121.
8-bit data 1123 and 8- (3n−2.8) = 3
The data 1124 is divided into 8-3n-bit data 1124, and the data 1131 is n (3 / 8-3n) = 4n-3.
8-bit data 1133 and 8- (4n−3 · 8) = 4
It is divided into 8-4n-bit data 1134.

The divided data 1113 is shifted in the MSB direction by 8-n bits 1115, the data 1123 is shifted in the MSB direction by 2.8-2n bits 1125, and the data 1133 is shifted in the MSB direction by 3.8-3n bits. It is shifted by 1135 minutes. The divided data 110
4 is shifted in the LSB direction by 8- (8-n) = n bits 1107, and the data 1114 is shifted in the LSB direction by 8- (2.
8-2n) = 2n-8 bits are shifted by 1117, and the data 1124 is 8- (3 · 8-3n) = 3 in the LSB direction.
n-2 · 8 bits are shifted by 1127. The former data thus shifted in the MSB direction is data 1
116, 1126, and 1136, and the latter data shifted in the LSB direction are data 1108, 111.
8 and 1128. Here, the 0th latter data 1108 and the 1st former data 1116 are combined (1109), and new n-bit data 1110 is created. Further, the first latter data 1118 and the second former data 1126 are combined (1119) to create new n-bit data 1120. Furthermore, the second latter data 1128 and the third former data 11
36 and 1 are combined (1129) to create new n-bit data 1130, and data is reconstructed by division / composition in the same manner.

This will be described with reference to the flowchart of FIG. First, in step 1202, “j” 1916 is “0”.
In step 1203, the j-th original 8-bit input data received as the data in the bit synchronization idle section from the line 1914 via the line interface 1909 is input to the storage area A 1910 in step 1203. To be done. Storage area A19 in step 1204
By logically ^ANDing 10 data with 2 ^{n (j + 1) -8j} −1, n (j on the LSB side of the original 8-bit data is
+1) −8j bits are divided and input to the storage area B1912. In step 1205, the data in the storage area A 1910 is ANDed with 2 ⁸ −2 ^{n (j + 1) −8j} to ^obtain (j + 1) · 8 on the MSB side of the original 8-bit data.
-N (j + 1) bits are divided into storage area C1912
Is input to At step 1206, the data in the storage area B1911 is shifted to the MSB side by 8j-nj bits, and at step 1207, the data in the storage area C1912 is shifted to the LSB side by n (j + 1) -8j bits.

If "j" 1916 is "0" in step 1208, that is, if it is the first data, the data in storage area B1911 is directly used as n-bit output data in step 1209, and the data in storage area C1912 is transferred to storage area D1913 in step 1210. To be done.

If "j" 1916 is not "0" in step 1208, that is, if it is not the first data, the data in the storage area B1911 and the storage area D1 are read in step 1211.
The data in 913 is logically ORed into the output data of n bits, and it is checked in step 1212 whether it is the final data. If the final data, step 1213
Ends the process with. If not final data, step 1
Line 1914 to line interface 1909 at 203
The next original 8-bit data received as the data in the idle period of the bit synchronization by the receiving device 1908 via the is input as the input data.

Next, the processing when the character length of the received bit-synchronized data is longer than the character length of the start-stop synchronization or the character synchronization will be described. Referring to FIG.
Line 1914 to line interface 1 in FIG.
From the j-th original 8-bit data 1570 and the j + 1-th original 8-bit data 1571 received from the receiving device 1908 as data of the bit synchronization idle section via 909, the original 16-bit data is obtained. Data 154
1 is created, and the value rounded down to the decimal point of j / 2 is put in “i” 1915 (1572).
541 is n (i + 1) -16i-bit data 1543
And (i + 1) · 16-n (i + 1) -bit data 15
It is divided into 44 and. In addition, at 1572 in FIG.
T "means a process of rounding down the fractional part. Here," n "1918 is the character length of start-stop synchronization or character synchronization. The divided former data is 1 in the MSB direction.
The latter data divided by 6i-ni bits 1545 are shifted in the LSB direction by n (i + 1) -16i bits 1547. The former data thus shifted is 1546, and the latter data is 154.
8 Here, the i-th latter data 1548 and i +
The first former data 1546 is combined (154)
9), new n-bit data 1550 is created.

Specifically, referring to FIG. 15, the 0th original 8 bits received as data in the idle section of the bit synchronization from the receiving apparatus 1908 via the line interface 1909 from the line 1914 in FIG. Input data 1561, second original 8-bit data 1
563, 4th original 8-bit data 1565, 6th original 8-bit data 1567, 1st original 8-bit data 1562, and 3rd original 8-bit data 1564, the original data of 8 bits 1566, and the original data of 8 bits 1568, the original data of 16 bits 150
1, 1511, 1521, and 1531 are made.
Here, a value obtained by rounding down the decimal point of j / 2 is put in "i" 1915 (1572), and the original data 1501 of 16 bits is divided into n-bit data 1503 and 16-n-bit data 1504. To be done. Data 1511
Is n− (16−n) = 2n−16 bits of data 15
13 and 16− (2n−16) = 2 · 16−2n bits of data 1514, and the data 1521 is n.
-(2 · 16-2n) = 3n−2 · 16-bit data 1523 and 16− (3n−2 · 16) = 3 · 16-3
The data 153 is divided into n-bit data 1524 and data 153.
1 is n− (3 · 16−3n) = 4n−3 · 16-bit data 1533 and 16− (4n−3 · 16) = 4 ·
It is divided into 16-4n-bit data 1534.

The divided data 1513 is shifted by 16-n bits 1515 in the MSB direction, the data 1523 is shifted by 2.16-n bits in the MSB direction, and the data 1533 is shifted by 3.16-3n bits in the MSB direction. To be done. Further, the divided data 1504 is shifted by 16- (16-n) bits in the LSB direction to obtain data 15
14 is in the LSB direction, 16− (2 · 16−2n) = 2n
The data 1524 is shifted by -16 bits, and the data 1524 is shifted by 16- (3 * 16-3n) = 3n-2 * 16 bits in the LSB direction. The former data thus shifted in the MSB direction are data 1516, 1526, and 15
36, and the latter data shifted in the LSB direction are data 1508, 1518, and 1528.

Here, the 0th latter data 1508 and
The first former data 1516 is combined (150
9), new n-bit data 1510 is created. Further, the first latter data 1518 and the second former data 1526 are combined (1519) to create new n-bit data 1520. Further, the second latter data 1528 and the third former data 1536 are combined (1529) to create new n-bit data 1530. Similarly, the data is reconstructed by dividing / combining.

This will be described with reference to the flowchart of FIG. First, in step 1602, "j" 1916 is "0".
Is initialized to the storage area A 1910 in step 1603, and the j-th original 8-bit input received as data in the bit synchronization idle section from the line 1914 via the line interface 1909 is input to the storage area A 1910. It Next, in step 1604, “j” 1916
"1" is added to the storage area B19 in step 1605.
The next j-th original 8-bit input data received as data in the bit synchronization idle section from the line 1914 via the line interface 1909 is input to the line 11. Next, Step 1606
Then, the data in the storage area B1911 is shifted to the MSB side by 8 bits, and in step 1607 the data in the storage area B1911 and the data in the storage area A1910 are logically ORed and stored in the storage area A1910.

In step 1608, j / is added to "i" 1915.
The value rounded down to the second decimal point is entered, and step 16 is entered.
In the data of the storage area A1910 at 09, 2 ^{n (i + 1) -16i} −
The original 8-bit data L is obtained by ANDing 1s.
The n (i + 1) -16i bits on the SB side are divided and placed in the storage area B1911. In step 1610, 2 ¹⁶ −2 ^{n (i + 1) −16i} is logically ANDed with the data in the storage area A 1910 to (i + 1) · 16−n (i + 1) bits on the MSB side of the original 8-bit data. The minutes are divided and placed in storage area C1912. In step 1611, the data in the storage area B1911 is shifted to the MSB side by 16i-ni bits, and in step 1612, the storage area C1912.
Data is shifted to the LSB side by n (i + 1) -16i bits. In step 1613, “i” 1915 is “0”
In other words, if it is the first data, in step 1614 the storage area B1
The data 911 is directly used as n-bit output data. In step 1615, the data in the storage area C1912 is transferred to the storage area D1913.

If "i" 1915 is not "0" in step 1613, that is, if it is not the first data, the data in the storage area B1911 and the storage area D1 are searched in step 1616.
The data of 913 is logically ORed to obtain n-bit output data. Then, in step 1617, it is checked whether it is the final data. If the final data, step 161
The process ends at 8. If it is not the final data, in step 1603 the line 1914 to the line interface 190
The next original 8-bit data received as data in the idle section of bit synchronization via 9 is input as input data. In addition, "INT" in 1608 of FIG. 16 means a process of cutting off a part after the decimal point.

As described above, according to the fourth embodiment, when the bit synchronization data in the idle section is received as the start-stop synchronization or the character synchronization data, the bit synchronization data received as the start-stop synchronization or the character synchronization data is received. Even when the character length of the data is different from the character length of the start-stop synchronization or character synchronization, the received start-stop synchronization or character-synchronization data can be easily decoded.

[Fifth Embodiment] As an embodiment of claim 5, as in the embodiment of claim 4, each received data is decomposed / combined bit by bit to convert bit-synchronized data into start-stop synchronization or character-synchronization. An embodiment of a data communication method capable of reconstructing to a predetermined character length equal to the character length and decoding the received start / stop synchronization data will be described with reference to FIGS. 8, 13, 17, and 19.

First, in FIG. 19, the device 1901 includes a control device 1902, a storage device 1903 connected thereto, a temporary storage device 1904, an input device 1905, an output device 1906, a transmission device 1907, and a reception device 1908.
And a line interface 1909 connected to the transmitter 1907 and the receiver 1908. The line interface 1909 is connected to the line 1914.
The temporary storage device 1904 has a storage area A1910, a storage area B1911, a storage area C1912, and a storage area D19.
13, an area 1915 for storing the variable “i”,
An area 1916 for storing the variable “j”, an area 1917 for storing the variable “m”, and an area 1918 for storing the variable “n” are included.

In such a device 1901, the control device 1902 is recorded in the storage device 1903 or the temporary storage device 1904 according to an instruction from the input device 1905 or an instruction recorded in the storage device 1903 or the temporary storage device 1904. Depending on the procedure, the temporary storage device 1904 may operate as a work place in some cases. At this time, the control device 1902 directly or converts the information input from the input device 1905 or the information recorded in the storage device 1903 or the temporary storage device 1904, and transmits it as transmission data from the transmission device 1907 via the line interface 1909. To the line 1914.

In FIG. 8, the information to be transmitted is the opening flag character 801, the dummy character 802, and the closing flag character 8
03, the abort character 804, and the start / stop synchronization data 806 that follow. Further, x-bit dummy data 805 may be sent between the abort character 804 and the start / stop synchronization data 806.

Next, on the receiving side, in FIG. 19, the control device 1902 records the data from the line 1914 as it is or from the receiving device 1908 via the line interface 1909 and records it in the temporary storage device 1904.
Alternatively, the data is output to the output device 1906, or some operation is performed based on the information. At this time, the control device 1902 receives an instruction from the input device 1905 or an instruction recorded in the storage device 1903 or the temporary storage device 1904, and according to the procedure recorded in the storage device 1903 or the temporary storage device 1904. The temporary storage device 1904 operates as a work place.

The opening dummy frame 813 for bit synchronization is read out from the information received here, and the start / stop synchronization data 806 following it is processed by the following method.

First, the processing when the character length of the received bit synchronization data is shorter than the character length of the start / stop synchronization will be described.

In FIG. 13, first step 1302
Then, "m" 1917 is initialized to "8". Step 1
In 303, the original 8-bit input data received as data in the idle section of the bit synchronization from the line 1914 via the line interface 1909 in the storage area A 1910 is recorded.

In step 1304, the LSB of the data in storage area A 1910 is checked. LSB at step 1304
If is "1", the data in the storage area 1910 is shifted to the LSB by 1 bit in step 1305. Step 130
In step 6, "1" is subtracted from "m" 1917, and step 1
At 307, it is checked whether "m" 1917 is "0",
If "0", the process returns to step 1302. If not "0", the process returns to step 1304. Step 130
If the LSB is "0" in step 4, "8- in step 1308"
The value of m "is checked. If" 8-m "is" n "191
If it is equal to 8, the data in the storage area A 1910 is output as n-bit data in step 1309. If "8
If -m "is greater than" n "1918, then step 13
In step 10, 2 ⁿ -1 is logically ANDed with the data in the storage area A 1910 to output n-bit data obtained by dividing n bits on the LSB side from the original 8-bit data.

In step 1311, the data in the storage area A 1910 is logically ANDed with 2 ⁸ −2 ⁿ to divide 8-bit data on the MSB side of the original 8-bit data into the storage area A 1910. Then, in step 1312, the data in the storage area A 1910 is shifted to the LSB side by n bits. In step 1313, the data in the storage area A 1910 is put into the storage area B 1911, and in step 1314, the next original 8 received as data in the idle section of the bit synchronization from the line 1914 via the line interface 1909 is received. Bits of data are placed in storage A1910. In step 1315, the data in the storage area A 1910 is logically ANDed with 2 ^{2n-8 + m} -1 to convert the original 8-bit data to 2 on the LSB side.
The data is divided into n-8 + m bits, and in step 1316, the data in the storage area C1912 is shifted by 8-mn bits toward the MSB side. In step 1317, the data in the storage area B1911 and the data in the storage area C1912 are logically ORed to obtain n.
The data in the storage area A1910 is logically ANDed with the data in the storage area A1910 and 2 ⁸ -2 ^{2n-8 + m} in step 1318, and the 16-2n-m bit data on the MSB side is stored in the storage area A1.
It is put in 910. Storage area A19 in step 1319
10 data is shifted to the LSB side by 2n−8 + m bits, and in step 1320, “m” 1917 is 16-2n−.
m is entered, and the process returns to step 1304. If “8-m” is smaller than “n” 1918 in step 1308, the process proceeds to step 1313.

Next, the processing when the character length of the received bit synchronization data is longer than the character length of the start / stop synchronization will be described.

In FIG. 17, first step 1702
"M" 1917 is initialized to "16" by step 1
At 703, the original 16-bit input data received as data in the idle section of bit synchronization from the line 1914 via the line interface 1909 to the storage area A 1910 is input.

In step 1704, the LSB of the data in storage area A 1910 is checked. LSB at step 1704
If is "1", the data in the storage area A1910 is shifted to the LSB by 1 bit in step 1705, and then in step 170
In step 6, “1” is subtracted from “m” 1917, and step 17
At 07, it is checked whether "m" 1917 is "0".
If it is "0", the process returns to step 1702. If it is not "0", the process returns to step 1704. Step 170
If the LSB is "0" at step 4, "16-" at step 1708.
"m" can check the value. If "16-m" is "n" 19
If it is equal to 18, the storage area A1910 in step 1709
Data is output as n-bit data.

If "16-m" is larger than "n" 1918, the data in the storage area A 1910 is logically ANDed with 2 ⁿ -1 in step 1710, and the original 8-bit data is converted into n on the LSB side. Bits are divided and output as n-bit data. In step 1711, the data in the storage area A 1910 is logically ANDed with 2 ¹⁶ -2 ⁿ to obtain 1 on the MSB side of the original 16-bit data.
6-n bits are divided and stored in the storage area A1910, and in step 1712, the data in the storage area A1910 is set to L.
N bits are shifted to the SB side.

In step 1713, the data in the storage area A1910 is put into the storage area B1911, and the step 1714 is executed.
Then, the next original 16-bit data received as data in the bit synchronization idle section from the line 1914 via the line interface 1909 is put into the storage area A1910. Step 1715
Then, the data in the storage area A1910 is logically ANDed with 2 ^{2n-16 + m} −1 to obtain L from the original 16-bit data.
2n-16 + m bits on the SB side are divided, and in step 1716, the data in the storage area C1912 is divided into 16 bits on the MSB side.
-M-n bits are shifted. In step 1717, the data in the storage area B1911 and the data in the storage area C1912 are logically ORed to obtain n-bit output data, and then step 1
718 and the data in the storage area A1910 and 2 ¹⁶ -2 ^{2n-16 + m}
And are logically ANDed and 32-2n-m-bit data on the MSB side is stored in the storage area A 1910. Step 171
The data of the storage area A 1910 is 2n-16 on the LSB side in 9
+ M bits are shifted, and “m” 19 in step 1720
32-2n-m is put into 17 and the process returns to step 1704. Also, in step 1708, "16-m" is "n" 1.
If it is smaller than 918, the process proceeds to step 1713.

As described above, according to the fifth embodiment, when the bit synchronization data in the idle section is received as the start / stop synchronization data, the character length of the received bit synchronization data is equal to the start / stop synchronization character length. Even if they are different, by detecting the start bit, the received start-stop synchronization data can be easily decoded. [Sixth Embodiment] As an embodiment of claim 6, similarly to the embodiment of claim 4, each received data is decomposed / combined bit by bit and the data of bit synchronization is set to the character length of start / stop synchronization or character synchronization. An embodiment of a data communication method capable of reconstructing to an equal predetermined character length and decoding received character synchronization data is shown in FIGS.
4, FIG. 18 and FIG.

To simplify the explanation, the bit synchronization character length is 8 bits. First, referring to FIG.
The device 1901 includes a control device 1902, a storage device 1903 connected thereto, a temporary storage device 1904, an input device 1905, an output device 1906, and a transmission device 190.
7, a receiving device 1908, and a line interface 190 connected to the transmitting device 1907 and the receiving device 1908.
9 is provided. The line interface 1909 is connected to the line 1914. The temporary storage device 1904 has a storage area A 1910, a storage area B 1911, and a storage area C.
1912, a storage area D1913, an area 1915 for storing the variable “i”, an area 1916 for storing the variable “j”, and an area 19 for storing the variable “m”.
17 and an area 1918 for storing the variable “n”.

In such a device 1901, the control device 1902 is recorded in the storage device 1903 or the temporary storage device 1904 according to an instruction from the input device 1905 or an instruction recorded in the storage device 1903 or the temporary storage device 1904. Depending on the procedure, the temporary storage device 1904 operates as a work place in some cases.
At this time, the control device 1902 converts the information input from the input device 1905 or the information recorded in the storage device 1903 or the temporary storage device 1904 as it is or by converting it as communication data from the transmission device 1907 via the line interface 1909. To the line 1914.

Here, the information transmitted in FIG. 9 is the opening flag character 901, the dummy character 902, the closing flag character 903,
Following the abort character 904, character synchronization data 906 is sent. Further, x-bit dummy data 905 may be sent between the abort character 904 and the character synchronization data 906.

Next, referring to FIG. 19, a controller 1902 is provided.
Is directly or converted from the receiving device 1908 via the line 1914 via the line interface 1909, and is recorded in the temporary storage device 1904 or is output to the output device 1906, or some operation is performed based on these information. To do. At this time, the control device 1902
Instruction from input device 1905 or storage device 1903
Alternatively, according to an instruction stored in the temporary storage device 1904, the storage device 1903 or the procedure stored in the temporary storage device 1904 is used, and in some cases, the temporary storage device 1904 is used as a work place.

The opening dummy frame 911 is read out from the information received here, and the following character synchronization data 906 is processed by the following method.

First, the processing when the character length of the received bit synchronous data is shorter than the character synchronous character length will be described.

In FIG. 14, in step 1402, the storage area A 1910 is filled with the original 8-bit input data received as the data in the idle section of the bit synchronization from the line 1914 via the line interface 1909 by the receiving device 1908. Next, in step 1403, “m” 1917 is initialized to “8-n”, and step 1
At 404, the n bits on the LSB side of the data in the storage area A 1910 are examined. If the n bits on the LSB side are not SYN characters in step 1404, the data in the storage area A 1910 is shifted by 1 bit to the LSB side in step 1405, and "1" is subtracted from "m" 1917 in step 1406. In step 1407, “m” 1917 is “0”
Whether it is “0” is determined in step 1413.
Go to step 1404, if not "0". In step 1404, the n bits on the LSB side are SY.
If it is an N character, the value of "n + m" is checked in step 1408.

If the value of "n + m" is "n" 1918, the data in the storage area A 1910 is used as n-bit output data in step 1409. Also, the value of "n + m" is "n" 1
If not equal to 918, then in step 1410 storage area A
By logically ANDing 2 ⁿ −1 with the data of 1910, n bits on the LSB side are divided from the original 8 bits of data and output as n bits of data. In step 1411, the data in the storage area A 1910 and 2 ⁸ -2 ⁿ are logically ANDed to obtain the original M of 8-bit data.
Storage area A1910 is obtained by dividing 8-n bits on the SB side.
, And the data in the storage area A 1910 is shifted to the LSB side by n bits in step 1412.
At 3, the data in the storage area A1910 is put into the storage area B1911. In step 1414, it is checked whether there is data in the storage area D1913, and if there is data, step 14
In step 15, the data in the storage area D1913 is bit-shifted to the NSB side (the number of effective bits in the storage area B1911), and in step 1416, the data in the storage area B1911 and the storage area D19 are stored.
The data of 13 are logically ORed and stored in the storage area B1911, and the process proceeds to step 1417. Step 1414
If there is no data in the storage area D1913, the process immediately proceeds to step 1417.

At step 1417, the receiving device 190 is connected from the line 1914 via the line interface 1909.
The following original 8-bit data received as data in the idle period of bit synchronization by 8 is stored in the storage area A1910.
Can be put in. In step 1418, the data in the storage area A 1910 and 2 ^k -1 (k = (8-the effective number of bits in the storage area B 1911)) are logically ANDed to convert the original 8-bit data from the LSB side (8- The number of effective bits of the storage area B1911) is divided. Step 1419
The data in storage area C1912 is transferred to the MSB side (storage area B1
911 effective bits) bit-shifted, step 1
Data in storage area B1911 and storage area C1912 in 420
Data is logically ORed into the storage area A1910. In step 1421, data in the storage area A 1910 and 2
⁸ −2 ^k (k = (8−the number of effective bits of the storage area B1911)) is logically ANDed and (MS storage area B1911)
(The effective number of bits of) is stored in the storage area D1913, and the process returns to step 1403.

Next, the processing when the character length of the received bit synchronous data is longer than the character synchronous character length will be described.

Referring to FIG. 18, in step 1802, the storage area A 1910 is filled with the original 16-bit input data received as the data in the idle section of the bit synchronization from the line 1914 via the line interface 1909 by the receiving device 1908. Then, in step 1803, “m” 1917 is initialized to “16-n”. In step 1804, n on the LSB side of the data in the storage area A 1910
The bits are examined. In step 1804, n on the LSB side
If the bit is not a SYN character, step 180
In step 5, the data in the storage area A1910 is shifted to the LSB by 1 bit, and in step 1806, "m" 1917 to "1".
Is drawn. In step 1807, it is checked whether "m" 1917 is "0", and if "0", step 1
Proceed to 813, and if not "0", step 1804.
Return to If the n bit on the LSB side is a SYN character in step 1804, "n + m" is determined in step 1808.
The value of is examined.

If the value of "n + m" is "n" 1918, the data in the storage area A 1910 is set to n-bit output data in step 1809. Also, the value of "n + m" is "n" 1
If not equal to 918, then in step 1810 storage area A
By logically ANDing the data of 1910 and 2 ⁿ −1, the original 8-bit data is divided into n bits on the LSB side and output as n-bit data. In step 1811, the data in storage area A 1910 and 2 ¹⁶ -2 ⁿ
16-n bits on the MSB side of the original 16-bit data are divided by ANDing with the storage area A
1910, and in step 1812 the storage area A19
10 bits of data are shifted to the LSB side by n bits. In step 1813, the data in the storage area A1910 is stored in the storage area B1.
911 and storage area D191 in step 1814.
The presence or absence of the data of 3 is checked. If there is data, the data in the storage area D1913 is bit-shifted to the MSB (the number of effective bits in the storage area B1911) in step 1815, and the data in the storage area B1911 and the data in the storage area D1913 are logically ORed and stored in step 1816. Area B19
11 is entered, and the process proceeds to step 1817. If there is no data in the storage area D1913 in step 1814, the process immediately proceeds to step 1817.

At step 1817, the receiving device 190 is connected from the line 1914 via the line interface 1909.
The following original 16-bit data received as data of the idle section of bit synchronization by 8 is stored in the storage area A191.
It can be put in 0. Storage area A1910 in step 1818
And 2 ^k −1 (k = (16−the number of effective bits of storage area B1911)) are logically ANDed to obtain (16−storage area B1 on the LSB side from the original 16-bit data.
911 effective bits) bits are divided. In step 1819, the data in the storage area C1912 is bit-shifted to the MSB side (the number of effective bits in the storage area B1911), and in step 1820, the data in the storage area B1911 and the storage area C are stored.
The data in 1912 is logically ORed and stored in the storage area A 1910. In step 1821, the data in the storage area A 1910 and 2 ¹⁶ −2 ^k (k = (16−the effective number of bits in the storage area B 1911)) are logically ANDed to each other (the storage area B on the MSB side).
1911 effective bit number) bit data is stored in the storage area D1
It is put in 913 and it returns to step 1803.

As described above, according to the sixth embodiment, when the bit synchronization data in the idle section is received as the character synchronization data and the character length of the bit synchronization data is different from the character synchronization character length. However, by detecting the sync character,
The received character synchronization data can be easily decoded.

[0107]

As described above, according to the data communication method of the first aspect of the present invention, the dummy bit synchronization packet is added to the beginning of the start-stop synchronization data or the character synchronization data at the transmitting side, The bit sync packet is detected at the receiving side, and when the bit sync packet is detected, the bit sync data in the subsequent idle section is received as start-stop sync data or character sync data. Even in the case of using the device, it is possible to provide a data communication method capable of transmitting and receiving not only bit-synchronized communication data but also start-stop synchronization and character-synchronization communication data at high speed.

According to the data communication method of the second aspect, in addition to the effect of the first aspect of the invention, a dummy bit synchronization packet is added after the start-stop synchronization or character synchronization data on the transmitting side. The bit in the idle section according to claim 1, wherein the receiving side detects a dummy bit-sync packet added after the start-stop sync or character-sync data and determines the end of the start-stop sync data or the character-sync data. It is possible to provide a data communication method capable of knowing the end of the packet of start-stop synchronization data or character-sync data when the synchronization data is received as start-stop synchronization data or character-sync data.

According to the data communication method of the third aspect, in addition to the effect of the invention of the first aspect, a dummy bit synchronization packet is transmitted on the transmitting side when transmitting / receiving start / stop synchronization communication data. Between the start-stop synchronization data,
((Bit-synchronized character length) -1) Dummy data is added and transmitted, and at the receiving side of the start-stop synchronized communication data, ((bit-synchronized character length)-
1) Since the bit synchronization data and the data corresponding to the bit synchronization data subsequent to the data corresponding to the start bit of the start-stop synchronization are received as the start-stop synchronization data, the bit-synchronization data in the idle section according to claim 1 is received. When received as data, each data starts with a start bit in start-stop synchronization, but by removing this, it is possible to provide a data communication method that can easily decode start-stop synchronization data from data received as bit-synchronization. it can.

According to the data communication method of the fourth aspect, in addition to the effect of the first aspect of the invention, the data of the bit synchronization received as the data of the start-stop synchronization or the data of the character synchronization is received on the receiving side. The character length is
If the character length is different from the character length in the start-stop synchronization or the character length in the character synchronization, the received data in the bit-sync is decomposed / combined in bit units to obtain a predetermined character equal to the character length in the start-stop synchronization or the character length in the character synchronization. Since the data is reconstructed into a long character, the bit received as the start-stop synchronization data or the character synchronization data when the bit synchronization data in the idle section is received as the start-stop synchronization data or the character synchronization data. It is possible to provide a data communication method capable of easily decoding received start-stop synchronization data or character-sync data even when the character length of the start-sync data is different from the character length of start-stop synchronization or the character length of character-sync.

According to the data communication method of the fifth aspect, in addition to the effect of the invention of the fourth aspect, each reception data is transmitted in bit units at the receiving side when transmitting / receiving start / stop synchronization communication data. Claims: Since the data is reconstructed by synthesizing / disassembling into a character of start / stop synchronization having a predetermined character length equal to the character length of start / stop synchronization, the start bit of start / stop synchronization data is detected, and then the start / stop synchronization data is decoded. Even when the character length of the bit synchronization data received as the start-stop synchronization data when the bit synchronization data in the idle section is received as the start-stop synchronization data in 4 is different from the start-stop synchronization character length,
By detecting the start bit, it is possible to provide a data communication method capable of easily decoding received start-stop synchronization data.

According to the data communication method of the sixth aspect, in addition to the effect of the invention of the fourth aspect, on the receiving side when transmitting and receiving character-synchronized communication data,
After each received data is decomposed / combined bit by bit, it is reconstructed into a character-synchronized character having a predetermined character length equal to the character-synchronized character length, and the character-synchronized data of the character-synchronized data is detected. Therefore, even if the character length of the bit synchronization data received as the start / stop synchronization data is different from that of the start / stop synchronization when the bit synchronization data in the idle section is received as the start / stop synchronization data. By detecting the synchronization character, it is possible to provide a data communication method that can easily decode the received character synchronization data.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of communication methods of start-stop synchronization, character synchronization, and bit synchronization.

FIG. 2 is an explanatory diagram of zero insertion / zero deletion in bit synchronization.

FIG. 3 is an explanatory diagram of a section in which zero insertion / zero deletion of bit synchronization is performed and a section in which zero insertion / zero deletion is not performed.

FIG. 4 is a diagram of communication data according to the first embodiment of claim 1.

FIG. 5 is a diagram of communication data of the second embodiment according to claim 2;

FIG. 6 is a diagram of communication data of a third embodiment according to claim 3;

FIG. 7 is a diagram of communication data of a fourth embodiment according to claim 4;

FIG. 8 is a diagram of communication data of the fifth embodiment according to claim 5;

FIG. 9 is a diagram of communication data of the sixth embodiment according to claim 6;

FIG. 10 is a block diagram showing a device example of a first embodiment, a second embodiment and a third embodiment according to claim 1, claim 2 and claim 3;

FIG. 11 is a specific explanatory diagram of decomposition / combination of received data when the character length of the received data is short according to the fourth embodiment of the present invention.

FIG. 12 is a flowchart of decomposition / composition of received data when the character length of the received data is short according to the fourth embodiment of the present invention.

FIG. 13 is a flowchart of processing received data in a fifth embodiment according to claim 5;

FIG. 14 is a flowchart of a process of received data in a sixth embodiment according to claim 6;

FIG. 15 is a specific explanatory diagram of disassembling / combining the received data when the character length of the received data is long according to the fourth embodiment of the present invention.

FIG. 16 is a flowchart of decomposition / composition of received data when the character length of the received data is long according to the fourth embodiment of the present invention.

FIG. 17 is a flowchart of processing of received data in a fifth embodiment according to claim 5;

FIG. 18 is a flowchart of a process of received data in a sixth embodiment according to claim 6;

FIG. 19 is a block diagram showing a device example of a fourth embodiment, a fifth embodiment and a sixth embodiment according to claim 4, claim 5 and claim 6;

FIG. 20 is a general explanatory diagram of decomposition / composition of received data when the character length of the received data is short according to the fourth embodiment of the present invention.

FIG. 21 is a general explanatory diagram of decomposition / synthesis of received data when the character length of the received data is long according to the fourth embodiment of the present invention.

[Explanation of symbols]

101 Asynchronous 102 Character Synchronous 103,301 Bit Synchronous 104,607,807 Start Bit 405 Bit Synchronous Dummy Frame 408,507 Bit Synchronous Idle Section 406,506,706 Asynchronous or Character Synchronous Data Frame 606 806 Asynchronous data frame 906 Character synchronous data frame 407 Asynchronous or character synchronous idle section

Claims (6)

[Claims] 1. A communication method for transmitting and receiving communication data of start-stop synchronization or character synchronization in a communication device having only a bit synchronization circuit, wherein a dummy bit is provided at the beginning of start-stop synchronization data or character synchronization data on the transmission side. When a sync packet is added and transmitted, at the receiving side, a bit sync packet is detected, and when a bit sync packet is detected, the bit sync data in the idle period after that is detected. And a step of receiving as synchronous data. 2. A step of adding a dummy bit synchronization packet after the start-stop synchronization data or the character synchronization data at the transmitting side and transmitting the data, and a step of receiving the start-stop synchronization data or the character synchronization data at the receiving side. Further comprising the step of detecting the dummy bit synchronization packet added after, and determining the end of the start-stop synchronization data or the character synchronization data.
The data communication method described in 1. 3. On the transmitting side when transmitting / receiving start / stop synchronization communication data, between the dummy bit synchronization packet and the start / stop synchronization data, ((bit synchronization character length) -1)
And a step of adding dummy data of bits, and at the receiving side, bit synchronization of the data corresponding to the ((bit synchronization character length) -1) bits of dummy data and the start bit of the start-stop synchronization that follows. The data communication method according to claim 1, further comprising the step of: receiving the data of step 1 as start-stop synchronization data. 4. When the character length of the bit synchronization data received as the start-stop synchronization data or the character synchronization data at the receiving side is different from the start-stop synchronization character length or the character synchronization character length, each received data is bit-coded. Disassemble in units /
The data communication method according to claim 1, further comprising the step of reconstructing bit-synchronized data into a character having a predetermined character length equal to the character length of the start-stop synchronization or the character length of character synchronization by combining. 5. A communication method for transmitting / receiving start / stop synchronization communication data, wherein the reception side decomposes / combines each received data in bit units to obtain a start / stop synchronization of a predetermined character length equal to the start / stop synchronization character length. 5. The data communication method according to claim 4, further comprising the step of reconstructing the start character of the start / stop synchronization data and decoding the start / stop synchronization data. 6. A communication method for transmitting and receiving character-synchronized communication data, wherein the receiving side decomposes / combines each received data bit by bit to obtain a character synchronization having a predetermined character length equal to the character length of the character synchronization. 5. The data communication method according to claim 4, further comprising the step of reconstructing the character synchronization data, detecting the synchronization character of the character synchronization data, and then decoding the character synchronization data.