JPH09179723A - Multiplier and arithmetic unit for sum of product - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the number of inputs to an adder for adding partial products in a multiplier. SOLUTION: A multiplier encoder 101 encodes an 8-bit multiplier in accordance with secondary Booth's algorithm. In parallel with the encoding, a complementer 102 bit-inverts the five lower bits of an 8-bit multiplicand and adds '1' to the bit-inverted multi-plicand to form a 2's compliment and finds out complement data and a carry. A multi-input adder 104 adds four partial products generated by 1st to 4th partial product generators 110 to 113 from the output of the encoder 101 and the multiplicand to find out a product. When the logic value of a partial product complementing bit in the uppermost part of the output from the encoder 101 is '1', a selector circuit 103 substitutes the five lower bits of 4th partial product data generated by the 4th partial product generator 113 for the complement data of the circuit 102 and the influence of the carry of the complementer 102 to three upper bits of the 4th partial product data is attained in the 1st and 2nd partial product generators 110, 111.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplication device and a product-sum calculation device using the multiplication device.

[0002]

2. Description of the Related Art In recent years, there has been an increasing demand for speeding up of semiconductor integrated circuits, and a high-speed multiplying device is required for a multiplying device which is one of the arithmetic elements. As one of algorithms for realizing a high-speed multiplication device, there is Booth's algorithm for coding a multiplier to generate a partial product. In a multiplication device, generally, a product is calculated by adding a plurality of partial products generated using inputs of a multiplier and a multiplicand. According to Booth's algorithm, by encoding the multipliers to generate partial products,
The number of partial products can be reduced. For example, the number of partial products can be halved in the second-order Booth algorithm. The operation speed of the adder for adding partial products depends on the number of partial products, and the larger the number of partial products, the lower the operation speed. If the number of partial products, that is, the number of inputs to the adder is reduced to about half, the load on the adder is reduced, and as a result, the speeding up of the addition is achieved.

Now, the negative partial product data generated by coding the multiplier is data in the one's complement format. Therefore, the process of performing sign extension on the negative partial product data and the process of adding the bit of the logical value “1” for converting the negative partial product data to 2's complement to the least significant bit of the partial product data are performed. is necessary. In the positive partial product data, the bit having the logical value "0" is added to the least significant bit. In the following description, a bit having a logical value "1" or "0" to be added to the least significant bit of the partial product data is called a complemented bit.

Japanese Unexamined Patent Publication (Kokai) No. 58-56033 discloses an 8-bit.times.8-bit multiplier having a multiplier encoder for realizing a secondary Booth's algorithm and a sign extension omission mechanism. An outline of the operation according to the partial product generation method is shown in FIG. In FIG. 25, X [0]
˜X [7] represents 8 bits of the multiplicand, Y [0] to Y [7] represent 8 bits of the multiplier, and M [0] to M [15] represent 16 bits of the product. The first input of the adder is the first partial product data P0 [0] to P0 generated using the first part (the lowest part) of the coded output of the multiplier encoder and the multiplicand.
[7] (bit positions M [0] to M [7]) and the inversion bit IS0 of the sign of the first partial product (bit position M [8]). The second input of the adder is a second portion generated using the second portion of the coded output of the multiplier encoder and the multiplicand.
Partial product data P1 [0] to P1 [7] (bit position M [2] to
M [9]), the inversion bit IS1 of the sign of the second partial product (bit position M [10]), and the complementation bit BC0 (bit position M) to be added to the least significant bit of the first partial product data.
[0]) and. The third input of the adder is the third partial product data P2 [0] to P2 [7] (bit position M [4]) generated using the third part of the coded output of the multiplier encoder and the multiplicand. ~ M [11]), the inversion bit IS2 of the sign of the third partial product (bit position M [12]), and the complemented bit BC1 to be added to the least significant bit of the second partial product data.
(Bit position M [2]). The fourth input of the adder is the fourth partial product data P3 [0] to P3 [7] (bits) generated using the fourth part (most significant part) of the coded output of the multiplier encoder and the multiplicand. Positions M [6] to M [1
3]), the inversion bit IS3 of the sign of the fourth partial product (bit position M [14]), and the complemented bit BC2 (bit position M [4]) to be added to the least significant bit of the third partial product data. )
It is composed of The fifth input of the adder is the bit position M
[8], M [9], M [11], M [13], M [15] 5 logical value "1" bits and the least significant bit of the 4th partial product data should be added Complement bit BC3 (bit position M [6]
). The inversion bits IS0 to IS3 of the signs of the first to fourth partial products and the five bits of the logical value "1" for carry propagation are bits for omitting the sign extension of each partial product. Is. The complement bit BC3 is a bit included in the most significant part of the coded output of the multiplier encoder, and is a bit for making the fourth partial product data 2's complement, that is, the most significant partial product complement bit. Is. Then, by adding the first to fifth inputs, 16-bit products M [0] to M [15] in 2's complement format are obtained.

[0005]

The above-mentioned conventional 8 bits ×
The 8-bit multiplier required a 5-input adder.
That is, there is a problem that the load on the adder cannot be reduced sufficiently because of only some of the bit positions M [6] and M [8]. In addition, the time required for the encoding process of the multiplier is an idle time on the multiplicand side.

An object of the present invention is to effectively utilize the idle time on the multiplicand side generated during the encoding process of the multiplier, and reduce the number of inputs of the adder for adding the partial products in the multiplier. It is in.

Another object of the present invention is to provide a product-sum calculation device in which the number of inputs of an adder is reduced by using the multiplication device of the present invention.

[0008]

[Means for Solving the Problems] Conventional 8 bits × 8
Of the 6 bits forming the fifth input of the adder in the bit multiplier, bit positions M [8], M [9], M [11],
The five logical "1" bits of M [13], M [15] can be easily moved into the first to fourth inputs of the adder. The present invention has the same effect as the addition of the most significant partial product complement bit BC3 to the bit position M [6], and the complement data and carry obtained by converting the lower bit of the multiplicand to 2 in the complement circuit. And are to be achieved in the first to fourth inputs of the adder. That is, conventionally, the most significant partial product complement bit BC for the fourth partial product data is used.
While the addition of 3 is performed in the adder, in the present invention, the complement data is obtained by adding 1 to the inverted data of the lower bit of the multiplicand in the complement circuit, and the most significant partial product is obtained. When the logical value of the complement bit BC3 is “1”,
The lower bit of the fourth partial product data is replaced with the complementary data, and the carry effect of the complement circuit on the upper bit of the fourth partial product data is achieved in the first and second inputs of the adder. . This reduces the number of inputs to the adder. The complementation process for obtaining the complement data and the carry is executed by utilizing the free time on the multiplicand side that occurs during the coding process of the multiplier.

More specifically, the multiplication device of the present invention is
In order to achieve the above object, a multiplier encoder for encoding a multiplier and a complement of 2 by complementing the low order bit of the multiplicand and adding 1 to output complement data and carry are provided. A complement circuit, a partial product generating means for generating a plurality of partial products using the coded output of the multiplier encoder, the multiplicand, the complement data output from the complement circuit and the carry, and the partial product generating means. In addition, a configuration including an adder for adding a plurality of partial products is adopted.

The partial product generating means is composed of at least the following selection circuit and first to third type partial product generators. That is, the selection circuit selects either the lower bit of the multiplicand or the complement data output by the complement circuit according to the partial product complemented bit in the most significant part of the coded output of the multiplier encoder. Circuit.
The first-type partial product generator generates a first-type partial product data by using a part of the coded output of the multiplier encoder and the multiplicand, and a partial product including the first-type partial product data. Is supplied to the adder. The second type partial product generator uses the other part of the encoded output of the multiplier encoder and the multiplicand to generate a second product.
Type partial product data is generated, and the carry output by the complement circuit is added to the upper bit position of the second type partial product data, and the carry is added to the second type partial product data. Supply the partial product to the adder. The third type partial product generator uses the most significant part of the encoded output of the multiplier encoder and the upper bits of the multiplicand to output the upper bits of the third type partial product data to the encoded output of the multiplier encoder. Of the third type partial product data are generated by using the uppermost part of the above and the output data of the selection circuit, and the partial product including the third type partial product data is supplied to the adder. To do.

According to the above-described multiplication device of the present invention, since the multiplicand is complemented in parallel with the multiplier coding process, unless the number of bits to be complemented of the multiplicand is too large.
This is convenient because the time required for the encoding process of the multiplier and the time required for the complementing process of the multiplicand are balanced. When the complement data output by the complement circuit is selected by the selection circuit, a carry occurs when the lower bits of the third type partial product data are generated. This carry is generated by the second type partial product data. It is reflected as a carry added to the high-order bit position.

A plurality of partial products in which the first multiplicand is XA and the first multiplier is YA are obtained by the multiplication device of the present invention, and the second multiplicand is XB and the second multiplier is YB. If the partial products of are obtained by a multiplier having the same configuration and all the partial products are added by the multi-input adder, the first product X
Sum of A × YA and second product XB × YB, that is, product sum U
It is possible to realize an arithmetic unit for reducing the number of inputs of the adder for calculating However, the multiplier and multiplicand XA, YA, X
If both B and YB are 8 bits, an adder input including partial product data generated by using the code most significant part of the first multiplier YA and the first multiplicand XA, and
A vacancy occurs at each bit position U [5] between the most significant part of the code of the multiplier YB and the adder input containing the partial product data generated using the second multiplicand XB. The product-sum calculation apparatus of the present invention utilizes the two vacant positions at the bit position U [5] to store the most significant partial product complementation bit of the second product XB × YB at the bit position U [6]. This is to achieve the same effect as the addition.

More specifically, the product-sum calculation apparatus of the present invention comprises a first multiplier encoder for coding the first multiplier YA and a second multiplier encoder for coding the second multiplier YB.
Of the first multiplicand XA, a low-order bit of the first multiplicand XA is bit-inverted, and 1 is added to form a two's complement to output complement data and carry. First partial product generating means for generating a plurality of partial products using the coded output, the coded output of the second multiplier encoder, the first multiplicand XA, the complement data output from the complement circuit, and the carry. And a second partial product generating means for generating a plurality of partial products using the coded output of the second multiplier encoder and the second multiplicand XB, and the first partial product generating means. This configuration employs a configuration including an adder for adding a plurality of partial products and a plurality of partial products generated by the second partial product generating means.

The first partial product generating means comprises at least the following selection circuit and first to third type partial product generators. That is, the selection circuit selects the lower bit of the first multiplicand XA and the complement data output from the complement circuit according to the partial product complemented bit in the uppermost part of the coded output of the first multiplier encoder. This is a circuit for selecting either one. The first type partial product generator is
Generating a first type partial product data using a portion of the encoded output of the first multiplier encoder and the first multiplicand XA;
The partial product including the partial product data of the first type is supplied to the adder. The second type partial product generator uses the other part of the coded output of the first multiplier encoder and the first multiplicand XA to generate the second type partial product data and outputs the complementary circuit of the complement circuit. The carry to be output is added to the upper bit position of the second type partial product data, and the partial product including the second type partial product data to which the carry is added is supplied to the adder. A third type partial product generator uses the most significant portion of the coded output of the first multiplier encoder and the high order bits of the first multiplicand XA to generate a third product.
The upper bits of the partial product data of the type are respectively assigned to the lower bits of the partial product data of the third type by using the most significant part of the encoded output of the first multiplier encoder and the output data of the selection circuit. Generate and add a partial product complement bit in the most significant part of the encoded output of the second multiplier encoder to the lower bit position of the third type partial product data, and the partial product complement bit is added The partial product including the third type partial product data is supplied to the adder. The second
The partial product generating means is composed of at least the following fourth and fifth type partial product generators. That is, the fourth type partial product generator generates the fourth type partial product data by using a part of the coded output of the second multiplier encoder and the second multiplicand XB, and the fourth type partial product data is generated. The partial product including the partial product data of is supplied to the adder. The fifth type partial product generator generates a fifth type partial product data by using the uppermost part of the coded output of the second multiplier encoder and the second multiplicand XB, and the second multiplier Fifth type partial product data in which the partial product complement bit in the most significant part of the encoded output of the encoder is added to the lower bit position of the fifth type partial product data, and the partial product complement bit is added Is supplied to the adder.

According to the above product-sum calculation apparatus of the present invention,
The partial product complemented bits in the most significant part of the coded output of the multiplier encoder are doubled in the lower bit position of the third type partial product data and the lower bit position of the fifth type partial product data. Is added. This reduces the number of inputs to the adder.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Specific examples of a multiplication device and a product-sum calculation device according to the present invention will be described below with reference to the drawings.

FIG. 1 shows a product M in which the multiplicand is X and the multiplier is Y.
1 shows a schematic configuration example of an 8-bit × 8-bit multiplication device according to the present invention for calculating The multiplication device of FIG.
A multiplication device employing a second-order Booth algorithm and omission of sign extension, comprising a multiplier encoder 101, a complement circuit 102, a selection circuit 103, and first to fourth partial product generators 110 to 113. , And a multi-input adder 104.

The multiplier encoder 101 encodes the multiplier Y according to the quadratic Booth's algorithm and provides a coded output with first (least significant), second, third and fourth (most significant) portions. To do.

The complement circuit 102 bit-inverts the lower 5 bit data of the multiplicand X and adds 1 to obtain 2
Is complemented to output 5-bit complement data (IX + 1) and carry. Here, "I" means a bit inversion operation.

The selection circuit 103 is a multiplier encoder 101.
Depending on the partial product complemented bit in the fourth part (most significant part) of the coded output of, i.e., the most significant partial product complemented bit, the lower 5 bits of the multiplicand X and the complement circuit 1
One of the 5-bit complement data output by 02 is selected. If the logical value of the most significant partial product complement bit is "0", the lower 5 bit data of the multiplicand X,
If the logical value of the most significant partial product complement bit is "1", the 5-bit complement data output from the complement circuit 102 is selected.

The first to fourth partial product generators 110 to 113
Are the first (lowest) partial product data P0 and the second
Partial product data P1, third partial product data P2, fourth
And (top) partial product data P3.
Of these, the first partial product generator 110 is the first part (the lowest part) of the encoded output of the multiplier encoder 101.
And the multiplicand X are used to generate the first partial product data P0, and the complemented bit to be added to the least significant bit of the first partial product data P0 is added to the lower bit position of the second partial product data P1. , And the sign bit of the first partial product, its inversion bit, and the complemented bit reflecting the most significant partial product complemented bit are added to the upper bit positions of the first partial product data P0. The second partial product generator 111 generates the second partial product data P1 using the second part of the coded output of the multiplier encoder 101 and the multiplicand X, and outputs the least significant bit of the second partial product data P1. To the lower bit position of the third partial product data P2, and the inverted bit of the sign of the second partial product and the complemented bit reflecting the carry output from the complement circuit 102. Is added to the upper bit position of the second partial product data P1. The third partial product generator 112 uses the third part of the encoded output of the multiplier encoder 101 and the multiplicand X to generate third partial product data P.
2 is generated, the complemented bit to be added to the least significant bit of the third partial product data P2 is added to the lower bit position of the fourth partial product data P3, and the inverted bit of the sign of the third partial product, The bit of logical value "1" and the third partial product data P
It is added to the high-order bit position of 2. Fourth partial product generator 1
13 uses the fourth part (most significant part) of the encoded output of the multiplier encoder 101 and the upper 3 bits of the multiplicand X to generate the upper 3 bits of the fourth partial product data P3, and the multiplier encoder The fourth part (uppermost part) of the coded output of 101 and the output data of the selection circuit 103 are used to generate the lower 5 bits of the fourth partial product data P3, and the sign of the fourth partial product. And the bit having the logical value "1" are added to the upper bit position of the fourth partial product data P3.

The multi-input adder 104 is an adder for adding the outputs of the first to fourth partial product generators 110 to 113 and outputting the product M in the two's complement form. Wallace) tree circuit and a carry propagation adder (CPA).

FIG. 2 shows the internal structure of the multiplier encoder 101. The multiplier encoder 101 of FIG. 2 is composed of four Booth encoders BE. Each booth encoder BE has 8 bits Y [0] to Y that form a multiplier Y.
3 bits of [7], that is, Y [i * 2 + 1], Y [i * 2]
, Y [i * 2-1] is input. Here, “*” means multiplication, i is 0, 1, 2 or 3, and Y [−1] = “0”
It is. BCP of the coded output shown in FIG.
[0] to BCP [3] are complemented bits to be added to the least significant bit of each partial product data. BCP [3] is the most significant partial product complement bit described above.

FIG. 3 shows the complement circuit 102 and the selection circuit 10.
3 is shown in detail. Complement circuit (COMP) 102
Is a two's complement by bit-reversing the lower 5 bit data X [0] to X [4] of the multiplicand X and adding 1 to obtain 5's complement.
Bit complement data XC [0] to XC [4] and carry XC
Outputs [5]. The selection circuit (SEL) 103, in accordance with the most significant partial product complementation bit BCP [3], the lower 5 bits data X [0] to X [4] of the multiplicand and the 5 bits complement data XC [0] to Either one of XC [4] is output as the selected data XS [0] to XS [4].

FIGS. 4A and 4B show the internal structure of the first partial product generator 110, and FIGS. 5A and 5B show the internal structure of the second partial product generator 111. 6 (a) and 6 (b) show the internal structure of the third partial product generator 112.
(A) and (b) have shown the internal structure of the 4th partial product generator 113, respectively. First to fourth partial product generators 1
10 to 113 are seven types of unit partial product generators PPG1 to PPG1.
It is composed of a combination of PPG7. S3C and IS3C shown in FIG. 4A are the complemented bit generated from the most significant partial product complemented bit BCP [3] and its inverted bit. C3 [0] shown in FIG. 5A is the most significant partial product complement bit BCP [3], the carry XC [5] of the complement circuit 102, and the most significant bit of the output data of the selection circuit 103. It is a complemented bit generated from XS [4].
Further, C3 [1] shown in FIG. 5A is the most significant partial product complement bit BCP [3] and the carry X of the complement circuit 102.
It is a complemented bit generated from C [5].

FIG. 8 shows the internal structure of each Booth encoder BE, and FIG. 9 shows the truth table of each Booth encoder BE. X [7: 0] in FIG. 9 is a shorthand notation that means 8 bits X [0] to X [7] forming the multiplicand X.
"BX1 =" 1 "" means that a multiple of the multiplicand X should be generated as a partial product, "BX2 =" 1 "" means that a multiple of the multiplicand X should be generated as a partial product, and "BC ="
Each "1" indicates that a negative partial product should be generated.

FIG. 10 shows the internal structure of the complement circuit COMP.
FIG. 11 shows the internal configuration of the selection circuit SEL as shown in FIGS.
Indicate the internal configurations of the first to seventh unit partial product generators PPG1 to PPG7, respectively. Detailed description of each configuration is omitted.

FIG. 19 shows a partial product generation method in the multiplication device of FIG. In FIG. 19, the adder 104
The first input of is the first partial product data P0 [0] to P0 [7]
(Bit positions M [0] to M [7]), the sign bit S0 of the first partial product (bit positions M [8] and M [9]), and its inversion bit IS0 (bit position M [10]). And the complemented bit S3 generated from the most significant partial product complemented bit BCP [3]
C (bit position M [12]) and its inverted bit IS3C
(Bit position M [11]). The second input of the adder 104 is the second partial product data P1 [0] to P1 [7] (bit positions M [2] to M [9]) and the inverted bit IS1 (bit of the sign of the second partial product). Position M [10]) and complement circuit (CO
MP) 102 carry XC [5] generated complemented bits C3 [0], C3 [1] (respectively bit positions M [11],
M [12]) and the complemented bit BC0 (bit position M [0]) to be added to the least significant bit of the first partial product data. The third input of the adder 104 is the third partial product data P2 [0] to P2 [7] (bit positions M [4] to M [11]).
, The inversion bit IS2 of the sign of the third partial product (bit position M [12]), and the bit of the logical value "1" (bit position M [1
3]) and the complementary bit BC1 (bit position M [2]) to be added to the least significant bit of the second partial product data. The fourth input of the adder 104 is the fourth partial product data P3 [0] to P3 [7] (bit positions M [6] to M [13]),
Inversion bit IS3 of the sign of the fourth partial product (bit position M [1
4]) and the bit of logical value “1” (bit position M [15])
And the complemented bit BC2 (bit position M [4]) to be added to the least significant bit of the third partial product data. 4 bits S3C, IS3C, C3 [1], C3
[0] is a bit added for converting the higher-order 3-bit data P3 [5] to P3 [7] of the fourth partial product data to 2's complement. Incidentally, if necessary (if the logical value of the most significant partial product complementation bit BCP [3] is "1"), the complement circuit (COMP) 102 complements the two-complement 5-bit complement data XC [0. ] To XC [4] are used as the lower 5 bit data P3 [0] to P3 [4] of the fourth partial product data. Then, the first to fourth inputs are added by the adder 104 to obtain a 16-bit product M of 2's complement format.
[0] to M [15] are required.

FIG. 20 shows the i + 1th partial product (0≤i≤2),
That is, FIG. 21 shows a truth table relating to the generation of the first (lowest), second and third partial products, and FIG. 21 shows a truth table relating to the generation of the fourth (top) partial product. here,"*"
Means multiplication, “I” means bit inversion operation, and “<< 1” means 1-bit left shift operation (double operation). Y [-1] is always the logical value "0". Pi [7: 0]
, P3 [7: 6], P3 [4: 0], etc. are the same abbreviations as the multiplicand X [7: 0] in FIG.

According to FIG. 20, for example, Y [3] =
If “0”, Y [2] = “0”, and Y [1] = “1”,
The partial product to be generated is a multiple of the multiplicand X [7: 0]. At this time, the second partial product generator 111 sets the most significant bit X [7] of the multiplicand in the sign bit S1 of the second partial product (actually, the inverted bit IS1 of the sign of the second partial product).
Is set to the most significant inversion bit IX [7] of the multiplicand),
The multiplicand X [7: 0] is set in the second partial product data P1 [7: 0], and the logical value “0” is set in the complemented bit BC1 to be added to the least significant bit of the second partial product data. It Further, Y [3] = “1”, Y [2] = “0”, and Y [1] =
If “0”, the partial product to be generated is − of multiplicand X [7: 0].
It is a multiple. At this time, the second partial product generator 111 sets the most significant inversion bit IX [7] of the multiplicand in the sign bit S1 of the second partial product (actually, the inversion bit IS1 of the sign of the second partial product). The most significant bit X [7] of the multiplicand
Is set), inverted data of a multiple of the lower 6-bit data X [6: 0] of the multiplicand is set in the second partial product data P1 [7: 0], and the least significant bit of the second partial product data is set. A logical value "1" is set in the complemented bit BC1 to be added. Note that “FF (hexadecimal number display)” in FIG.
Represents a bit of a logical value "1".

According to FIG. 21, for example, Y [7] =
If “0”, Y [6] = “0”, and Y [5] = “1”,
The partial product to be generated is a multiple of the multiplicand X [7: 0]. At this time, the selection circuit 103 sets the lower 5-bit data X [4: 0] of the multiplicand to the selected data XS [4: 0]. 4th
Partial product generator 113 of the fourth partial product
The most significant bit X [7] of the multiplicand is set (actually, the most inverted bit IX [7] of the multiplicand is set to the inversion bit IS3 of the sign of the fourth partial product), and the fourth partial product data P
Set the multiplicand X [7: 0] to 3 [7: 0]. The first partial product generator 110 outputs a logical value “0” to the complementation bit S3C,
The logical value "1" is set to each of the inversion bits IS3C. The second partial product generator 111 generates a complement bit C3.
The logical value “0” is set to each of [1] and C3 [0]. Further, Y [7] = “1”, Y [6] = “1”, and Y [5] =
If “0”, the partial product to be generated is − of multiplicand X [7: 0].
It is a multiple. At this time, the selection circuit 103 adds the complement data X of the lower 5 bits of the multiplicand to the selected data XS [4: 0].
Set C [4: 0]. The fourth partial product generator 113 sets the most significant inverted bit IX [7] of the multiplicand to the sign bit S3 of the fourth partial product (actually, the inverted bit IS3 of the sign of the fourth partial product is set to the multiplicand). (The most significant bit X [7] is set), the upper 3 bits P3 [7: 5] of the fourth partial product data are set to the upper inverted 3 bits IX [7: 5] of the multiplicand, and the lower part of the fourth partial product data is set. Complement data XC [4: 0] is set in each of 5 bits P3 [4: 0]. The first partial product generator 110 outputs the logical value "0" to the complemented bit S3C and the inverted bit IS thereof.
A logical value "1" is set in each of 3C. The second partial product generator 111 outputs a logical value “0” to the complemented bit C3 [1].
To the complement bit C3 [0] and carry X of the complement circuit 102.
Set C [5] respectively. Note that "3 (1
"Hexadecimal notation)" represents two bits of logical value "1".

As described above, according to the multiplication device of FIG. 1, the same effect as the addition of the most significant partial product complement bit BC3 to the bit position M [6] in the conventional multiplication device can be obtained. Using the complement data XC [4: 0] obtained by converting the 5-bit data X [4: 0] to 2's complement and the carry XC [5], the first to fourth inputs of the adder 104 are input. Since the number of inputs to the adder 104 is reduced, the speeding up of addition is achieved.

Incidentally, the arithmetic unit for the operation X × Y + A is obtained by replacing the adder 104 in FIG. 1 with a 5-input adder.
This can be realized by supplying 16-bit data corresponding to the addend A to the 5-input adder as the fifth input.

Further, the first multiplicand (8 bits) is XA,
First product XA × Y where YA is the first multiplier (8 bits)
The sum of A and a second product XB × YB in which the second multiplicand (8 bits) is XB and the second multiplier (8 bits) is YB;
That is, the product-sum calculation apparatus for calculating the product sum XA × YA + XB × YB is a multi-input adder for adding the constituent elements except the adder 104 in FIG. 1 in duplicate and for adding eight partial products. Can be achieved by adding

FIG. 22 shows another configuration example of the 8-bit / 4-input multiply-accumulate operation apparatus according to the present invention. The product-sum calculation apparatus of FIG. 22 includes a first multiplier encoder 101a and a second multiplier encoder 101a.
Multiplier encoder 101b, complement circuit 102a, selection circuit 103a, and first to third partial product generators 110a
-112a, the 4th partial product generator 213, the 5th-8th partial product generators 310-313, and the multi-input adder 30.
And 4.

The first multiplier encoder 101a encodes the first multiplier YA according to the second order Booth algorithm. The second multiplier encoder 101b is
The second multiplier YB is encoded according to the second order Booth's algorithm. The internal configuration of each of the first and second multiplier encoders 101a and 101b is the same as that of the multiplier encoder 101 in FIG.

The complement circuit 102a bit-inverts the lower 5-bit data of the first multiplicand XA and adds 1 to make it 2's complement, and the 5-bit complement data (IXA).
+1) and carry are output.

The selection circuit 103a is responsive to the partial product complement bit in the most significant part of the coded output of the first multiplier encoder 101a, ie the first most significant partial product complement bit, to produce a first multiplicand. Lower 5 bits data of XA,
One of the 5-bit complement data output from the complement circuit 102a is selected.

The first to fourth partial product generators 110a to 110
2a and 213 generate partial products related to the first product XA × YA, and each of them is the first partial product data P0.
, Second partial product data P1, and third partial product data P2
And the fourth partial product data P3 are generated. The fifth to eighth partial product generators 310 to 313 generate partial products relating to the second product XB × YB, and respectively include fifth partial product data P4 and sixth partial product data P5. , The seventh partial product data P6 and the eighth partial product data P7 are generated. Of these, the first to third partial product generators 110a to 112a
Each of the internal configurations is similar to that of the first to third partial product generators 110 to 112 in FIG. Fourth partial product generator 21
3 uses the most significant part of the encoded output of the first multiplier encoder 101a and the most significant 3 bits of the first multiplicand XA to generate the most significant 3 bits of the fourth partial product data P3; The lowermost 5 bits of the fourth partial product data P3 are generated using the uppermost part of the coded output of the multiplier encoder 101a and the output data of the selection circuit 103a.
Add a partial product complement bit in the most significant part of the coded output of the second multiplier encoder 101b, ie the second most significant partial product complement bit, to the lower bit position of the fourth partial product data P3, and The inversion bit of the sign of the fourth partial product and the bit of the logical value "1" are added to the upper bit position of the fourth partial product data P3. The internal configuration of the fourth partial product generator 213 is the same as the fourth partial product generator 1 of FIG.
It is almost the same as 13.

The fifth partial product generator 310 uses the first part (the lowest part) of the coded output of the second multiplier encoder 101b and the second multiplicand XB to calculate the fifth partial product data P4. To generate a complementary bit to be added to the least significant bit of the fifth partial product data P4,
5, and the sign bit of the fifth partial product and its inverted bit are added to the upper bit position of the fifth partial product data P4. Sixth partial product generator 311
Generates the sixth partial product data P5 using the second part of the encoded output of the second multiplier encoder 101b and the second multiplicand XB, and adds it to the least significant bit of the sixth partial product data P5. The complementary bit to be processed is the seventh partial product data P
6 is added to the lower bit position, and the inverted bit of the sign of the sixth partial product and the bit having the logical value "1" are added to the upper bit position of the sixth partial product data P5. The seventh partial product generator 312 generates the seventh partial product data P6 using the third part of the coded output of the second multiplier encoder 101b and the second multiplicand XB, and outputs the seventh partial product data P6. The complemented bit to be added to the least significant bit of the data P6 is added to the lower bit position of the eighth partial product data P7, and the inverted bit of the sign of the seventh partial product and the bit of logical value "1" are added. It is added to the upper bit position of the seventh partial product data P6. 8th
The partial product generator 113 of the second multiplier encoder 101
The fourth part (top part) of the coded output of b and the second part
And the multiplicand XB of the eighth partial product data P7 is generated, and the complemented bit to be added to the least significant bit of the eighth partial product data P7, that is, the second most significant partial product complemented bit is It is added to the lower bit position of the 8th partial product data P7, and the inverted bit of the sign of the 8th partial product data and the bit of the logical value "1" are added to the higher bit position of the 8th partial product data P7. Fifth to eighth partial product generators 310-3
Reference numeral 13 denotes the seven types of unit partial product generators PPG1 to PP
First and second unit partial product generators PPG of G7
1 and PPG2 are combined.

The multi-input adder 304 includes first to eighth partial product generators 110a to 112a, 213, 310 to 313.
Are added together and the product sum XA × YA + in 2's complement format is added.
This is an adder for outputting XB × YB, and is composed of a Wallace tree circuit and a carry propagation adder (CPA).

FIG. 23 shows a method of generating a partial product relating to the first product XA.times.YA in the product-sum calculation device of FIG. The first to fourth inputs of the adder 304 shown in FIG. 23 are the same as the first to fourth inputs of the adder 104 shown in FIG. However, at the fourth input of the adder 304, the least significant bit P3 [0] of the fourth partial product data and the complemented bit B to be added to the least significant bit of the third partial product data.
The second most significant partial product complementation bit BC7
Is inserted.

FIG. 24 shows a method of generating a partial product relating to the second product XB.times.YB in the product-sum calculation device of FIG. The fifth input of the adder 304 is the fifth partial product data P4.
[0] to P4 [7], the sign bit S4 of the fifth partial product, and its inversion bit IS4. The sixth input of the adder 304 is the sixth partial product data P5 [0] to P5 [7], the inversion bit IS5 of the sign of the sixth partial product, the bit of the logical value "1", and the fifth partial product. Complementary bit BC4 to be added to the least significant bit of data. Adder 30
The seventh input of No. 4 is the seventh partial product data P6 [0] to P6 [7]
, The inversion bit IS6 of the sign of the seventh partial product, the bit of the logical value "1", and the complementation bit BC5 to be added to the least significant bit of the sixth partial product data. The eighth input of the adder 304 is the eighth partial product data P7 [0]
P7 [7] and the inversion bit IS7 of the sign of the eighth partial product,
It is composed of a bit having a logical value "1", a complemented bit BC6 to be added to the least significant bit of the seventh partial product data, and a second most significant partial product complemented bit BC7. At the eighth input of adder 304, the second most significant partial product complement bit BC7 is the least significant bit P7 of the eighth partial product data.
It is inserted between [0] and the complemented bit BC6 to be added to the least significant bit of the seventh partial product data. And
By adding the first to eighth inputs by the adder 304, the 16-bit product sum XA × YA + XB in the 2's complement format
XYB is required.

The sum-of-products calculation device of FIG. 22 calculates the first to third partial products according to the truth table of FIG. 20, the fourth partial product according to the truth table of FIG. 21, and the fifth part of the truth table of FIG. ~ Is to generate an eighth partial product. Moreover, the complemented bit to be added to the least significant bit P7 [0] of the eighth partial product data, that is, the second most significant partial product complemented bit BC7.
Is added to the position of 1 bit lower than the least significant bit P7 [0] of the eighth partial product data so that the second most significant partial product complement bit BC7 is added to the least significant bit of the eighth partial product data. It has the same effect as adding to the position of bit P7 [0]. Thus, the 8-input adder 304 achieves high-speed addition.

The details of the multiplication device of FIG. 1 and the product-sum calculation device of FIG. 22 according to the present invention have been described above.

Although the fourth partial product generator 113 and the selection circuit 103 are separate circuit blocks in the multiplication apparatus of FIG. 1, five unit partial products in the fourth partial product generator 113 are included. The generator PPG3 may have the function of the selection circuit 103. The fourth partial generator 2 of the product-sum calculation apparatus of FIG.
The same applies to 13 and the selection circuit 103a.

Also, the multiplier encoder 1 of the multiplication device of FIG.
Although 01 uses the second-order Booth's algorithm, a third-order or higher-order Booth's algorithm or another multiplier coding algorithm may be used instead. FIG.
First and second multiplier encoders 10 of the product sum operation device of 2
The same applies to 1a and 101b.

In the multiplication device of FIG. 1, the complemented bit IS3C in place of the complemented bit to be added to the least significant bit P3 [0] (bit position M [6]) of the fourth partial product data is added to the adder 104. The complement circuit 102 adds the lower 5-bit data X [4 of the 8-bit multiplicand to the bit position M [11] of the first input (this is the empty bit position closest to the bit position M [6]). : 0] is made to be two's complement.
However, if the additional bit position of the complement bit IS3C is changed, the complement bit number of the multiplicand in the complement circuit 102 is changed accordingly, and the complement bit C3 [0] based on the carry of the complement circuit 102 is changed. , C3 [1] additional bit positions are changed. The 8-bit multiplicand X [7: 0] may be wholly complemented with two. The bit numbers of the multiplicand X and the multiplier Y can be arbitrarily changed. Similar changes can be made in the product-sum calculation apparatus of FIG.

[0049]

As described above, according to the multiplication device of the present invention, the same effect as the addition of the most significant partial product complementation bit to the same bit position as the least significant bit of the most significant partial product data can be obtained. Since it is decided to achieve in each partial product data by using the complement data and the carry obtained by converting the lower bit of the multiplicand to 2's complement, the multiplicand side generated at the time of the encoding process of the multiplier The free time can be effectively used to reduce the number of inputs to the adder for adding partial products.

Further, according to the product-sum calculation apparatus of the present invention, since the multiplication apparatus of the present invention is used for calculating the first product XA.times.YA, the number of inputs of the adder can be reduced. Moreover, since the double addition of the most significant partial product complementation bit relating to the second product XB × YB is adopted, the number of inputs of the adder relating to the second product is reduced, and the second product is calculated. The configuration of the multiplication device for is simplified.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram showing a configuration example of a multiplication device according to the present invention.

FIG. 2 is a block diagram showing an internal configuration of a multiplier encoder in FIG.

3 is a block diagram showing details of a complement circuit and a selection circuit in FIG.

4 (a) and (b) are block diagrams showing an internal configuration of a first partial product generator in FIG.

5 (a) and 5 (b) are block diagrams showing an internal configuration of a second partial product generator in FIG.

6 (a) and 6 (b) are block diagrams showing an internal configuration of a third partial product generator in FIG.

7 (a) and (b) are block diagrams showing the internal configuration of a fourth partial product generator in FIG.

8 is a circuit diagram showing an internal configuration of each Booth encoder in FIG. 2. FIG.

9 is a diagram showing a truth table of the Booth encoder shown in FIG. 8;

10 is a circuit diagram showing an internal configuration of a complement circuit in FIG.

11 is a circuit diagram showing an internal configuration of a selection circuit in FIG.

FIG. 12 is a circuit diagram showing an internal configuration of a first unit partial product generator.

FIG. 13 is a circuit diagram showing an internal configuration of a second unit partial product generator.

FIG. 14 is a circuit diagram showing an internal configuration of a third unit partial product generator.

FIG. 15 is a circuit diagram showing an internal configuration of a fourth unit partial product generator.

FIG. 16 is a circuit diagram showing an internal configuration of a fifth unit partial product generator.

FIG. 17 is a circuit diagram showing an internal configuration of a sixth unit partial product generator.

FIG. 18 is a circuit diagram showing an internal configuration of a seventh unit partial product generator.

19 is a diagram showing a partial product generation method in the multiplication device in FIG. 1. FIG.

20 is a diagram showing a truth table relating to the generation of first, second and third partial products of the multiplication device of FIG. 1;

21 is a diagram showing a truth table relating to the generation of a fourth partial product in the multiplication device shown in FIG. 1;

FIG. 22 is a schematic block diagram showing a configuration example of a product-sum calculation apparatus according to the present invention.

23 is a diagram showing a method of generating a partial product relating to a first product in the product-sum calculation apparatus of FIG. 22.

FIG. 24 is a diagram showing a method of generating a partial product relating to a second product in the product-sum calculation apparatus of FIG. 22.

FIG. 25 is a diagram showing a partial product generation method in a conventional multiplication device.

[Explanation of symbols]

 101, 101a, 101b Multiplier encoder 102, 102a Complement circuit (COMP) 103, 103a Selection circuit (SEL) 104, 304 Multi-input adder 110-113 Partial product generator 110a-112a, 213 Partial product generator 310-313 Part Product generator

Claims (4)

[Claims] 1. A multiplier encoder for encoding a multiplier, and a complement circuit for converting two bits of a lower bit of a multiplicand and adding 1 to form 2's complement, and outputting complement data and a carry. A coded output of the multiplier encoder, the multiplicand,
Partial product generating means for generating a plurality of partial products using the complement data and carry carried by the complement circuit; and an adder for adding the plurality of partial products generated by the partial product generating means. And a multiplication device. 2. The multiplication device according to claim 1, wherein the partial product generation means sets a lower bit of the multiplicand according to a partial product complementation bit in a most significant part of the coded output of the multiplier encoder. , A selection circuit for selecting one of the complement data output from the complement circuit, a part of the coded output of the multiplier encoder, and the multiplicand to generate partial product data of the first type A partial product generator of the first type for supplying a partial product containing the partial product data of the first type to the adder, another part of the coded output of the multiplier encoder, and the multiplicand Is used to generate the second type partial product data, and the carry output from the complement circuit is added to the high-order bit position of the second type partial product data, and the carry is added to the second The partial product containing the partial product data of the type A second-type partial product generator for supplying to the adder, a most significant part of the coded output of the multiplier encoder, and the high-order bit of the multiplicand. Using the most significant bit of the coded output of the multiplier encoder and the output data of the selection circuit, the least significant bit of the partial product data of the third type is generated, and the high order bit of the third type is generated. And a third type partial product generator for supplying a partial product containing partial product data to the adder. 3. The first multiplicand is XA, and the first multiplier is YA.
And a second product XB × YB in which the second multiplicand is XB and the second multiplier is YB. A first multiplier encoder for encoding the first multiplier YA, a second multiplier encoder for encoding the second multiplier YB, and bit inversion of the lower bits of the first multiplicand XA. 1
2's complement by adding, and a complement circuit for outputting complement data and carry; a coded output of the first multiplier encoder;
First partial product generating means for generating a plurality of partial products using the coded output of the multiplier encoder, the first multiplicand XA, and the complement data and the carry output from the complement circuit, A coded output of the second multiplier encoder;
Second partial product generating means for generating a plurality of partial products by using the multiplicand XB of, and a plurality of partial products generated by the first partial product generating means, and a second partial product generation And a plurality of partial products generated by the means, and an adder for adding the partial products. 4. The product-sum calculation apparatus according to claim 3, wherein the first partial product generating means is responsive to a partial product complement bit in the most significant part of the coded output of the first multiplier encoder. A selection circuit for selecting one of the lower bit of the first multiplicand XA and the complement data output from the complement circuit, and a part of the coded output of the first multiplier encoder, A first type partial product generation for generating a first type partial product data by using the first multiplicand XA and supplying a partial product including the first type partial product data to the adder Unit, another part of the coded output of the first multiplier encoder, and the first multiplicand XA to generate second type partial product data, and a carry output from the complement circuit. To the upper bit position of the second type partial product data A second type partial product generator for supplying the adder with a partial product containing the second type partial product data to which the carry is added; and a maximum of the coded output of the first multiplier encoder. A third part is formed using the upper part and the upper bits of the first multiplicand XA.
The upper bits of the partial product data of the type are respectively generated by using the uppermost part of the coded output of the first multiplier encoder and the output data of the selection circuit to generate the lower bits of the partial product data of the third type. And a partial product complement bit in the most significant part of the coded output of the second multiplier encoder is added to the lower bit position of the partial product data of the third type, and the partial product complement bit is added. A third partial product generator for supplying a partial product including the generated third partial product data to the adder, wherein the second partial product generating means includes the second multiplier. A fourth type partial product data is generated by using a part of the encoded output of the encoder and the second multiplicand XB, and a partial product including the fourth type partial product data is supplied to the adder. A partial product generator of the fourth type for A fifth type of partial product data is generated using the uppermost portion of the encoded output of the encoder and the second multiplicand XB, and among the uppermost portion of the encoded output of the second multiplier encoder A partial product complement bit is added to the lower bit position of the fifth type partial product data, and a partial product including the fifth type partial product data with the partial product complement bit added is supplied to the adder. And a fifth type partial product generator for performing the multiplication.