CN112631546A - KO-8 algorithm-based high-performance modular multiplier - Google Patents
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Abstract
The invention discloses a high-performance modular multiplier based on a KO-8 algorithm, which comprises the steps of calculating the product T of input a and input b by utilizing the KO-8 algorithm; wherein T _ l is the low 256 bits of T; calculating a product m of T _ l and invp, and only calculating the lower 256 m _ l of m by improving the KO-8 algorithm; calculating the product c of m _ l and p by using a KO-8 algorithm; and adding the calculated c and T, judging whether the calculated c is larger than p, and if the calculated c is larger than p, outputting res-c, and if the calculated c is not larger than p, outputting res-c. The invention is based on the extended KO-8 algorithm, processes the algorithm to only calculate the low digit number of the required product, and ignores the high digit number of the product, thereby meeting the requirement of the function of the modular multiplier and achieving the purpose of reducing the power consumption. The multiplier reduces the number of digits of operands and the like at the cost of an adder, thereby greatly reducing the hardware overhead, reducing the area power consumption, meeting the requirement of optimizing the performance of the modular multiplier and improving the advantages of the modular multiplier in area and power consumption.
Description
Technical Field
The invention relates to a modular multiplier, in particular to a high-performance modular multiplier based on a KO-8 algorithm.
Background
Since Hendrik Lenstra given the integer factorization algorithm based on elliptic curves in 1984, the use of elliptic curves in cryptography and computer numerical theory has been greatly developed.
The performance of the modular multiplier is the bottleneck of point multiplication operation on an elliptic curve, wherein large integer multiplication is a basic unit in the modular multiplier, the performance of the modular multiplier is determined by the performance of the large number multiplier, and a large number multiplication unit for realizing fast operation is one of the problems which are urgently needed to be solved in ECC. When large number multiplication is implemented, sometimes we do not need to get all the bits of the multiplier product, i.e. there is redundancy of the input data, which reduces the speed of the modular multiplier to some extent, increasing area and power consumption.
The architecture of the ECC algorithm can be divided into four layers: an external interface layer, an ECC top protocol layer, an ECC point operation layer and a finite field operation layer. The top protocol layer of ECC is the highest layer: this level will complete various operations according to the operation rules prescribed by the elliptic curve algorithm application or the cryptographic protocol, achieving the protocol goal. The ECC top layer protocol comprises: ECC digital signature, ECC key exchange protocol, ECC encryption mechanism and the like; the ECC point operation layer comprises scalar multiplication operation on the elliptic curve, and the scalar multiplication is decomposed into point addition and point doubling operation implementation on a series of elliptic curves. The scalar multiplication algorithm directly influences the operation cycle number and the key path of scalar multiplication; and the finite field operation layer is positioned at the lowest layer of the ECC hierarchy: all the calculations of the algorithm are finally decomposed into basic arithmetic operations on a finite field, and the finite field operations are realized by converting into binary streams. In hardware design, the design scheme of domain operation greatly affects the length of a critical path, and further affects the dominant frequency of a system.
In summary, reducing the power consumption of the ECC algorithm improves the performance, and the main problem is to reduce the power consumption of the modular multiplication operation. In the elliptic curve-based cryptographic algorithm, the modular multiplication accounts for about 90% of the overall Power consumption of the flip-flop, for example, in the ECDH algorithm, the Switch Power of the modular multiplier accounts for 98% of the overall ECC module, and in the ECDSA _ verify algorithm, the Switch Power of the modular multiplier accounts for 92% of the overall ECC module. Therefore, the low-power-consumption high-performance design of the modular multiplier plays a decisive role in improving the energy efficiency ratio of the whole ECC module in the working state.
Disclosure of Invention
The purpose of the invention is as follows: aiming at the problems, the invention provides a high-performance modular multiplier based on a KO-8 algorithm, which designs a Montgomery modular multiplier realizing a four-stage production line, wherein the KO-8 multiplier can be improved according to the requirement of a data result in subsequent work, only one part of data bits is selected for partial product operation, and finally the final required result is obtained.
The technical scheme is as follows: in order to realize the purpose of the invention, the technical scheme adopted by the invention is as follows: a KO-8 algorithm-based high-performance modular multiplier comprises the following steps:
(1) calculating the product T of the inputs a and b by using a KO-8 algorithm; wherein T _ l is the low 256 bits of T;
T＝mul_ko8(a，b)，T_l＝T[lowbit]
(2) calculating a product m of T _ l and invp, and only calculating the lower 256 m _ l of m by improving the KO-8 algorithm;
m_l＝mul_ko8_lowbit(T_l，invp)
(3) calculating the product c of m _ l and p by using a KO-8 algorithm;
c＝mul_ko8(m_l，p)
(4) and (3) adding the c calculated in the step (3) and the T calculated in the step (1) to judge whether the sum is larger than p, and if the sum is larger than p, outputting res as c-p, and if the sum is not larger than p, outputting res as c.
Further, in the step (1), the KO-8 algorithm uses 36 32-bit multipliers to implement the calculation module.
Further, in the step (2), the improved KO-8 algorithm only calculates the lower 256 bits of the output result, and the calculation module is implemented by using 24 32-bit multipliers.
Further, the KO-8 algorithm realizes 8N-bit multiplication through 36N-bit multipliers, data are divided and summed after entering the multipliers, 36 partial products are calculated, and then the multiplication results of the 36 partial products are calculated through a partial product compression module.
Further, the calculation process of the KO-8 algorithm:
(1) acquiring a multiplier X and a multiplier Y, and determining the weight of each bit in the multiplier;
x＝x727N+x626N+x525N+x424N+x323N+x222N+x12N+x0
y＝y727N+y626N+y525N+y424N+y323N+y222N+y12N+y0
(2) according to the weight determined in the step (1), multiplying the multiplier and the multiplicand bit by bit to obtain a calculated partial product;
p0＝x0*y0，p1＝x1*y1，……，p7＝x7*y7
p01＝(x0+x1)*(y0+y1)，p02＝(x0+x2)*(y0+y2)
p03＝(x0+x3)*(y0+y3)，p04＝(x0+x4)*(y0+y4)
……
p57＝(x5+x7)*(y5+y7)，p67＝(x6+x7)*(y6+y7)
(3) and (3) compressing the partial products obtained by bit-by-bit multiplication in the step (2) to obtain the final result.
r＝p7*214N+…+(p01-p0-p1)*2N+p0
Further, the calculation process of the KO-8 algorithm is improved:
(1) acquiring a multiplier X and a multiplier Y, and determining the weight of each bit in the multiplier;
x＝x727N+x626N+x525N+x424N+x323N+x222N+x12N+x0
y＝y727N+y626N+y525N+y424N+y323N+y222N+y12N+y0
(2) selectively calculating the digit of the multiplier and the multiplicand according to the weight determined in the step (1) and the digit requirement of the final data result so as to obtain a calculated partial product;
p0＝x0*y0，p1＝x1*y1，……，p7＝x7*y7
p01＝(x0+x1)*(y0+y1)，p02＝(x0+x2)*(y0+y2)
p03＝(x0+x3)*(y0+y3)，p04＝(x0+x4)*(y0+y4)
p05＝(x0+x5)*(y0+y5)，p06＝(x0+x6)*(y0+y6)
p07＝(x0+x7)*(y0+y7)
p12＝(x1+x2)*(y1+y2)，p13＝(x1+x3)*(y1+y3)
p14＝(x1+x4)*(y1+y4)，p15＝(x1+x5)*(y1+y5)
p16＝(x1+x6)*(y1+y6)
p23＝(x2+x3)*(y2+y3)，p24＝(x2+x4)*(y2+y4)
p25＝(x2+x5)*(y2+y5)
p34＝(x3+x4)*(y3+y4)
(3) and (3) compressing the partial products obtained by bit-by-bit multiplication in the step (2) to obtain the final result.
r＝(p34-p3-p4)*27N+(p25-p2-p5)*27N+(p61-p1-p6)*27N
+(p07-p0-p7)*27N+........+p0
Has the advantages that: the design of the invention can not only reduce the complexity and time in the calculation process and reduce the power consumption and the area overhead, but also meet the requirement on the calculation result when optimizing the modular multiplier.
The invention designs an expanded KO-8 multiplier, greatly reduces the number of multipliers in the circuit at the cost of increasing part of addition and subtraction circuits, and greatly reduces the complexity of hardware circuits in the multipliers.
Compared with the prior art, the circuit design is simple, the power consumption area is greatly reduced, the data flux of the circuit is not influenced, and meanwhile, the design of full customization is carried out on each step of calculation aiming at the particularity of the modular multiplier circuit. Through the design of the mode, the calculation result of one-time modular multiplication can be output in each clock period, the data flux is ensured, the customized design is carried out on each stage of calculation, the advantages of the area and the power consumption are ensured, and the performance of the modular multiplier is optimized to a certain extent.
Drawings
FIG. 1 is a flow chart of the KO-8 algorithm based high performance modular multiplier of the present invention;
FIG. 2 is a flow chart of the regular algorithm;
FIG. 3 is a flow chart of the KO algorithm;
FIG. 4 is a flow chart of the KO-8 algorithm;
FIG. 5 is a flow chart of the lowbit KO-8 algorithm;
FIG. 6 is a schematic diagram of the lowbit KO-8 algorithm;
FIG. 7 is a flow chart of the KO-8 multiplier.
Detailed Description
The technical solution of the present invention is further described below with reference to the accompanying drawings and examples.
As shown in FIG. 1, the KO-8 algorithm-based high-performance modular multiplier of the present invention is a four-stage pipeline Montgomery modular multiplier, with inputs of a, b, p, invp, and an output of res. The method comprises the following steps:
(1) calculating the product T of the inputs a and b by using a KO-8 algorithm, wherein T _ l is the low 256 bits of T, and T _ h is the high 256 bits of T;
T＝mul_ko8(a，b)，T_l＝T[lowbit]
(2) calculating a product m of T _ l and invp, wherein only the lower 256 bits of m are used in the subsequent calculation process, so that only the lower 256 bits of m are calculated by further utilizing a KO-8-based algorithm, namely m _ l;
m_l＝mul_ko8_lowbit(T_l，invp)
for a 256-bit Montgomery modular multiplier, there are a total of three 256-bit multiplication calculations, and each 256-bit multiplier can be implemented with 36 32-bit multipliers by the KO-8 algorithm. In the third 256-bit multiplication in the Montgomery modular multiplier, only the low 256-bit of the result of the second multiplication is used, so that the multiplier in the second multiplication can be designed in a full-custom mode, only the low 256-bit of the output result is calculated, and the calculation module can be realized by only 24 32-bit multipliers, thereby further reducing the area and the power consumption of the circuit.
(3) Calculating the product c of m _ l and p by using a KO-8 algorithm;
c＝mul_ko8(m_l，p)
(4) and (3) adding the c calculated in the step (3) and the T calculated in the step (1) and judging whether the sum is larger than p, if so, outputting res-c, and if not, outputting res-c.
By the design of the invention, the calculation result of one-time modular multiplication can be output in each clock period, the data flux is ensured, and the customized design is carried out on each stage of calculation, thereby ensuring the advantages of area and power consumption.
As shown in fig. 2, the calculation process of the regular algorithm:
(1) acquiring a multiplier X and a multiplier Y, and determining the weight of each bit in the multiplier;
x＝x12N+x0
y＝y 12N+y0
(2) according to the weight determined in the step (1), multiplying the multiplier and the multiplicand bit by bit to obtain a calculated partial product;
p0＝x0*y0，p1＝x1*y1
P01＝(x0+x1)*(y0+y1)
(3) and (3) compressing the partial products obtained by bit-by-bit multiplication in the step (2) to obtain the final result.
r＝p1*22N+p01*2N+p0
As shown in FIG. 3, the calculation procedure of KO algorithm, p in regular multiplier01＝x0*y1+x1*y0And at KO multiplier p01＝(x0+x1)*(y0+y1)-p0-p1. Thus, at the cost of an adder only, when a 2N-bit multiplier is realized, the original 4N-bit multipliers can be reduced into 2N-bit multipliers and 1 (N +1) -bit multiplier, and the (N +1) -bi multiplier can be realized by replacing the N-bit multipliers. The following formula:
a*b＝(a[N]*b[N]*22N)+((a[N]*b[N-1：0]+b[N]*a[N-1：0])*2N)
+a[N-1：0]*b[N-1：0]
the KO multiplier is applied to greatly reduce the hardware overhead when N is large, the more the algorithm is split, the larger the saved area and the power consumption are, and the operation efficiency of the arithmetic core is not influenced.
As shown in FIG. 4, the calculation process of the KO-8 algorithm:
(1) acquiring a multiplier X and a multiplier Y, and determining the weight of each bit in the multiplier;
x＝x727N+x626N+x525N+x424N+x323N+x222N+x12N+x0
y＝y 727N+y 626N+y 525N+y 424N+y 323N+y 222N+y 12N+y0
(2) according to the weight determined in the step (1), multiplying the multiplier and the multiplicand bit by bit to obtain a calculated partial product;
p0＝x0*y0，p1＝x1*y1，……，p7＝x7*y7
p01＝(x0+x1)*(y0+y1)，p02＝(x0+x2)*(y0+y2)
p03＝(x0+x3)*(y0+y3)，p04＝(x0+x4)*(y0+y4)
……
p57＝(x5+x7)*(y5+y7)，p67＝(x6+x7)*(y6+y7)
(3) and (3) compressing the partial products obtained by bit-by-bit multiplication in the step (2) to obtain the final result.
r＝p7*214N+…+(p01-p0-p1)*2N+p0
The invention adopts the KO-8 multiplier, can realize 8N-bit multiplication by 36N-bit multipliers theoretically, but can realize the multiplication only by 64N-bit multipliers under the conventional condition, data is divided and summed after entering the multipliers, then 36 partial products are calculated, and then 36 partial products are calculated through a partial product compression module to calculate the multiplication result.
As shown in FIG. 5, the KO-8 multiplier in the second multiplication of the four-stage pipeline Montgomery modular multiplier is designed in a full-customization manner, so that only low 256 bits of output results are calculated, and the calculation module can be realized by only 24 32-bit multipliers.
Calculation procedure of lowbit KO-8 algorithm:
(1) acquiring a multiplier X and a multiplier Y, and determining the weight of each bit in the multiplier;
x＝x727N+x626N+x525N+x424N+x323N+x222N+x12N+x0
y＝y 727N+y 626N+y 525N+y 424N+y 323N+y 222N+y 12N+y0
(2) selectively calculating the digit of the multiplier and the multiplicand according to the weight determined in the step (1) and the digit requirement of the final data result so as to obtain a calculated partial product;
p0＝x0*y0，p1＝x1*y1，……，p7＝x7*y7
p01＝(x0+x1)*(y0+y1)，p02＝(x0+x2)*(y0+y2)
p03＝(x0+x3)*(y0+y3)，p04＝(x0+x4)*(y0+y4)
p05＝(x0+x5)*(y0+y5)，p06＝(x0+x6)*(y0+y6)
p07＝(x0+x7)*(y0+y7)
p12＝(x1+x2)*(y1+y2)，p13＝(x1+x3)*(y1+y3)
p14＝(x1+x4)*(y1+y4)，p15＝(x1+x5)*(y1+y5)
p16＝(x1+x6)*(y1+y6)
p23＝(x2+x3)*(y2+y3)，p24＝(x2+x4)*(y2+y4)
p25＝(x2+x5)*(y2+y5)
p34＝(x3+x4)*(y3+y4)
(3) and (3) compressing the partial products obtained by bit-by-bit multiplication in the step (2) to obtain the final result.
r＝(p34-p3-p4)*27N+(p25-p2-p5)*27N+(p61-p1-p6)*27N
+(p07-p0-p7)*27N+........+p0
As shown in FIG. 6, the present invention adopts KO-8 based multiplier, the data is divided and summed after entering the multiplier, then 24 partial products with lower bits are calculated, and then the multiplication result is calculated by the partial product compression module for the 24 partial products.
As shown in fig. 7, in the implementation process of the KO-8 multiplier, first, two 8N-bit data are divided into a group every N data according to weights from low to high, and N values of the two data are 1,2,3.. eta.n in sequence; then, the two multipliers are respectively processed according to the requirements of the final result, the number of the data groups before the user is selected, the N values of the selected groups of the two multipliers are ensured to be the same, and the number of the data groups which are not needed is ignored; and calculating the result of each group by adopting KO-8 algorithm according to the selected data and the groups with the same N value in the two multipliers.
The method is based on the KO algorithm, extends the KO algorithm to the KO-8 algorithm, processes the algorithm to only calculate the low digit of the product, and ignores the high digit, thereby achieving the purpose of reducing the power consumption. The KO-8 multiplier designed by the invention reduces the number of bits of operands and the like at the cost of an adder, thereby greatly reducing the hardware overhead, reducing the area power consumption, meeting the requirement of optimizing the performance of the modular multiplier and improving the advantages of the modular multiplier in area and power consumption.
Claims (6)
1. A KO-8 algorithm-based high-performance modular multiplier is characterized by comprising the following steps of:
(1) calculating the product T of the inputs a and b by using a KO-8 algorithm; wherein T _ l is the low 256 bits of T;
T＝mul_ko8(a，b)，T_l＝T[lowbit]
(2) calculating a product m of T _ l and invp, and only calculating the lower 256 m _ l of m by improving the KO-8 algorithm;
m_l＝mul_ko8_lowbit(T_l，invp)
(3) calculating the product c of m _ l and p by using a KO-8 algorithm;
c＝mul_k08(m_l，p)
(4) and (3) adding the c calculated in the step (3) and the T calculated in the step (1) to judge whether the sum is larger than p, and if the sum is larger than p, outputting res as c-p, and if the sum is not larger than p, outputting res as c.
2. The KO-8 algorithm-based high-performance modular multiplier of claim 1, wherein in the step (1), the KO-8 algorithm uses 36 32-bit multipliers to realize the calculation module.
3. The KO-8 algorithm-based high-performance modular multiplier of claim 1, wherein in the step (2), the improved KO-8 algorithm only calculates the lower 256 bits of the output result, and the calculation module is implemented by using 24 32-bit multipliers.
4. The KO-8 algorithm-based high-performance modular multiplier of claim 1, wherein the KO-8 algorithm realizes 8N-bit multiplication through 36N-bit multipliers, data is divided and summed after entering the multipliers, 36 partial products are calculated, and then the 36 partial products are calculated through a partial product compression module to obtain a multiplication result.
5. The KO-8 algorithm-based high-performance modular multiplier of claim 4, wherein the KO-8 algorithm is calculated by:
(1.1) acquiring a multiplier X and a multiplier Y, and determining the weight of each bit in the multiplier;
x＝x727N+x626N+x525N+x424N+x323N+x222N+x12N+x0
y＝y727N+y626N+y525N+y424N+y323N+y222N+y12N+y0
(1.2) according to the weight determined in the step (1.1), multiplying the multiplier and the multiplicand bit by bit to obtain a calculated partial product;
(1.3) compressing the partial products obtained by bit-by-bit multiplication in the step (1.2) to obtain a final result;
r＝p7*214N+…+(p01-p0-p1)*2N+p0。
6. the KO-8 algorithm based high performance modular multiplier of claim 3, wherein the KO-8 algorithm is improved in the calculation process:
(2.1) acquiring a multiplier X and a multiplier Y, and determining the weight of each bit in the multiplier;
x＝x727N+x626N+x525N+x424N+x323N+x222N+x12N+x0
y＝y727N+y626N+y525N+y424N+y323N+y222N+y12N+y0
(2.2) selectively calculating the digit of the multiplier and the multiplicand according to the weight determined in the step (2.1) and the digit requirement of the final data result so as to obtain a calculated partial product;
p0＝x0*y0，p1＝x1*y1，……，p7＝x7*y7
p01＝(x0+x1)*(y0+y1)，p02＝(x0+x2)*(y0+y2)
p03＝(x0+x3)*(y0+y3)，p04＝(x0+x4)*(y0+y4)
p05＝(x0+x5)*(y0+y5)，p06＝(x0+x6)*(y0+y6)
p07＝(x0+x7)*(y0+y7)
p12＝(x1+x2)*(y1+y2)，p13＝(x1+x3)*(y1+y3)
p14＝(x1+x4)*(y1+y4)，p15＝(x1+x5)*(y1+y5)
p16＝(x1+x6)*(y1+y6)
p23＝(x2+x3)*(y2+y3)，p24＝(x2+x4)*(y2+y4)
p25＝(x2+x5)*(y2+y5)
p34＝(x3+x4)*(y3+y4)
(2.3) compressing the partial products obtained by bit-by-bit multiplication in the step (2.2) to obtain a final result;
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