JPH09172359A - Gate circuit for voltage driven semiconductor switching element - Google Patents

Gate circuit for voltage driven semiconductor switching element

Info

Publication number
JPH09172359A
JPH09172359A JP32999295A JP32999295A JPH09172359A JP H09172359 A JPH09172359 A JP H09172359A JP 32999295 A JP32999295 A JP 32999295A JP 32999295 A JP32999295 A JP 32999295A JP H09172359 A JPH09172359 A JP H09172359A
Authority
JP
Japan
Prior art keywords
gate
iegt
voltage
semiconductor switching
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP32999295A
Other languages
Japanese (ja)
Inventor
Hironobu Kin
宏信 金
Katsumi Fukazawa
勝美 深沢
Takeo Koyama
建夫 小山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP32999295A priority Critical patent/JPH09172359A/en
Publication of JPH09172359A publication Critical patent/JPH09172359A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To improve the current balance in a chip by connecting each gate resistor suitable for an on-characteristic and an off-characteristic of a voltage driven semiconductor switching element between a gate drive circuit and a gate terminal respectively. SOLUTION: The voltage drive semiconductor switching element IEGT (SD) is formed by containing plural chips ch1-chn in one package, connecting anodes, cathodes, gates of each chip in common respectively and leading out an anode terminal A, a cathode terminal K and a gate terminal G as external terminals. Then a gate resistor RP whose resistance is suitable for an on-characteristic of the IEGT (SD) is connected between a gate drive circuit 1 and the gate terminal G via a diode DP and a gate resistor RN whose resistance is suitable for an off-characteristic of the IEGT (SD) is connected between the gate drive circuit 1 and the gate terminal G via a diode DN. Thus, the IEGT(SD) is controlled by using the suitable resistor RP (RN) for the ON (OFF) state respectively.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は複数のチップを並列
接続して成る電圧駆動形半導体スイッチング素子(In
jection Enhanced Gate Tra
nsistor)(以下単に、IEGTと記す)のスイ
ッチング時の電流バランスを改良してスイッチング特性
を良好なものにする電圧駆動形半導体スイッチング素子
のゲート回路に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage-driven semiconductor switching element (In
injection Enhanced Gate Tra
The present invention relates to a gate circuit of a voltage-driven semiconductor switching element that improves the current balance during switching of a transistor (hereinafter simply referred to as IEGT) to improve switching characteristics.

【0002】[0002]

【従来の技術】図5に従来のIEGTのゲート制御回路
を示す。図において、1はゲート駆動回路であり、この
ゲート駆動回路1は図示しない制御回路の出力信号に従
って、オン時には例えば+15Vの電圧を出力し、IE
GT(SD)をオンし、オフ時には―15Vの電圧を出
力してIEGT(SD)オフさせる。この時のゲ―ト抵
抗Rは共通に一個で制御してた。なお、Aはアノード端
子、Gはゲート端子、Kはカソード端子である。
2. Description of the Related Art FIG. 5 shows a conventional IEGT gate control circuit. In the figure, reference numeral 1 is a gate drive circuit, and the gate drive circuit 1 outputs a voltage of, for example, +15 V when turned on according to an output signal of a control circuit (not shown).
The GT (SD) is turned on, and when it is off, a voltage of -15 V is output to turn off the IEGT (SD). At this time, the gate resistance R was commonly controlled by one. A is an anode terminal, G is a gate terminal, and K is a cathode terminal.

【0003】ここで、IEGT(SD)は図5に示すよ
うに比較的小さなチップch1〜chnを多数並列接続
して結果的に大容量のIEGT(SD)を作っている。
これらの素子では多数チップch1〜chnの並列接続
を行うため、その電流バランスを良くさせる必要があ
り、オン時の電圧を揃える等の対策を行っていたが、定
常時は良いがスイッチング時は各チップch1〜chn
間の電流バランスは悪かった。
Here, as shown in FIG. 5, the IEGT (SD) is formed by connecting a large number of relatively small chips ch1 to chn in parallel, and as a result, a large capacity IEGT (SD) is produced.
Since a large number of chips ch1 to chn are connected in parallel in these elements, it is necessary to improve the current balance, and measures such as making the voltages at the on-time equalized were taken. Chips ch1 to chn
The current balance between them was bad.

【0004】[0004]

【発明が解決しようとする課題】以上、従来のゲート制
御回路のようにオンとオフ時に同じゲート抵抗RでIE
GT(SD)を駆動するのではスイッチング時の各チッ
プch1〜chnの電流バランスは良くならない。
As described above, the IE with the same gate resistance R at the time of turning on and off like the conventional gate control circuit.
When the GT (SD) is driven, the current balance of the chips ch1 to chn at the time of switching is not improved.

【0005】そこで本発明はオン時とオフ時とも各チッ
プch1〜chnの電流バランスを良くしてスイッチン
グ特性を良好なものとすることができる電圧駆動形半導
体スイッチのゲート回路を提供するとを目的とする。
Therefore, an object of the present invention is to provide a gate circuit of a voltage drive type semiconductor switch capable of improving the current balance of each of the chips ch1 to chn at the time of turning on and off and improving the switching characteristics. To do.

【0006】[0006]

【課題を解決するための手段】前記目的を達成するため
に、請求項1に記載の発明に係る電圧駆動形半導体スイ
ッチング素子のゲート回路は、複数のチップを並列接続
して共通のアノード端子とカソード端子及びゲート端子
を有する電圧駆動形半導体スイッチング素子において、
前記電圧駆動形半導体スイッチング素子のオン特性及び
オフ特性のそれぞれに適したゲート抵抗を前記電圧駆動
形半導体スイッチング素子のゲート駆動回路と前記ゲー
ト端子との間に接続する手段を備えたことを特徴する。
In order to achieve the above object, a gate circuit of a voltage-driven semiconductor switching element according to a first aspect of the present invention comprises a plurality of chips connected in parallel and a common anode terminal. In a voltage-driven semiconductor switching element having a cathode terminal and a gate terminal,
A means for connecting a gate resistance suitable for each of the ON characteristic and the OFF characteristic of the voltage driven type semiconductor switching element between the gate driving circuit of the voltage driven type semiconductor switching element and the gate terminal. .

【0007】又、前記目的を達成するために、請求項2
に記載の発明に係る電圧駆動形半導体スイッチング素子
のゲート回路は、複数のチップを並列接続して共通のア
ノード端子とカソード端子及び独立して前記チップ毎に
ゲート端子を有する電圧駆動形半導体スイッチング素子
において、前記各チップ毎のオン特性、オフ特性のそれ
ぞれに適したゲート抵抗を前記電圧駆動形半導体スイッ
チング素子のゲート駆動回路と前記各ゲート端子との間
に接続する手段を備えたことを特徴とするものである。
Further, in order to achieve the above-mentioned object, claim 2
According to another aspect of the present invention, there is provided a gate circuit for a voltage-driven semiconductor switching device, wherein a plurality of chips are connected in parallel to have a common anode terminal and a common cathode terminal, and each gate independently has a gate terminal. In the above, the device further comprises means for connecting a gate resistance suitable for each of the on-characteristic and the off-characteristic of each chip between the gate driving circuit of the voltage driving type semiconductor switching element and each of the gate terminals. To do.

【0008】[0008]

【発明の実施の形態】次に、請求項1に記載の発明に係
る電圧駆動形半導体スイッチング素子のゲート回路の第
1の実施の形態を図1の構成図を参照して説明する。図
1において、1はIEGT(SD)のゲート駆動回路で
図示しない制御回路にしたがってIEGT(SD)のオ
ン時には例えば+15Vの電圧を出力し、オフ時には−
15Vの電圧を出力してIEGT(SD)のオン・オフ
を制御する。ch1〜chnはIEGTのチップch1
〜chnであり、複数個のチップch1〜chnを1つ
のパッケージに納めて各チップのアノード、カソード、
ゲートをそれぞれ共通接続して、アノード端子A、カソ
ード端子K及びゲート端子Gを外部端子として導出して
IEGT(SD)を構成する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a first embodiment of a gate circuit of a voltage-driven semiconductor switching device according to the present invention will be described with reference to the block diagram of FIG. In FIG. 1, reference numeral 1 denotes a gate drive circuit of the IEGT (SD), which outputs a voltage of, for example, +15 V when the IEGT (SD) is on and outputs a voltage of −15 V when the IEGT (SD) is on, according to a control circuit (not shown).
A voltage of 15 V is output to control the on / off of IEGT (SD). ch1 to chn are IEGT chips ch1
~ Chn, a plurality of chips ch1 to chn are accommodated in one package, and an anode, a cathode of each chip,
The gates are commonly connected to each other, and the anode terminal A, the cathode terminal K, and the gate terminal G are led as external terminals to form an IEGT (SD).

【0009】前述のように構成されたIEGT(SD)
において、IEGT(SD)のオン特性に適したゲート
抵抗RPはゲート駆動回路1とゲート端子Gとの間にダ
イオードDPを介して接続され、IEGT(SD)のオ
フ特性に適したゲート抵抗RNはゲート駆動回路1とゲ
ート端子Gとの間にダイオードDNを介して接続され
る。
IEGT (SD) constructed as described above
In, the gate resistance RP suitable for the ON characteristic of IEGT (SD) is connected between the gate drive circuit 1 and the gate terminal G via the diode DP, and the gate resistance RN suitable for the OFF characteristic of IEGT (SD) is The gate drive circuit 1 and the gate terminal G are connected via a diode DN.

【0010】従って、IEGT(SD)はオン時、オフ
時において、それぞれに適したゲート抵抗RP,RNで
制御されるためIEGT(SD)内部のチップのスイッ
チング時の電流バランスを改善することができる。
Therefore, since the IEGT (SD) is controlled by the gate resistances RP and RN suitable for ON and OFF, the current balance at the time of switching the chip inside the IEGT (SD) can be improved. .

【0011】次に、請求項1に記載の発明の他の実施例
に係る電圧駆動形半導体スイッチング素子のゲート回路
の第2の実施の形態を図1と同一部に同一符号を付して
示す図2の構成図を参照して説明する。
Next, a second embodiment of the gate circuit of the voltage-driven semiconductor switching element according to another embodiment of the invention described in claim 1 is shown in FIG. Description will be made with reference to the configuration diagram of FIG.

【0012】図2に示す実施例は、図1のIEGT(S
D)のチップch1〜chnに内部ゲート抵抗Rch1
〜Rchnを予め接続(プロセスで作成しても良い)し
たものである。
In the embodiment shown in FIG. 2, the IEGT (S
D) chips ch1 to chn have internal gate resistance Rch1
~ Rchn are connected in advance (may be created by a process).

【0013】これにより、図1のように外部のみにゲー
ト抵抗RP,RNを接続したものに比べ更に内部ゲート
抵抗Rch1〜Rchnによりチップ間の差が更に少く
なるためスイッチング時の電流バランスは更に改善され
る。
As a result, the internal gate resistances Rch1 to Rchn further reduce the difference between the chips as compared with the case where the gate resistances RP and RN are connected only to the outside as shown in FIG. 1, so that the current balance during switching is further improved. To be done.

【0014】次に、請求項2に記載の発明の実施例に係
る電圧駆動形半導体スイッチング素子のゲート回路の第
3の実施の形態を図3の構成図を参照して説明する。図
3において、1はIEGT(SD)のゲート駆動回路で
図示しない制御回路にしたがってIEGT(SD)のオ
ン時には例えば+15Vの電圧を出力し、オフ時には−
15Vの電圧を出力してIEGT(SD)のオン・オフ
を制御する。ch1〜chnはIEGT(SD)のチッ
プであり、複数個のチップch1〜chnを1つのパッ
ケージに納めて各チップch1〜chnのアノード、カ
ソードをそれぞれ共通接続して、アノード端子A、カソ
ード端子Kとして外部へ導出して、更にゲ―トGはそれ
ぞれ独自に外部ゲート端子G1〜Gnとして導出してI
EGT(SD)を構成する。
Next, a third embodiment of the gate circuit of the voltage-driven semiconductor switching device according to the second embodiment of the invention will be described with reference to the block diagram of FIG. In FIG. 3, reference numeral 1 denotes a IEGT (SD) gate drive circuit, which outputs a voltage of, for example, +15 V when the IEGT (SD) is on and outputs a voltage of −15 V when the IEGT (SD) is on, according to a control circuit (not shown).
A voltage of 15 V is output to control the on / off of IEGT (SD). ch1 to chn are IEGT (SD) chips, and a plurality of chips ch1 to chn are housed in one package, and the anode and cathode of each chip ch1 to chn are commonly connected to each other to form an anode terminal A and a cathode terminal K. As the external gate terminals G1 to Gn, and the gate G is also independently derived as I
Configure EGT (SD).

【0015】本実施例は、IEGT(SD)の各チップ
ch1〜chnからゲート端子G1〜Gnを導出して、
IEGT(SD)のオン特性に適したゲート抵抗RP1
〜RPnをゲート駆動回路1と、それぞれのゲート端子
G1〜Gnとの間にダイオードDP1〜DPnを介して
接続し、IEGT(SD)のオフ特性に適したゲート抵
抗RN1〜RNnはゲート駆動回路1と、それぞれのゲ
ート端子G1〜Gnとの間にダイオードDN1〜DNn
を介して接続する。
In this embodiment, the gate terminals G1 to Gn are derived from the chips ch1 to chn of the IEGT (SD),
Gate resistance RP1 suitable for on-state of IEGT (SD)
To RPn are connected between the gate drive circuit 1 and the respective gate terminals G1 to Gn via diodes DP1 to DPn, and the gate resistances RN1 to RNn suitable for the off characteristics of the IEGT (SD) are the gate drive circuit 1 And the diodes DN1 to DNn between the respective gate terminals G1 to Gn.
Connect through.

【0016】前述のように構成することによって、IE
GT(SD)のオン時はダイオードDP1,ゲート抵抗
RP1を通してチップch1がオン、同様にダイオード
DPn、ゲート抵抗RPnを通してチップchnがオン
する。つまり全チップ独立してオンとなる。
By configuring as described above, the IE
When the GT (SD) is turned on, the chip ch1 is turned on through the diode DP1 and the gate resistor RP1, and similarly, the chip chn is turned on through the diode DPn and the gate resistor RPn. That is, all chips are turned on independently.

【0017】一方、オフ時はダイオードDN1、ゲート
抵抗Rn1を通してチップch1がオフ、同様にダイオ
ードDNn、ゲート抵抗RNnを通してチップchnが
オフとなる。つまり全チップ独立にオフとなる。
On the other hand, when off, the chip ch1 is turned off through the diode DN1 and the gate resistor Rn1, and similarly, the chip chn is turned off through the diode DNn and the gate resistor RNn. That is, all chips are turned off independently.

【0018】又、各チップch1〜chnのオン時とオ
フ時でゲート抵抗を変えているのでオン時、オフ時とも
電流バランスが良くなるように自由に設定できる。例え
ば、オフ時にゲート抵抗が大きいと、各チップ間のミラ
ー効果のばらつきが生じ、オフの早い素子は早く切れる
ため遅いチップに電流が集中してしまい電流がアンバラ
ンスになってしまう。そのため、オフは比較的低抵抗で
駆動させてミラー効果時間差のばらつきの影響を小さく
させることによってオフ時の電流バランスを良くさせる
ことができる。
Further, since the gate resistance is changed when each of the chips ch1 to chn is turned on and off, it can be freely set so that the current balance is good both when turned on and when turned off. For example, if the gate resistance is large at the time of turning off, the mirror effect varies among the chips, and the elements turning off early turn off quickly, so that the current concentrates on the chips that are slowing and the current becomes unbalanced. Therefore, the off current can be driven with a relatively low resistance to reduce the influence of the variation in the mirror effect time difference, thereby improving the current balance during the off time.

【0019】一方、オン時は比較的大きな抵抗で駆動さ
せて、ミラー効果を長くさせてオン時の時間差の影響を
少くさせてオン時の電流アンバランスを無くすることが
できる。
On the other hand, at the time of turning on, the current is imbalanced at the time of turning on by driving with a relatively large resistance to lengthen the mirror effect and reduce the influence of the time difference at the time of turning on.

【0020】以上のように、IEGT(SD)の各チッ
プch1〜chnを並列接続したとき各チップch1〜
chnを独立に制御できるので、各チップch1〜ch
nの電流バランスをオン,オフ時とも最適に設定でき
る。
As described above, when each chip ch1 to chn of the IEGT (SD) is connected in parallel, each chip ch1 to chn
chn can be controlled independently, so each chip ch1 ~ ch
The current balance of n can be optimally set at both on and off.

【0021】以上の説明では、IEGT(SD)のチッ
プレベルの電流バラスについて説明したが、素子を多数
並列接続した時の素子間の電流バランスについても全く
同様なことがいえる。
In the above description, the chip-level current variation of IEGT (SD) has been described, but the same applies to the current balance between elements when a large number of elements are connected in parallel.

【0022】最後に、請求項2に記載の発明の他の実施
例に係る電圧駆動形半導体スイッチング素子のゲート回
路の第4の実施の形態を図3と同一部に同一符号を付し
て示す図4の構成図を参照して説明する。
Finally, a fourth embodiment of the gate circuit of the voltage-driven semiconductor switching device according to another embodiment of the invention described in claim 2 is shown in FIG. This will be described with reference to the configuration diagram of FIG.

【0023】図4の実施例では、図3の実施例に比較し
て各チップch1〜chnに内部ゲート抵抗Rch1〜
Rchnを接続してあるためチップch1〜chn間の
差がさらに少くなるため、スイッチング時の電流バラン
スは更に改善することが出来る。尚、図3及び図4の実
施例において、ダイオードDP1〜DPnを共通にして
1個とし、又、ダイオードDN1〜DNnを共通にして
1個としても良い。
In the embodiment shown in FIG. 4, the internal gate resistors Rch1 to Rch1 to the chips ch1 to chn are different from those in the embodiment shown in FIG.
Since the Rchn is connected, the difference between the chips ch1 to chn is further reduced, so that the current balance at the time of switching can be further improved. In the embodiment of FIGS. 3 and 4, the diodes DP1 to DPn may be shared by one, or the diodes DN1 to DNn may be shared by one.

【0024】[0024]

【発明の効果】以上説明のように、本発明によれば簡単
な方法でスイッチング素子内の多数チップを並列接続し
た場合にオン時、オフ時ともチップ内の電流バランスが
良くなるのでチップの利用率が改善され信頼性を上げる
ことができる。
As described above, according to the present invention, when a large number of chips in a switching element are connected in parallel by a simple method, the current balance in the chip is improved both when the chip is on and when it is off. The rate is improved and the reliability can be increased.

【図面の簡単な説明】[Brief description of the drawings]

【図1】請求項1の発明に係る第1の実施の形態を示す
構成図。
FIG. 1 is a configuration diagram showing a first embodiment according to the invention of claim 1.

【図2】請求項1の発明の他の実施例に係る第2の実施
の形態を示す構成図。
FIG. 2 is a configuration diagram showing a second embodiment according to another embodiment of the invention of claim 1.

【図3】請求項2の発明に係る第3の実施の形態を示す
構成図。
FIG. 3 is a configuration diagram showing a third embodiment according to the invention of claim 2.

【図4】請求項2の発明の他の実施例に係る第4の実施
の形態を示す構成図。
FIG. 4 is a configuration diagram showing a fourth embodiment according to another embodiment of the invention of claim 2;

【図5】従来の電圧駆動形半導体スイッチング素子のゲ
―ト回路の構成図。
FIG. 5 is a configuration diagram of a gate circuit of a conventional voltage-driven semiconductor switching element.

【符号の説明】[Explanation of symbols]

1 …ゲート駆動回路 DP1〜
DPn…ダイオード DN1〜DNn…ダイオード RP1〜
RPn…ゲート抵抗 RN1〜RNn…ゲート抵抗 G
…ゲート端子 G1〜Gn …ゲート端子 A
…アノード端子 K …カソード端子 ch1〜
chn…チップ SD …電圧駆動形半導体素子
1 ... Gate drive circuit DP1
DPn ... Diodes DN1 to DNn ... Diodes RP1
RPn ... Gate resistance RN1 to RNn ... Gate resistance G
… Gate terminals G1 to Gn… Gate terminals A
… Anode terminal K… Cathode terminal ch1
chn ... Chip SD ... Voltage driven semiconductor device

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 複数のチップを並列接続して共通
のアノード端子とカソ―ド端子及びゲート端子を有する
電圧駆動形半導体スイッチング素子において、前記電圧
形半導体スイッチング素子のオン特性及びオフ特性のそ
れぞれに適したゲート抵抗を前記電圧駆動形半導体スイ
ッチング素子のゲート駆動回路と前記ゲート端子との間
に接続する手段を備えたことを特徴とした電圧駆動形半
導体スイッチング素子のゲート回路。
1. A voltage-driven semiconductor switching device having a plurality of chips connected in parallel and having a common anode terminal, cathode terminal, and gate terminal. A gate circuit for a voltage-driven semiconductor switching device, comprising means for connecting a suitable gate resistor between the gate drive circuit for the voltage-driven semiconductor switching device and the gate terminal.
【請求項2】 複数のチップを並列接続して共通
のアノード端子とカソード端子及び独立して前記チップ
毎にゲート端子を有する電圧駆動形半導体スイッチング
素子において、前記各チップ毎のオン特性、オフ特性の
それぞれに適したゲート抵抗を前記電圧駆動形半導体ス
イッチング素子のゲート駆動回路と前記各ゲート端子と
の間に接続する手段を備えたことを特徴とした電圧駆動
形半導体スイッチング素子のゲート回路。
2. A voltage-driven semiconductor switching device having a plurality of chips connected in parallel and having a common anode terminal and cathode terminal and independently a gate terminal for each of the chips, on-characteristics and off-characteristics of each chip. A gate circuit for a voltage-driven semiconductor switching element, comprising means for connecting a gate resistor suitable for each of the above between a gate drive circuit of the voltage-driven semiconductor switching element and each of the gate terminals.
JP32999295A 1995-12-19 1995-12-19 Gate circuit for voltage driven semiconductor switching element Pending JPH09172359A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP32999295A JPH09172359A (en) 1995-12-19 1995-12-19 Gate circuit for voltage driven semiconductor switching element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP32999295A JPH09172359A (en) 1995-12-19 1995-12-19 Gate circuit for voltage driven semiconductor switching element

Publications (1)

Publication Number Publication Date
JPH09172359A true JPH09172359A (en) 1997-06-30

Family

ID=18227569

Family Applications (1)

Application Number Title Priority Date Filing Date
JP32999295A Pending JPH09172359A (en) 1995-12-19 1995-12-19 Gate circuit for voltage driven semiconductor switching element

Country Status (1)

Country Link
JP (1) JPH09172359A (en)

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JPH11235015A (en) * 1998-02-13 1999-08-27 Toshiba Corp Voltage-driven power semiconductor device and method of controlling the gate of the same
JP2004096191A (en) * 2002-08-29 2004-03-25 Mitsubishi Electric Corp Semiconductor switching element and semiconductor switching apparatus
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US8598942B2 (en) 2011-07-06 2013-12-03 Fuji Electric Co., Ltd. Current correction circuit for power semiconductor device and current correction method
US8644038B2 (en) 2010-10-22 2014-02-04 Fuji Electric Co., Ltd. Current detection circuit for a power semiconductor device
US8659864B2 (en) 2010-10-08 2014-02-25 Fuji Electric Co., Ltd. Power semiconductor device current detector circuit and detection method
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11235015A (en) * 1998-02-13 1999-08-27 Toshiba Corp Voltage-driven power semiconductor device and method of controlling the gate of the same
JP2004096191A (en) * 2002-08-29 2004-03-25 Mitsubishi Electric Corp Semiconductor switching element and semiconductor switching apparatus
US8659864B2 (en) 2010-10-08 2014-02-25 Fuji Electric Co., Ltd. Power semiconductor device current detector circuit and detection method
US8644038B2 (en) 2010-10-22 2014-02-04 Fuji Electric Co., Ltd. Current detection circuit for a power semiconductor device
US8598942B2 (en) 2011-07-06 2013-12-03 Fuji Electric Co., Ltd. Current correction circuit for power semiconductor device and current correction method
US8884560B2 (en) 2011-11-25 2014-11-11 Mitsubishi Electric Corporation Inverter device and air conditioner including the same
CN103138596A (en) * 2011-11-25 2013-06-05 三菱电机株式会社 Inverter device and air conditioner including the same
JP2013115855A (en) * 2011-11-25 2013-06-10 Mitsubishi Electric Corp Inverter device and air conditioner having the same
EP2597767A3 (en) * 2011-11-25 2014-08-06 Mitsubishi Electric Corporation Inverter device and air conditioner including the same
JP2014187483A (en) * 2013-03-22 2014-10-02 Oki Electric Ind Co Ltd Load drive circuit
JP2019149558A (en) * 2014-05-12 2019-09-05 ローム株式会社 Semiconductor device
US11133398B2 (en) 2014-05-12 2021-09-28 Rohm Co., Ltd. Semiconductor device including sense insulated-gate bipolar transistor
US11942531B2 (en) 2014-05-12 2024-03-26 Rohm Co., Ltd. Semiconductor device including sense insulated-gate bipolar transistor
JP2021005925A (en) * 2019-06-25 2021-01-14 株式会社デンソー Parallel switching circuit
CN113691109A (en) * 2020-05-19 2021-11-23 三菱电机株式会社 Semiconductor device with a plurality of semiconductor chips
JP2021182813A (en) * 2020-05-19 2021-11-25 三菱電機株式会社 Semiconductor device
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