JPH06112780A - Signal output circuit - Google Patents

Abstract

PURPOSE:To increase the signal transition speed of an output signal and to variably control the signal transition time with respect to the signal output circuit which outputs the output signal to drive a capacitive load in the succeeding stage side based on an input signal inputted from the preceding stage side. CONSTITUTION:Since a driving circuit 1 outputs the output signal based on the input signal and the transition speed increasing signal to increase the signal level transition speed of this output signal is outputted from an output speed increasing circuit 2 and the signal level transition time is controlled by a transition time control circuit 3, the transition time control circuit 3 changes the on-state resistance of a MOS transistor by the transition time control signal inputted from the outside to the transition time control circuit 3 to change the current value of the transition speed increasing signal; and thereby, the signal level rise speed of the output signal is increased, and the transition time required for signal level fall is variably controlled.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal output circuit for outputting an output signal for driving a capacitive load on a rear stage based on an input signal input from a front stage, and more particularly, to a signal level transition time of the output signal. The present invention relates to a signal output circuit for variably controlling.

[0002]

2. Description of the Related Art Heretofore, a signal output circuit of this type has been disclosed in JP-A-3-147417. A signal output circuit similar to this is shown in FIG. In the figure, a conventional signal output circuit includes a drive circuit 1 that drives and outputs an output signal based on an input signal, and a transition speed-up signal that outputs a transition speed-up signal to the drive circuit 1 when the signal level of the input signal changes. The circuit 2 is provided.

The drive circuit 1 has a C-MOS gate composed of a MOS transistor P _i and an n-MOS transistor n ₁ on the input side of the front stage, and np on the output side of the rear stage.
This is a configuration including an output transistor Q ₁ formed of a Schottky type npn-type transistor in which an n-type off-buffer transistor Q ₂ is connected in series.

The transition speed-up circuit 2 is a p-MOS transistor.
Register P₂, N-MOS transistor n_FourAnd resistance R
_FourAre connected in series, and the -MOS and n-MOS
Each transistor P₂, N_FourConnect each gate of
Note n-MOS transistor n _FourAnd resistance R_FourAt the connection midpoint
npn transistor Q_FourConfiguration to connect the base terminals of
Is.

When an "L" level input signal is input to the drive circuit 1, an "H" level output signal is output. When the input signal transits to the "H" level, the output signal becomes "H". It becomes the "L" level. In the transition transition period of the input signal, the transition speed-up circuit 2 outputs the transition speed-up signal to the base terminal of the output transistor Q ₁ . This transition speed-up signal shortens the signal transition time T _PHL (transition time from the H level to the L level) of the output signal output from the output transistor Q ₁ .

[0006]

Since the conventional signal output circuit is configured as described above, even if the signal transition time of the output signal can be shortened, the signal transition time can be changed to an arbitrary time. There was a problem that it could not be set and controlled.

The present invention has been made to solve the above problems, and an object of the present invention is to propose a signal output circuit capable of accelerating the signal transition time of an output signal and variably controlling the signal transition time. To do.

[0008]

FIG. 1 is a diagram for explaining the principle of the present invention. In the figure, a signal output circuit according to the present invention has a MOS transistor driven based on an input signal and a bipolar transistor to which a signal output according to the driving state of the corresponding MOS transistor is input as a base current. A drive circuit (1) which outputs an output signal based on the drive state of the drive circuit, and two MOS transistors connected in series that are complementarily turned on / off based on the input signal. An output speed-up circuit (2) for outputting a transition speed-up signal for speeding up a signal level transition of an output signal from a series connection circuit end of two MOS transistors to a base terminal of a bipolar transistor in the drive circuit (1); A signal level transition time of the output signal, which is connected in series to the output speed-up circuit (2) Transition time control signal for controlling are those comprising a transition time control circuit having a MOS transistor (3) which is input as a gate voltage.

[0009]

In the present invention, the MOS of the transition time control circuit is
The on-resistance of the transistor is controlled and changed by the transition time control, and the change of the on-resistance changes the current value of the transition speed-up signal supplied from the output speed-up circuit to the output transistor of the drive circuit. Since the transition speed-up signal in which the current value has changed is added to the base current output from the MOS transistor of the drive circuit and supplied to the base terminal of the output transistor, the turn-on time of the output transistor can be adjusted. The rise (the transition from the “L” level to the “H” level) is accelerated, and the transition time required for the fall (the transition from the “H” level to the “L” level) of the output signal is variably controlled.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. In the figure, the signal output circuit according to the present embodiment is
Wherein an inverter according to the conventional circuit as well as Bi-CMOS process, the signal level of the output signal V _{ou t} deviating output from the driving circuit 1 and the driving circuit 1 outputs an output signal V _out based on the input signal Vin The output acceleration circuit 2 for accelerating the transition times T _PLH and T _PHL is provided,
In addition to this configuration, it is connected between the output speed-up circuit 2 and the ground GND, and is turned on / off based on the transition control signal V _con.
This is a configuration including a transition time control circuit 3 in which the ON resistance value R _ON is controlled by being turned off.

Next, the operation of the circuit of the present embodiment based on the above configuration will be described. When the input signal Vin is input to the drive circuit 1 and the output speed-up circuit 2 at the “L” level, C-MO
The P-MOS transistor P _i of the S gate 10 is turned on, and the n-MOS transistor n ₃ and the buffer transistors (each npn-type bipolar transistor) Q ₂ and Q ₃ connected in the subsequent stage are turned on.

Further, the n-MOS transistor n₃When
N-MOS transistor n connected in series₂Is "L"
Bell input signal V_inIs input and remains turned off.
Output transistor Q₁Is turned off. this
Output transistor Q ₁Is turned off,
Quffa transistor Q₂Is turned on
Output signal V of "H" level_outAnd output
It

The output speed-up circuit 2 to which the "L" level input signal V _in is input is a P-MOS transistor P ₂
Is turned on, but the n-MOS transistor n
N is connected to the subsequent stage because ₄ is turned off
The pn transistor Q ₄ maintains the turn-off state, and the transition speed-up signal I _B is not output.

[0014] In addition, when the signal level of the input signal V _in transitions from "L" to "H" level, C-MO
N-MOS transistors n _i of S gate 10 becomes turned on, respectively and turned off the n-MOS transistor n ₃ and a buffer transistor Q _2, Q ₃ is connected to the subsequent stage. Further, the n-MOS transistor n ₂ to which the “H” level input signal is input is turned on, and the output transistor Q ₁ is turned on. As described above, since the output transistor Q ₁ is turned on and the buffer transistors Q ₂ and Q ₃ are turned off, the output signal V _out transits from the “H” level to the “L” level.

In the transition period when the signal level changes, P- of the output speed-up circuit 2 to which the input signal V _in is input.
MOS transistor P ₂ and n-MOS transistor n
₄ are turned on at the same time, and a through current I _o flows. In order to pass this through current I _o , a P-MOS
By setting the areas of the transistor P ₂ and the n-MOS transistor n ₄ to be substantially equal to each other, due to the difference in carrier mobility u _p between the transistors P ₂ and n ₄ , n−
The turn-on speed of the MOS transistor n ₄ is set to P-MOS.
It must be faster than the turn-off speed of the transistor P ₂ .

Further, each of the P or n MOS transistors
Star P₂, N_FourThrough current I _DIs flowing,
The transition control signal V is applied to the transition time control circuit 3._conIs entered
And this transition control signal V_conON resistance corresponding to the voltage of
R_onIs a P-MOS transistor P_FiveOccurs in This on
Resistance R_onDepending on the resistance value of each of the P or n MOS transistors
Register P₂, N_FourThrough current I flowing through_DShunt
Through current I_D1And I_D2It will be distributed to and.

Now, the P-MOS transistor P_FiveOn
Resistance R_onWhen the resistance becomes low, the shunt current I_D2Is increasing
Slew current I_D1Decrease, npn type
Langista Q_FourTurn-on time is delayed. This tar
Due to the delay in the turn-on time, the output transistor Q1
Current I_BIIs also delayed, and the output signal V
_outSignal level transition time T_PHLSlow down.

On the other hand, when the on-resistance R _{on of the} P-MOS transistor P ₅ has a high resistance value, the shunt-through current I _D1 increases, the turn-on time of the npn transistor Q ₄ is shortened, and the signal of the output signal V _out is increased. _{Increase the} level transition time T _PHL .

It should be noted that PM of the transition time control circuit 3
The OS transistor P ₅ can also be composed of an n-MOS transistor. In this case, the value of the transition control signal V _con is input as a positive predetermined voltage value.

In the above embodiment, the case where the drive circuit 1 is applied to the signal output circuit of the inverter logic is shown, but for example, when the input signal V _in and the output signal V _out change in the same logic state. Can be applied.
In this case, the smaller the area of the P-MOS transistor P ₂ of area than n-MOS transistor n4.
By setting each area, the turn-on of the n-MOS transistor n ₄ can be delayed when the input signal V _in transits from the “H” level to the “L” level, and similarly, the base of the output transistor Q ₁ can be delayed. The current can be increased.

Further, as shown in FIGS. 3A and 3B, the transition time control circuit 3 may be configured to connect a resistor R ₅ in series with the P-MOS transistor P ₅ .
In either case, the signal level transition time T _PHL of the output signal V _ont is controlled by a value obtained by adding the respective values of the ON resistance R _on and the resistance R ₅ of the P-MOS transistor P ₅ .

Further, as shown in FIGS. 4 (A) and 4 (B),
The transfer time control circuit 3 is connected to the n-MOS transistor n._FiveAgainst
Resistor R in series_FiveIt is also possible to have a configuration in which is connected.
On resistance R as in FIG._onAnd resistance R_FiveAnd each resistance value
Signal level transition time T _PHLTo control.

Further, a plurality of MOS transistors of the transition time control circuit 3 are connected in series as shown in FIG.
It is also possible to control each MOS transistor collectively or individually. In this case, the signal level transition time T is calculated by the sum of the ON resistance values of the MOS transistors.
Control _PHL . In particular, when individually controlling each MOS transistor, the ON resistance value can be set with high accuracy, and fine adjustment control of the signal level transition time T _PHL becomes possible.

[0024]

As described above, the drive circuit outputs the output signal based on the input signal, and the transition speed-up signal for speeding up the signal level transition of the output signal is output from the output speed-up circuit. Since the transition time control circuit controls the time of signal level transition, the transition time control circuit is
The on-resistance of the OS transistor is changed by a transition time control signal externally input to the transition time control circuit to change the current value of the transition speed-up signal to speed up the signal level rise of the output signal and This has the effect of variably controlling the transition time required for the level to fall.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a circuit configuration diagram for explaining a signal output circuit according to an embodiment of the present invention.

FIG. 3 is a partial circuit configuration diagram for explaining a signal output circuit according to another embodiment of the present invention.

FIG. 4 is a partial circuit configuration diagram for explaining a signal output circuit according to another embodiment of the present invention.

FIG. 5 is a circuit configuration diagram of a transition time control circuit for explaining a signal output circuit according to another embodiment of the present invention.

FIG. 6 is a circuit configuration diagram of a conventional signal output circuit.

[Explanation of symbols]

1 ... driving circuit 2 ... output speed circuit 3 ... transition time control circuit 10 ... C-MOS gate _{P 1, P 2, P 5} ... P-MOS transistors _{n 1, n 2, n 3} , n 4 ... n-MOS Transistor Q ₁ ... Output transistor Q ₂ , Q ₃ ... Buffer transistor Q ₄ ... Npn type transistor V _in ... Input signal V _out ... Output signal V _con ... Transition control signal

Claims (4)

[Claims] 1. A MOS transistor driven based on an input signal and a bipolar transistor to which a signal output according to a driving state of the corresponding MOS transistor is input as a base current, and based on a driving state of the corresponding bipolar transistor. A drive circuit (1) for outputting an output signal, and two MOS transistors connected in series that are complementarily turned on / off based on the input signal, and the two MOS transistors connected in series are connected in series. An output speed-up circuit (2) for outputting a transition speed-up signal for speeding up the signal level transition of the output signal from the circuit end to the base terminal of the bipolar transistor in the drive circuit (1).
And a transition time control circuit (3) having a MOS transistor connected in series to the output speed-up circuit (2) and receiving a transition time control signal for controlling a signal level transition time of the output signal as a gate voltage. ), And an output signal circuit comprising: 2. The signal output circuit according to claim 1, wherein the transition time control circuit (3) has a resistance connected in series with a MOS transistor. 3. The signal output circuit according to claim 1, wherein the transition time control circuit (3) is configured by connecting a plurality of MOS transistors in series. 4. The signal output circuit according to each of claims 1 to 3, wherein the transition time control circuit (3) comprises:
A MOS transistor is an n-MOS transistor or a p-
An output signal circuit comprising one of MOS transistors.