JP2003169465A - Gate drive circuit and power conversion device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a gate drive circuit wherein, when a plurality of semiconductor switching elements are connected, an imbalance between a voltage share and a current share due to a variation in a threshold voltage from one switching element to another is improved. <P>SOLUTION: A gate drive circuit 103 which outputs gate control output signals to a semiconductor switching element 101 is provided with an offset circuit 3 which offsets the potentials of gate control output signals. Gate control output signals are offset through the offset circuit 3 by an amount equivalent to the potential corresponding to a difference in the threshold voltage between a plurality of semiconductor switching elements to equalize the timing of switching. Thereby, the imbalance between the voltage share and current share is improved. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate drive circuit,
The present invention also relates to a power converter, and more particularly to a gate drive circuit that drives a voltage-driven semiconductor switching element, and a power converter using the gate drive circuit.

[0002]

2. Description of the Related Art Semiconductor switching elements are widely used in power conversion devices such as inverters and chopper circuits, and are indispensable in the power field.

In recent years, such a semiconductor switching element for a power conversion device has been replaced by a gate turn-off thyristor (GTO) which has been widely used because it is excellent in high voltage and large current, and thus has high voltage and large current. In addition to,
A voltage-driven semiconductor switching element represented by an insulated gate bipolar transistor (IGBT) excellent in high-speed switching tends to be used.

Further, in the power converter, a plurality of semiconductor switching elements have been used in order to cope with an increase in capacity, an increase in voltage, and an increase in current.

Power converters using a plurality of semiconductor switching elements include those having a plurality of semiconductor switching elements connected in series and those having a plurality of semiconductor switching elements connected in parallel. In either case, FIG. As described above, the gate drive circuit 103 for driving the semiconductor switching element 101 is connected to the semiconductor switching element 101 through the gate resistor 105. The gate drive circuit 103 outputs a gate control output signal to output the voltage drive type semiconductor switching element 101.
Are driving.

Although the gate drive circuit is individually provided for the plurality of semiconductor switching elements, all of them output the gate control output signal of the same potential. Therefore, when the semiconductor switching elements are connected in series or in parallel, each of the multiple connected semiconductor switching elements performs a switching operation according to each threshold voltage, so that there is variation in each threshold voltage. The switching operation also varies, and among the plurality of semiconductor switching elements, the semiconductor switching element with a high threshold voltage bears a high voltage in the case of series connection, and in the case of parallel connection. It will bear a large current.

As a result, voltage or current exceeding the capacity is applied to some semiconductor switching elements due to variations in threshold voltage for some time, resulting in deterioration of capacity of power conversion operation and reliability of apparatus. There was a problem to say.

Therefore, in the conventional power converter, in order to prevent the bias of the voltage and the current in the plurality of semiconductor switching elements, for example, Japanese Patent Laid-Open No. 10-2374 is used.
No. 4, in order to minimize the imbalance of currents flowing in a plurality of voltage-driven semiconductor switching elements connected in parallel, a gate input voltage input to each semiconductor switching element is detected, and a turn-on signal is detected. It is disclosed that the switching of the semiconductor switching element is controlled so as to match the gate signal of the gate input terminal that turns on latest at the time and the gate signal that turns off earliest at the time of turn-off signal.

Further, in Japanese Unexamined Patent Publication No. 2001-119926, two semiconductor switching elements are connected in series in order to protect a semiconductor switching element to which an overvoltage is applied at high speed when an imbalance of voltage occurs. In the case of the circuit consisting of (3), it is disclosed that when the timing of those turn-on operations is detected and an overvoltage is detected, the circuit is turned on at a voltage higher than the normal forward bias voltage.

[0010]

However, each of the methods disclosed in the above publications detects a turn-on signal or a turn-off signal applied to the semiconductor switching element and switches the semiconductor switching element in accordance with its operation timing. Control circuit, it is necessary to have a circuit for detecting turn-on and turn-off signals, and a circuit for high-speed signal control according to the detection result, preventing bias in voltage and current applied to the elements. However, there is a problem that the cost increase for these circuits is great.

The present invention has been made in view of the above,
The purpose is to improve the bias of the voltage sharing and the current sharing of the semiconductor switching device with a simple configuration when connecting multiple semiconductor switching devices, and to maximize the performance of the semiconductor switching device. A drive circuit is provided.

Another object of the present invention is to prevent deterioration of performance and reliability due to variations in threshold voltage of a plurality of semiconductor switching elements when a plurality of semiconductor switching elements are used. An object of the present invention is to provide a power conversion device that can do the above.

[0013]

The invention according to claim 1 is
In order to solve the above problems, the present invention is a gate drive circuit having an offset means for displacing a potential of a gate control output signal for driving a semiconductor switching element.

According to the present invention, the potential of the gate control output signal for driving the semiconductor switching element is changed,
When a plurality of semiconductor switching elements are driven, the influence of the difference in threshold voltage between the semiconductor switching elements is suppressed to improve the bias of the voltage sharing and the current sharing of the semiconductor switching elements.

According to a second aspect of the present invention, in the gate drive circuit according to the first aspect, the offset means changes the potential of the gate control output signal according to an offset setting signal from the outside.

According to the present invention, the potential of the gate control output signal can be changed by a signal from the outside, so that when the threshold voltage of the semiconductor element is changed by an external factor, the gate control is performed accordingly. It is intended to change the potential of the output signal.

In order to solve the above-mentioned problems, a third aspect of the present invention is a power conversion device characterized in that a plurality of semiconductor switching elements driven by the gate drive circuit according to the first or second aspect are connected in series. Is.

According to the present invention, by varying the potential of the gate control output signal of each semiconductor switching element connected in series by the gate drive circuit according to claim 1 or 2, the variation in threshold voltage is caused. It is intended to improve the bias of the voltage sharing.

In order to solve the above-mentioned problems, a fourth aspect of the invention is a power conversion device characterized in that a plurality of semiconductor switching elements driven by the gate drive circuit according to the first or second aspect are connected in parallel. Is.

According to the present invention, by varying the potential of the gate control output signal of each semiconductor switching element connected in parallel by the gate drive circuit according to claim 1 or 2, the variation in threshold voltage is caused. It is intended to improve the bias of the current sharing.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 is a circuit diagram for explaining a gate drive circuit to which the present invention is applied.

As shown in the figure, in the first embodiment, the conventional gate drive circuit 10 is used as the gate drive circuit.
The offset circuit 3 is provided on the input side of 3. The gate drive circuit provided with the offset circuit 3 is referred to as a gate drive circuit with an offset circuit 1. The output from the gate drive circuit 103 is the same as that of the conventional one.
It is input to the gate of the semiconductor switching element 101 via 05.

The offset circuit 3 is a circuit that displaces (offsets) the potential of the gate control output signal 7 output from the gate drive circuit 103 with respect to the potential of the input gate control input signal 5.

The operation of the gate drive circuit with the offset circuit according to the first embodiment will be described.

FIG. 2 is a diagram showing a gate control output signal output from the gate driving circuit.

Here, for example, when there are variations in the threshold voltages of the two semiconductor switching elements 101, as shown in FIG. 2A, the two semiconductor switching elements 10 are connected.
In the case where only the conventional gate drive circuit 103 is connected to both of the two, the timing at which each gate control output signal output from the gate drive circuit 103 is turned off due to variation in the threshold values of the two semiconductor switching elements 101. Difference occurs.

On the other hand, as shown in FIG. 2B, in the case where the gate drive circuit 1 with the offset circuit in which the offset circuit 3 is provided is connected to both of the two semiconductor switching elements 101, the semiconductor having the higher threshold voltage is used. By setting a positive offset by the gate drive circuit 1 with an offset circuit connected to the switching element and changing the potential of the gate control output signal, the offset is set as compared with the semiconductor switching element in which the offset is not set. Also, the maximum potential of the gate control output signal in the semiconductor switching element can be increased.

In the first place, the variation of the threshold voltage of each semiconductor switching element 101 is the variation of the potential difference from the maximum output potential of the gate control output signal to each semiconductor switching element 101 to the threshold voltage. Therefore, a difference occurs in the timing of turning off the gate control output signal. Therefore, by adjusting the timing of turning off such a gate control output signal, it is possible to reduce the bias of the voltage and current distribution due to the variation in the threshold voltage.

The gate drive circuit 1 with an offset circuit according to the first embodiment operates the maximum output potential of the gate control output signal to change the maximum output potential of the gate control output signal to the threshold voltage. The potential difference is manipulated, which is apparently equivalent to the manipulation of the threshold voltage. That is, the offset circuit 3 in the first embodiment is capable of indirectly operating the threshold voltage of the semiconductor switching element 101.

Therefore, when there are a plurality of semiconductor switching elements 101, the offset circuit 3 displaces the difference between the threshold voltage of one of the semiconductor switching elements 101 and the threshold voltage of the other semiconductor switching element 101. The offset is set as an offset amount and the potential of the gate control output signal is changed to turn off the gate control output signal output from the gate drive circuit with this offset setting, and the gate drive circuit with no offset setting. It becomes possible to match the turn-off timings of the gate control output signals output from the plurality of semiconductor switching elements 1 as a result.
It is possible to eliminate the uneven distribution of the voltage and the current due to the variation in the threshold value of 01.

(Second Embodiment) FIG. 3 is a circuit diagram for explaining another gate drive circuit to which the present invention is applied.

In the second embodiment, the offset setting of the offset circuit 3 in the gate drive circuit with offset circuit 1 can be controlled by an offset setting signal 11 from the outside.

This makes it possible to set the offset dynamically. That is, it is possible to dynamically operate the apparent threshold voltage of the semiconductor switching element 101, and even if the threshold voltage changes due to a change in ambient temperature, for example, By changing the amount of displacement of the potential of the gate control output signal in accordance with the above, it becomes possible to respond sequentially to changes in the difference in the timing of turning off the gate control output signal.

(Third Embodiment) FIG. 4 is a circuit diagram showing the structure of a power conversion device to which the present invention is applied.

This power conversion device has two semiconductor switching elements 101a and 101b connected in series, and each semiconductor switching element 101a and 101b.
Similarly to the above-described first embodiment, b is driven by the gate drive circuits 1a and 1b with an offset circuit via the gate resistors 105a and 105b.

The operation of the power conversion device according to the third embodiment will be described.

FIG. 5 is a drawing showing the gate voltage and collector voltage of each semiconductor switching element in a power converter in which semiconductor switching elements having different threshold voltages are connected in series. FIG. 5A shows an offset in the gate control output signal. When not set, FIG. 5B shows the case where an offset is set in the gate control output signal.

When no offset is set in the gate control output signal, as shown in FIG. 5A, the gate voltage in the semiconductor switching element having the higher threshold voltage becomes higher, and the collector voltage becomes higher accordingly.

On the other hand, as shown in FIG. 5B, when a positive offset is set for the output potential of the semiconductor switching element having the higher threshold voltage, the potential difference between the maximum potential of the gate control output signal and the threshold voltage becomes. Since it becomes large, the threshold voltage of the semiconductor switching element in which the positive offset is set apparently becomes low. As a result, there is no difference in the collector voltage of the semiconductor switching element.

Therefore, in the power converter in which the two semiconductor switching elements 101a and 101b are connected in series, by applying a positive offset to the output potential supplied to the semiconductor switching element having the higher threshold voltage, It is possible to improve the bias of the voltage sharing in series connection due to the variation in the threshold voltage.

(Fourth Embodiment) FIG. 6 is a circuit diagram showing the configuration of another power converter to which the present invention is applied.

In this power conversion device, two semiconductor switching elements 101a and 101b are connected in parallel, and each semiconductor switching element 101a and 101b is connected.
Similarly to the above-described first embodiment, b is driven by the gate drive circuits 1a and 1b with an offset circuit via the gate resistors 105a and 105b.

The operation of the power conversion device according to the fourth embodiment will be described.

FIG. 7 is a drawing showing the gate voltage and collector current of each semiconductor switching element in a power converter in which semiconductor switching elements having different threshold voltages are connected in parallel. FIG. 7A shows an offset in the gate control output signal. When not set, FIG. 7B shows the case where an offset is set in the gate control output signal.

When no offset is set in the gate control output signal, as shown in FIG. 7A, the gate voltage in the semiconductor switching element having the higher threshold voltage becomes higher, and the collector current decreases accordingly.

On the other hand, as shown in FIG. 7B, when a positive offset is set to the output potential of the semiconductor switching element having the higher threshold voltage, the potential difference between the maximum potential of the gate control output signal and the threshold voltage becomes. Since it becomes large, the threshold voltage of the semiconductor switching element in which the positive offset is set apparently becomes low. As a result, there is no difference in the collector current of the semiconductor switching element.

Therefore, in the power converter in which the two semiconductor switching elements 101a and 101b are connected in parallel, by applying a positive offset to the output potential supplied to the semiconductor switching element having the higher threshold voltage, It is possible to improve the bias of current sharing in parallel connection due to the variation in the threshold voltage.

Although the embodiments to which the present invention is applied have been described above, the present invention is not limited to these embodiments.

For example, the power converters in the above-described embodiments have been described by connecting two semiconductor switching elements in series and connecting them in parallel, respectively. It can be applied even if it is connected in series or in parallel.

Further, the power converters in the above-described embodiments are provided with the gate drive circuit with the offset circuit in both of the two semiconductor switching elements. However, when there are two semiconductor elements, the gate drive circuit with the offset circuit is provided. Is
A gate drive circuit without a conventional offset circuit may be provided in one of the semiconductor switching elements, and the other semiconductor switching element may be provided. This is because, as described above, in the offset circuit, the potentials corresponding to the threshold values of the two semiconductor switching elements are displaced, so that providing the offset circuit in only one of the thresholds causes the threshold of the two semiconductor switching elements to be changed. It is possible to eliminate the difference in value voltage apparently.

Needless to say, various modifications can be made by those skilled in the art.

[0053]

As described above, according to the present invention,
When a large number of semiconductor switching elements are connected, it is possible to suppress variations in the switching of each semiconductor switching element due to variations in the threshold voltage of the semiconductor switching elements with a simple configuration. It is possible to improve the bias of the voltage sharing and the current sharing of the elements.

Further, according to the present invention, when a large number of semiconductor switching elements are connected, it is possible to suppress variation in switching of each semiconductor switching element due to variation in threshold voltage of the semiconductor switching element. By using the gate drive circuit, it is possible to improve the performance deterioration and the reliability deterioration of the power conversion device.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a gate drive circuit according to a first embodiment to which the present invention is applied.

FIG. 2 is a diagram illustrating a gate control output signal.

FIG. 3 is a circuit diagram of a gate drive circuit according to a second embodiment of the present invention.

FIG. 4 is a circuit diagram of a power conversion device according to a third embodiment of the present invention.

FIG. 5 is a diagram showing a gate voltage and a collector voltage of each semiconductor switching element in a power conversion device in which semiconductor switching elements having different threshold voltages are connected in series.

FIG. 6 is a circuit diagram of a power conversion device according to a fourth embodiment of the present invention.

FIG. 7 is a diagram showing a gate voltage and a collector current of each semiconductor switching element in a power conversion device in which semiconductor switching elements having different threshold voltages are connected in parallel.

FIG. 8 is a circuit diagram showing a conventional gate drive circuit.

[Explanation of symbols]

1, 1a, 1b Gate drive circuit with offset circuit 3 offset circuit 101, 101a, 101b Semiconductor switching element 103 gate drive circuit

Continued front page    (72) Inventor Ichiro Omura             1st Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa             Ceremony Company Toshiba Microelectronics Sen             Inside (72) Inventor Tomoichi Domon             1st Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa             Inside the Toshiba Research and Development Center F-term (reference) 5H740 BA11 BB01 BB05 JA01 JB01                       KK01 LL01 MM01

Claims (4)

[Claims] 1. A gate drive circuit comprising an offset means for displacing the potential of a gate control output signal for driving a semiconductor switching element. 2. The gate drive circuit according to claim 1, wherein the offset means changes the potential of the gate control output signal according to an offset setting signal from the outside. 3. A power conversion device comprising a plurality of semiconductor switching elements connected in series, which are driven by the gate drive circuit according to claim 1. 4. A power conversion device comprising a plurality of semiconductor switching elements driven in parallel by the gate drive circuit according to claim 1 or 2.