JPH09172065A - Dielectric isolating substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a dielectric isolating substrate whose warp is little. SOLUTION: A dielectric isolating substrate 1 is composed of a polysilicon layer 2a deposited by a vapor growth (CVD) method, and a polysilicon later 2b whose crystal grain diameter is smaller than that of the polysilicon layer 2a. In this case on the surface of the polysilicon layer 2b, single crystal silicon islands 4, made out of single crystal silicon and insulated individually electrically, whose sides and bottoms are covered with silicon oxide films 3 are arranged by a desired pattern. Accordingly, crystal grain boundaries become fewer, sine the grains of the polysilicon layer 2a are made larger than those of the polysilicon layer 2b. it becomes possible to prevent the shrinkage of the polysilicon layer 2a caused by the mutual uniting of grains, and the expansion of the polysilicon layer 2a caused by the diffusion of oxygen in an oxidizing process, and the warpage of the dielectric isolating substrate 1 can be lessened.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dielectric isolation substrate, and more particularly to a structure for reducing warpage of a dielectric isolation substrate.

[0002]

2. Description of the Related Art FIG. 5 shows a dielectric isolation substrate 1 according to a conventional example.
FIG. A conventional dielectric isolation substrate 1 has a plurality of single crystal silicon layers formed on the surface of a polysilicon layer 2f of a polysilicon substrate which is formed by separating into two polysilicon layers 2e and 2f by a silicon oxide film (SiO ₂ ) 3. The single crystal silicon island 4 is formed by being surrounded by the silicon oxide film 3.

In many cases, the polysilicon substrate is generally separated into two or more layers by the silicon oxide film 3. At this time, the crystal grain size (grain) of the polysilicon layer forming each layer separated into multiple layers is formed to be approximately the same throughout the layers.

[0004]

However, in the dielectric isolation substrate having the above-mentioned structure, the dielectric isolation substrate is formed on the substrate in the polysilicon deposition process and the subsequent oxidation process of forming the device in the single crystal silicon island 4. Warpage occurs, which causes troubles in the transport system of semiconductor manufacturing equipment and deterioration of accuracy in photolithography.

The cause of the warp of the substrate in the polysilicon deposition process in the manufacturing process of the dielectric isolation substrate 1 is that adjacent grains are coalescing with each other when polysilicon is deposited at a high temperature. A contraction phenomenon is considered to be caused, and the cause of the warp of the substrate that occurs when the dielectric isolation substrate 1 is oxidized is that oxygen that has entered from the polysilicon side diffuses to the boundaries (grain boundaries) between the grains. The expansion of polysilicon due to

The present invention has been made in view of the above points, and an object thereof is to provide a dielectric isolation substrate having a small warp.

[0007]

According to the first aspect of the present invention,
In a dielectric isolation substrate comprising a polycrystalline semiconductor layer and a single crystal semiconductor layer formed on the polycrystalline semiconductor layer via a dielectric layer, the polycrystalline semiconductor layer is formed in a thickness direction of the substrate of 2
The second polycrystal is formed by separating into two layers, and the layer on the single crystal semiconductor layer side of the two layers is a first polycrystal semiconductor layer and the other is a second polycrystal semiconductor layer. The crystal grain size of the semiconductor layer is larger than that of the first polycrystalline semiconductor layer.

According to a second aspect of the invention, in the dielectric isolation substrate according to the first aspect, a dielectric layer is formed between the first polycrystalline semiconductor layer and the second polycrystalline semiconductor layer. It is characterized by that.

According to a third aspect of the present invention, in the dielectric isolation substrate according to the first or second aspect, the second polycrystalline semiconductor layer is a composite layer including a dielectric layer and a polycrystalline semiconductor layer. It is characterized by being composed of a single layer or multiple layers.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic sectional view showing a dielectric isolation substrate 1 according to an embodiment of the present invention. The dielectric isolation substrate 1 according to this embodiment has a polysilicon layer 2a as a polycrystalline semiconductor layer deposited by a vapor deposition (CVD) method, and a crystal grain size (grain) smaller than that of the polysilicon layer 2a. In a polysilicon substrate composed of a polysilicon layer 2b serving as a polycrystalline semiconductor layer, a side surface and a bottom surface of the polysilicon layer 2b are covered with a silicon oxide film (SiO ₂ ) 3 serving as a dielectric layer, each of which is electrically conductive. Single crystal silicon islands 4 made of single crystal silicon as a single crystal semiconductor layer insulated from each other are arranged in a desired pattern.

Here, as an example of the deposition condition of the polysilicon layer 2a, a vapor phase epitaxial growth method is used and the temperature is 1200 ° C. and trichlorosilane (SiHCl).
₃ ) Flow rate: 20 g / min., Hydrogen (H ₂ ) flow rate: 60000
sccm, film thickness 300 μm. In addition, the polysilicon layer 2
As an example of the deposition condition of b, the vapor phase epitaxial growth method is used, and the temperature is 1100 ° C., the SiHCl ₃ flow rate is 20 g / min., the H ₂ flow rate is 60000 sccm, and the film thickness is 1
00 μm. Further, as an example of the formation condition of the silicon oxide film 3, it is possible to perform pyrooxidation at a temperature of 1100 ° C. for about 2 hours.

As described above, in the present embodiment, since the grains of the polysilicon layer 2a are made larger than the grains of the polysilicon layer 2b, the crystal grain boundaries (grain boundaries) are reduced, and the polysilicon formed by the coalescence of the grains is reduced. The contraction of the layer 2a and the expansion of the polysilicon layer 2a due to the diffusion of oxygen in the oxidation step can be prevented, and the warp of the dielectric isolation substrate 1 can be reduced.

Further, since the crystal grains are small around the single crystal silicon island 4, voids or the like are not generated and the reliability of the dielectric isolation substrate 1 is not impaired.

As shown in FIGS. 2 and 3, if the silicon oxide film 3 is interposed between the plurality of polysilicon layers 2a to 2d, the polysilicon layers 2a to 2d are deposited by the silicon oxide film 3. Dielectric isolation substrate 1 generated later
The warp of the can be reduced.

As an example of a method of forming the single crystal silicon island 4 at this time, first, as shown in FIGS. 4 (a) and 4 (b),
The V groove 6 is formed on one surface of the Si single crystal substrate 5, and
Silicon oxide films 3 are formed on both surfaces of the single crystal substrate 5. Then, after depositing the polysilicon layer 2b on the V-groove 6 side of the single crystal silicon substrate 5, a silicon oxide film 3 is formed on the surface of the polysilicon layer 2b, and the polysilicon layer 2a is deposited again. Finally, the polysilicon layer 2a of the Si single crystal substrate 5,
By polishing from the side where 2b is not deposited, the single crystal silicon island 4 is formed.

[0016]

According to the first aspect of the present invention, there is provided a dielectric isolation substrate comprising a polycrystalline semiconductor layer and a single crystal semiconductor layer formed on the polycrystalline semiconductor layer via a dielectric layer. The layer is divided into two layers in the thickness direction of the substrate, and of the two layers, the layer on the single crystal semiconductor layer side is the first polycrystalline semiconductor layer, and the other is the second polycrystalline semiconductor layer. Since the crystal grain size of the second polycrystalline semiconductor layer is made larger than that of the first polycrystalline semiconductor layer, the crystal grain boundaries (grain boundaries) can be reduced, and it is It is possible to prevent the second polycrystalline semiconductor layer from contracting and the second polycrystalline semiconductor layer from expanding due to oxygen diffusion in the oxidation step. Further, since the crystal grains are small around the single crystal semiconductor layer, voids are generated. Dielectric separation group Of no longer impair the reliability, it is possible to provide a small warpage dielectric isolation substrate.

According to a second aspect of the invention, in the dielectric isolation substrate according to the first aspect, the dielectric layer is formed between the first polycrystalline semiconductor layer and the second polycrystalline semiconductor layer. The body layer can reduce the warp of the substrate that occurs after the polycrystalline semiconductor layer is deposited.

According to a third aspect of the present invention, in the dielectric isolation substrate according to the first or second aspect, the second polycrystalline semiconductor layer is a single composite layer composed of a dielectric layer and a polycrystalline semiconductor layer. Since it is composed of multiple layers or multiple layers, the dielectric layer can further reduce the warp of the substrate that occurs after the deposition of the polycrystalline semiconductor layer.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing a dielectric isolation substrate according to one embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view showing a dielectric isolation substrate according to another embodiment of the present invention.

FIG. 3 is a schematic sectional view showing a dielectric isolation substrate according to another embodiment of the present invention.

FIG. 4 is a process drawing of forming a dielectric isolation substrate according to the present embodiment.

FIG. 5 is a schematic sectional view showing a dielectric isolation substrate according to a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Dielectric isolation substrate 2a-2f Polysilicon layer 3 Silicon oxide film 4 Single crystal silicon island 5 Si single crystal substrate 6 V groove

Claims (3)

[Claims] 1. A dielectric isolation substrate comprising a polycrystalline semiconductor layer and a single crystal semiconductor layer formed on the polycrystalline semiconductor layer via a dielectric layer, wherein the polycrystalline semiconductor layer is formed in a thickness direction of the substrate. In addition to the two separate layers,
Of the layers, the layer on the single crystal semiconductor layer side is the first polycrystalline semiconductor layer and the other is the second polycrystalline semiconductor layer, and the second polycrystalline semiconductor layer is the second polycrystalline semiconductor layer.
2. The dielectric isolation substrate, wherein the crystal grain size of the polycrystalline semiconductor layer is larger than that of the first polycrystal semiconductor layer. 2. The dielectric isolation substrate according to claim 1, wherein a dielectric layer is formed between the first polycrystalline semiconductor layer and the second polycrystalline semiconductor layer. 3. The first polycrystalline semiconductor layer according to claim 1, wherein the second polycrystalline semiconductor layer is composed of a single layer or a multi-layer of a composite layer composed of a dielectric layer and a polycrystalline semiconductor layer. 2. The dielectric isolation substrate according to 2.