JPH09172023A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an IC of high speed bipolar transistors by forming these transistors and elements having a low resistance poly-Si film on the same substrate. SOLUTION: A poly-Si film 21 is formed on a substrate 11 on which the collector layer 11a of bipolar transistors is formed, an impurity is introduced into the film 21 and it is heat-treated to activate the impurity. The film 21 is patterned to form resistance elements made from the layer 21a contg. the activated impurity on the surface of a substrate 11. A first semiconductor layer 12 formed on the substrate 11 is patterned to form a base layer 12a and second semiconductor layer 13 laminated on the layer 12 is patterned to form an emitter layer 13a whereby bipolar transistors 22 and resistance elements composed of the layer 21a are formed on the surface of the same substrate 11, without being affected by the activating heat treatment of the impurity in the layer 21a on the crystalline state and impurity diffusion state of the base layer 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a semiconductor formed by forming an element having a polysilicon layer containing activated impurities on the same substrate and a mesa type bipolar transistor. The present invention relates to a method of manufacturing a device.

[0002]

2. Description of the Related Art In order to increase the operating speed of a bipolar transistor, it is necessary to increase the maximum cutoff frequency (hereinafter referred to as fTmax) by narrowing the base width. However, if the base width is made narrower, the breakdown voltage between the emitter and collector deteriorates, and punch-through easily occurs. Therefore, in order to increase fTmax of the bipolar transistor, it is necessary to provide a shallow base layer with a high impurity concentration. . Generally, an impurity diffusion layer formed by introducing impurities by ion implantation has been used for the base layer. However, when introducing impurities by ion implantation,
Due to the problem of channeling, there is a limit to making the depth of the impurity diffusion layer shallow, and in a bipolar transistor having a base layer formed by this, fTmax = 30 to
The upper limit was 40 GHz.

Therefore, a method of forming a base layer has been proposed in which a silicon film containing impurities is epitaxially grown on a substrate made of silicon and the silicon film is patterned. According to this method, it is possible to make the depth of the base layer shallow and the concentration of impurities high as compared with the method of forming the base layer by ion implantation. It has been reported that the bipolar transistor having the base layer formed by the above method has fTmax of about 50 GHz. Further, the base layer 12a is
It may be formed by epitaxially growing a Si-Ge (silicon-germanium: SiGex) film containing impurities and patterning the Si-Ge film. The hetero-bipolar transistor having the base layer formed in this manner has a narrower band gap in the base than the bipolar transistor in which each layer is formed of only silicon, and thus the emitter concentration can be set low. Therefore, it is possible to prevent a decrease in hFE and a decrease in breakdown voltage between the emitter and the base due to the bandgap narrowing. It has been reported that the fTmax of the hetero-bipolar transistor having such a structure reaches about 100 GHz.

[0004]

In recent years, semiconductor devices have been highly integrated and highly functionalized, and in the field of information and communication, downsizing of communication devices and higher communication speed have been demanded. In order to achieve this, it is necessary to form the bipolar transistor having the shallow base layer formed as described above and other elements on the same substrate, and various steps are required in the formation process of the bipolar transistor. Is added. Then, some of the added steps involve high temperature treatment. For example, the gate of a MOS transistor formed on the same substrate as the bipolar transistor, the emitter and base of the bipolar transistor,
When the collector electrode, the resistor element, and the like are formed of polysilicon, it is necessary to activate the impurities in the polysilicon by performing high-concentration impurity doping and heat treatment at high temperature.

However, the impurities introduced into the Si film and the Si-Ge film are diffused when a high temperature is applied. Therefore, even if each of the above films is formed into a thin film by the epitaxial technique, it becomes impossible to maintain the diffusion state of the impurities during the film formation, that is, the thinness of the film due to the addition of the heat treatment step. Further, when the Si-Ge film is used as the base layer, the lattice constant of Ge atoms is about 4% larger than the lattice constant of Si atoms. Therefore, the Si-Ge film is formed on the Si substrate. At, the internal stress occurs at the interface. Therefore, when a heat treatment process is applied after forming the Si-Ge film on the Si substrate, the Si-Ge film undergoes plastic deformation so as to relieve the internal stress, thereby crystallizing in the Si-Ge film. There was a problem that defects occurred. Since the internal stress increases as the Ge composition ratio increases, the temperature resistance decreases as the Ge composition ratio increases. On the other hand, the band gap decreases as the Ge composition ratio increases. From the above, the epitaxial film (Si
The process temperature applied to the substrate after forming the (Ge film or Si film) will limit the effect of forming the shallow base layer as described above.

[0006]

Therefore, a method of manufacturing a semiconductor device according to the present invention is directed to a semiconductor device in which an element having a polysilicon layer containing activated impurities and a bipolar transistor are formed on the same substrate. In the manufacturing method,
The step of forming the base layer of the bipolar transistor on the substrate after performing the step of forming the polysilicon layer on the substrate is a means for solving the above problems. According to the method of manufacturing a semiconductor device described above, after the polysilicon layer is formed on the substrate, the base layer of the bipolar transistor is formed on the substrate. Therefore, the base layer is formed on the substrate without being affected by the step of forming the polysilicon layer containing the activated impurities. Therefore, even if the impurities in the polysilicon layer are activated by heating, the heating does not affect the base layer. Therefore, the crystalline state and the impurity diffusion state of the base layer are maintained in the state when the base layer was formed.

Further, a method of manufacturing a semiconductor device according to the present invention
When the element and the bipolar transistor are formed on the same substrate, a polysilicon film containing activated impurities is deposited and formed, and then the polysilicon film is patterned, or in the formed polysilicon film. Forming the polysilicon layer by introducing impurities activated by plasma doping into the polysilicon and then patterning the polysilicon film is a means for solving the above problems. According to this method, a polysilicon film containing activated impurities is formed without performing activation heat treatment. From this, even if the bipolar transistor is already formed on the substrate,
The polysilicon layer is formed without changing the crystalline state of each layer forming the bipolar transistor and the diffusion state of impurities in each layer.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION First and second embodiments of a method for manufacturing a semiconductor device of the present invention will be described below. In the description of each embodiment, the same components will be denoted by the same reference numerals, and overlapping description will be omitted. In addition, in each embodiment,
The case where the NPN bipolar transistor and the resistor element (element in the claims) formed of a polysilicon layer are formed on the same substrate will be described as an example. However, the present invention is not limited to the above, and the element is a MOS transistor having a gate electrode made of a polysilicon layer, or a bipolar transistor having an emitter electrode, a base electrode and a collector electrode made of a polysilicon layer. As described above, the low resistance polysilicon layer may be used as a part of the component. Further, the NPN bipolar transistor may be a PNP bipolar transistor, in which case the conductivity type in the following description is reversed.

FIG. 1 is a manufacturing process diagram of a semiconductor device according to a first embodiment to which claims 1 and 3 of the present invention are applied. The semiconductor device is a substrate 11 made of silicon shown in FIG. 1 (6). Is formed on the surface side of. Here, first, the procedure for forming the substrate 11 will be described with reference to the process chart of FIG.

As shown in FIG. 2A, P-type <111>
A silicon substrate (hereinafter referred to as a silicon substrate) 101 is prepared, and a silicon oxide film 102 having a thickness of about 300 nm is formed on the surface thereof by thermal oxidation. Next, using a resist pattern (not shown) as a mask, the silicon oxide film 102 (the portion indicated by the chain double-dashed line in the figure) in the portion where the N ⁺ buried layer of the bipolar transistor is to be formed is etched away. Next, antimony oxide (Sb
_By vapor phase diffusion using ₂ O ₃ ) as a solid diffusion source, antimony is diffused into the surface layer of the silicon substrate 101 in the portion where the silicon oxide film 102 is removed to form the N ⁺ buried layer 103. Here, the buried collector layer 10
3 sheet resistance ρs = 20 to 50Ω / □, depth Xj = 1
Diffusion is performed so as to have a size of about μm to 2 μm.

Next, as shown in FIG. 2 (2), after removing the silicon oxide film (102), the resistivity = 0.3 Ωcm to 5.0 Ωcm and the thickness = using an epitaxial technique.
A semiconductor layer 104 of N-type silicon having a thickness of about 0.7 to 2.0 μm is formed on the silicon substrate 101.

Thereafter, as shown in FIG. 2C, the surface of the semiconductor layer 104 is oxidized to form a buffer oxide film 105, which is then formed on the upper surface of the buffer oxide film 105 by a low pressure CVD (Chemical Vapor Deposition) method. A silicon nitride film 106 is formed. The film thickness of these films is determined by the length of the bird's beak of a LOCOS (Local Oxidation of Silicon) oxide film to be formed later and the controllability of stress and defect generation due to LOCOS oxidation. ˜50 nm, and the silicon nitride film 106 is set to about 50 nm to 100 nm. Next, in the figure, 2 of the silicon nitride film 106 and the buffer oxide film 105 on the region where LOCOS oxidation is performed by etching using a resist pattern (not shown) as a mask.
The portion indicated by the dotted line is removed, and the
The portion indicated by the dotted chain line is etched until the thickness is about 1/2 of the film thickness of the LOCOS oxide film. This allows the LOCO
The surface of the substrate after forming the S oxide film is made flat.

Then, as shown in FIG. 2 (4), 100
By performing steam oxidation at 0 ° C. to 1050 ° C. for 2 hours to 6 hours, L having a film thickness of 0.8 μm to 1.5 μm is formed on the surface of the semiconductor layer 104 exposed from the silicon nitride film 106.
The OCOS oxide film 107 is grown. LOC in this process
The N-type collector layer 11a is formed by the semiconductor layer 104 portion remaining without being OS-oxidized and the N ⁺ buried layer 103. Then, the substrate 11 including the silicon substrate 101, the collector layer 11a, and the LOCOS oxide film 107 is formed. After that, the silicon nitride film 106 is removed by wet etching using hot phosphoric acid, and then the substrate 1
1 is formed with a resist pattern 108 having a shape that opens on the extraction region of the collector layer 11a. Then, ion implantation using the resist pattern 108 as a mask introduces an N-type impurity for forming an extraction region in the surface portion of the collector layer 11a. Here, N
Using phosphorus (P) as a type impurity, 40 keV-100
About 10 ¹⁵ pieces / cm ² to 10 ¹⁶ pieces / cm ² are introduced with an implantation energy of keV.

Next, after removing the resist pattern 108, a silicon oxide film (not shown here) having a film thickness of about 100 to 600 nm is formed on the substrate 11 by the CVD method. Then, activation annealing of the phosphorus introduced into the surface portion of the substrate 11 by the ion implantation is performed.
Next, a resist film (not shown) is applied on the silicon oxide film. After that, RIE (Reactive Ion Etc
Hing) method is used to etch back the resist film and silicon oxide film until the collector layer 11a is exposed.
The surface of the substrate 11 is flattened.

Next, as shown in FIG. 2 (5), 900 ° C.
By performing a thermal oxidation process of about 10 to 30 on the exposed surface of the collector layer 11a formed on the front surface side of the substrate 11.
An oxide film 109 having a film thickness of about nm is grown. Then
After the resist pattern 110 is formed on the substrate 11, the element isolation region 11 of the bipolar transistor is formed by ion implantation using the resist pattern 110 as a mask.
A P-type impurity for forming 1 is introduced. afterwards,
The resist pattern 110 is removed. The steps up to this point are carried out in the same procedure as the conventional bipolar transistor formation.

The following steps shown in FIGS. 1 (6) to 1 (10) are characteristic steps in the method of manufacturing a semiconductor device described in the first embodiment, and are performed in the following procedure. . First, a resist pattern (not shown) having a shape exposing the portion where the resistor element is formed is formed on the substrate 11 on which the collector layer 11a is formed. After that, the substrate 1 is formed by the RIE method using this resist pattern as a mask.
The LOCOS oxide film 107 portion of No. 1 is 200 to 300 nm
By etching to a depth to form a recess on the surface of the substrate 11.

Next, after removing the resist pattern, a polysilicon film 21 is formed on the front surface side of the substrate 11 by the CVD method. The polysilicon film 21 is formed to have a film thickness such that the concave portion on the surface of the substrate 11 is filled, that is, a film thickness of 200 to 300 nm here. After that, impurities such as boron are introduced into the polysilicon film 21 by ion implantation. The amount of boron ions introduced is set to such an extent that a desired resistance value can be obtained in the polysilicon layer formed of the polysilicon film 21. Then, heat treatment is performed at a high temperature of 900 ° C. to 1100 ° C. to activate the impurities introduced into the polysilicon film 21, thereby forming the polysilicon film 21 containing the activated impurities on the substrate 11. To do. The polysilicon film 21 may be formed by introducing impurities into the polysilicon film formed by the CVD method by the plasma doping technique. Further, when the polysilicon film 21 is formed by the CVD method, impurities are added to the film forming gas to deposit a polysilicon film (doped polysilicon) 21 containing activated impurities. It may be a film.

After that, C using the oxide film 109 as a stopper
By the MP (Chemical Mechanical Polishing) method, the portion of the polysilicon film 21 indicated by the chain double-dashed line in the figure is polished from the surface side to flatten the surface of the substrate 11. As a result, a resistor element made of the polysilicon layer 21a is formed on the surface of the substrate 11 in a state where the concave portion on the surface of the substrate 11 is filled. The polysilicon layer 21a may be formed on the upper surface of the substrate 11. When forming such a polysilicon layer 21a, the polysilicon film 21 formed on the substrate 11 is patterned by RIE using a resist pattern as a mask.

Next, as shown in FIG. 1 (7), the substrate 11
After cleaning the surface of MBE (Molecular Beam Epita
xy), gas source MBE, UHV (Ultra High Vacuum)
The first semiconductor layer 12 is epitaxially grown on the substrate 11 by -CVD or LP (Low Pressure) -CVD method. The first semiconductor layer 12 is made of Si-Ge (silicon-germanium) or S containing P-type impurities.
i (silicon). Then, in order to keep the surface clean, the second semiconductor layer 13 is epitaxially grown following the growth of the first semiconductor layer 12.
The second semiconductor layer 13 is a Si layer containing N-type impurities. In the film formation, the first semiconductor layer 12 and the second semiconductor layer 13 are single crystal layers on the portion where the single crystal silicon is exposed in the film formation base of the first semiconductor layer 12. On the other hand, the film-forming base is an oxide film (LOCOS).
Above the oxide film 107) and the polysilicon layer 21a, the first semiconductor layer 12 and the second semiconductor layer 13 are microcrystalline layers.

After the above, as shown in FIG. 1 (8), the second
A resist pattern 112 is formed on the semiconductor layer 13, and the second semiconductor layer 13 is etched using the resist pattern 112 as a mask. Thereby, the emitter layer 13a made of the second semiconductor layer 13 is formed.

Next, as shown in FIG. 1 (9), after removing the resist pattern (112), a resist pattern 113 having a shape covering the base layer formation portion is formed on the first semiconductor layer 12. . Then, the first semiconductor layer 12 is etched using the resist pattern 113 as a mask, whereby the base layer 1 made of the first semiconductor layer 12 is etched.
2a is formed. As described above, the collector layer 11a formed on the front surface side of the substrate 11 and the collector layer 11a
a base layer 12a formed on the substrate 11 in a state of being connected to a and a mesa bipolar transistor 22 formed of an emitter layer 13a formed on the base layer 12a, and a resistor formed of a polysilicon layer 21a. The element and the element are formed on the front surface side of the same substrate 11.

After that, the resist pattern 113 is removed, and as shown in FIG.
An insulating film 25 having a thickness of about 300 nm is formed on the substrate 11 in a state of covering the emitter layer 13a and the base layer 12a. Then, a resist pattern (not shown here) is formed on the insulating film 25, and contact holes 26 reaching the collector layer 11a, the base layer 12a, the emitter layer 13a, and the polysilicon layer 21a are formed by RIE using the resist pattern as a mask. To do.

Next, after removing the resist pattern, a barrier metal (not shown) is formed, and then aluminum is sputter-deposited. After that, the aluminum and the barrier metal are RIEed by RIE using a resist pattern (not shown) as a mask, and the collector layers 11a,
A wiring 27 connected to the base layer 12a, the emitter layer 13a, and the polysilicon layer 21a is formed to form a semiconductor device.

In the method of manufacturing a semiconductor device described above, the process shown in FIG.
After forming the polysilicon layer 21a on the front surface side of the substrate 11 by the procedure described with reference to (6), FIGS.
The base layer 12a of the bipolar transistor is formed on the substrate 11 by the procedure described above. For this reason, this base layer is formed without being affected by the step of forming the polysilicon layer 21a (step of heat treatment for activating impurities in the polysilicon layer 21a). Therefore, the crystalline state of the base layer 21 and the impurity diffusion state are
A high-speed bipolar transistor 21 having a base layer 21 having a narrow base width and a high impurity concentration, which is held in the state in which the first semiconductor layer 12 forming the base layer 21 is formed.
It is possible to form the resistor element made of the polysilicon layer 21a on the same substrate 11 as described above.

Next, FIG. 3 is a manufacturing process diagram of a semiconductor device according to a second embodiment to which claims 2 and 4 of the present invention are applied. As shown in FIG. It is formed on the substrate 11 made of silicon. This substrate 11 is
Similar to the first embodiment, it is formed by the procedure described with reference to FIGS. A procedure for forming a bipolar transistor and a polysilicon layer to be a resistor on the surface side of the substrate 11 on which the collector layer 11a is formed as described above will be described below.

First, in the steps shown in FIGS. 3 (6) to 3 (8), FIG. 1 (7) in the manufacturing procedure of the first embodiment is used.
To (9), the base layer 12a formed by patterning the epitaxially grown first semiconductor layer 12 and the second semiconductor continuously epitaxially grown on the first semiconductor layer 12 in the same manner as described above. An emitter layer 13 a formed by patterning the layer 13 is formed on the substrate 11. Thereby, the collector layer 11a formed on the front surface side of the substrate 11, the base layer 12a formed on the substrate 11 in a state of being connected to the collector layer 11a,
A mesa type bipolar transistor 22 including the emitter layer 13a formed on the base layer 12a is formed.

Next, as shown in FIG. 3 (9), a polysilicon film 21 is formed on the substrate 11 so as to cover the collector layer 11a, the base layer 12a and the emitter layer 13a. Here, CV using a film-forming gas containing impurities
By the D method, a polysilicon (doped polysilicon) film 21 containing impurities is deposited and formed in a film thickness of about 200 to 300 nm. The content of the impurities is set to such an extent that a desired resistance value can be obtained in the polysilicon layer composed of the polysilicon film 21. In addition, here, CV
Impurities activated by the plasma doping technique may be introduced into the polysilicon film 21 formed by the D method.

Next, after forming a resist pattern (not shown) on the polysilicon film 21, the polysilicon film 21 is patterned by etching using the resist pattern as a mask, whereby the collector layer 11a and the base are formed. A polysilicon layer 21a insulated from the layer 12a and the emitter layer 13a is formed on the substrate 11. The polysilicon layer 21a may be embedded on the front surface side of the substrate 11 as shown in the first embodiment. Such a polysilicon layer 21a is formed by the same procedure as described with reference to FIG. 1 (6) in the first embodiment.

As described above, the bipolar transistor 22 and the resistor element formed of the polysilicon layer 21a are formed on the front surface side of the same substrate 11. The subsequent process is
By performing the same procedure as the procedure described with reference to FIG. 1 (10) in the manufacturing process of the first embodiment, as shown in FIG.
A semiconductor device as shown in 0) is formed.

In the method of manufacturing the semiconductor device described above, FIG.
As shown in (9), the polysilicon film 21 containing the activated impurities is formed at a low temperature without performing the activation heat treatment. From this, at this point, the polysilicon layer which has already been formed on the substrate 11 does not change the crystalline state of the collector layer 11a, the base layer 12a, and the emitter layer 13a and the diffused state of the impurities without changing the polysilicon layer. 21a is formed. Therefore, as in the first embodiment, the high-speed bipolar transistor 21 having the base layer 21 having a narrow base width and a high impurity concentration and the polysilicon layer 21a can be formed on the same substrate 11.

[0031]

As described above, according to the first aspect of the present invention.
Alternatively, according to the method of manufacturing a semiconductor device as described in 3, a step of forming a polysilicon layer containing activated impurities on a surface side of a substrate and then forming a base layer of a mesa type bipolar transistor on the substrate is performed. By this, when the impurities in the polysilicon layer are activated by heating, it is possible to prevent the heating from affecting the base layer. Therefore, the crystalline state of the base layer and the diffused state of the impurities can be maintained in the state at the time of forming the base layer, and a high-speed bipolar transistor having a base layer with a narrow base layer and a high impurity concentration can be used as a low-resistance poly transistor. It becomes possible to form an IC by forming it on the same substrate as the device provided with the silicon layer.

According to the method of manufacturing a semiconductor device according to the second or fourth aspect of the present invention, the polysilicon layer disposed on the same substrate as the mesa type bipolar transistor is patterned by doping the polysilicon layer. Alternatively, by patterning and forming a polysilicon film into which activated impurities are introduced by plasma doping, the polysilicon layer is formed without changing the crystalline state of each layer constituting the bipolar transistor and the diffusion state of impurities in each layer. Can be formed. Therefore, a high-speed bipolar transistor having a base layer having a narrow base layer and a high impurity concentration is formed on the same substrate as an element having a low-resistance polysilicon layer to form an IC.
Can be converted.

[Brief description of the drawings]

FIG. 1 is a manufacturing process diagram of a semiconductor device according to a first embodiment.

FIG. 2 is a manufacturing process diagram of a semiconductor device.

FIG. 3 is a manufacturing process diagram of the semiconductor device of the second embodiment.

[Explanation of symbols]

 11 substrate 12a base layer 21 polysilicon film 21a polysilicon layer, resistor element (element) 22 bipolar transistor

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[Procedure amendment]

[Submission date] January 22, 1996

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0010

[Correction method] Change

[Correction contents]

As shown in FIG. 2A, P-type <100>
A silicon substrate (hereinafter referred to as a silicon substrate) 101 is prepared, and a silicon oxide film 102 having a thickness of about 300 nm is formed on the surface thereof by thermal oxidation. Next, using a resist pattern (not shown) as a mask, the silicon oxide film 102 (the portion indicated by the chain double-dashed line in the figure) in the portion where the N ⁺ buried layer of the bipolar transistor is to be formed is etched away. Next, antimony oxide (Sb
_By vapor phase diffusion using ₂ O ₃ ) as a solid diffusion source, antimony is diffused into the surface layer of the silicon substrate 101 in the portion where the silicon oxide film 102 is removed to form the N ⁺ buried layer 103. Here, the buried collector layer 10
3 sheet resistance ρs = 20 to 50Ω / □, depth Xj = 1
Diffusion is performed so as to have a size of about μm to 2 μm.

Claims (4)

[Claims] 1. A method of manufacturing a semiconductor device, comprising: forming an element having a polysilicon layer containing activated impurities and a bipolar transistor on the same substrate, and forming the polysilicon layer on the substrate. And a step of forming a base layer of the bipolar transistor on the substrate, after the above step. 2. A method for manufacturing a semiconductor device, comprising: forming an element having a polysilicon layer containing activated impurities and a bipolar transistor on the same substrate, wherein the polysilicon layer contains activated impurities. Formed by patterning the polysilicon film after depositing and forming the polysilicon film, or by introducing impurities activated by plasma doping into the deposited polysilicon film and then patterning the polysilicon film A method for manufacturing a semiconductor device, comprising: 3. The method for manufacturing a semiconductor device according to claim 1, wherein the base layer is formed by epitaxially growing a semiconductor layer made of silicon and germanium containing activated impurities on a substrate, and then patterning the semiconductor layer. A method of manufacturing a semiconductor device, which is characterized by being formed as follows. 4. The method of manufacturing a semiconductor device according to claim 2, wherein the base layer is formed by epitaxially growing a semiconductor layer made of silicon and germanium containing activated impurities on a substrate, and then patterning the semiconductor layer. A method of manufacturing a semiconductor device, which is characterized by being formed as follows.