JPH09167823A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to avoid a complicatedness in the manufacturing process of a semiconductor device, such as a cutting of leads due to a stress, which is generated at the time of resin-sealing of the device, by a method wherein a polymerized plate is provided in a such a way as to oppose to a bed. SOLUTION: A second type of leads 2b are superposed on the opposite side to the side on one side of the sides of a semiconductor chip on a bed 3 via an insulating layer in addition to a first type of leads 2a and are wire-connected with pads 8b on the other side of the chip 8. Thereby, as the intervals between the first and second types of the leads 2a and 2b can be made wide, a distribution of the first and second types of the leads 2a and 2b is facilitated and the leads 2a and 2b are also formed comparatively short. As a result, as the leads 2a and 2b are also never cut by a stress, which is generated at the time of resin-sealing of a semiconductor device, and a processing of the leads 2a and 2b is also easy, a facilitation of the manufacturing work of the device can be contrived.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device using a resin-encapsulated semiconductor element container (plastic package), which has a high degree of integration and can easily be impaired. The present invention relates to a semiconductor device that achieves high performance and high reliability.

[0002]

2. Description of the Related Art Two types of materials, ceramics and plastics, are mainly used for packages that accommodate semiconductor chips in semiconductor devices. This ceramic is generally better than plastic in reliability, but is considerably more expensive. On the other hand, plastic is inexpensive and suitable for automation, and is most suitable as a package for a semiconductor chip such as a memory, which requires mass production and requires price competitiveness. As shown in FIG. 6, a conventional semiconductor device using the above plastic package is processed by processing a single metal plate 1 to form a plurality of leads 2 and beds 3.
Then, the hanging pins 4 are molded, the semiconductor chip is mounted on the upper surface of the bed 2, the pads of the semiconductor chip and the leads 2 are wire-bonded, and then the resin is sealed with the package resin 5, and then the leads 2 are formed. The semiconductor device is configured by separating the bed 3 from the metal plate (frame) 1 and bending the leads 2 into a desired shape.

One of the forms of the memory package of this semiconductor device is a ZIP (Zigzag Inline Package) as shown in FIG. This is lead 2
The outlet from the package resin 5 is concentrated on one side surface, and the leads 2 protruding from this side surface are alternately bent up and down.

[0004]

However, in the case of the above-mentioned conventional example, since the metal layer is a single layer, for example, the lead and the bed cannot be polymerized, so that the layout of the lead is limited or the desired lead is not obtained. Attempting to obtain a bed that secures an area and a shape has a disadvantage that the size of the package becomes large due to the layout of the leads.

On the other hand, when trying to obtain a fixed package size, the bed becomes smaller, and therefore the chip area of the semiconductor element mounted on the bed must be made smaller.
Therefore, there is a disadvantage that the design must be performed using extremely fine dimensions. In particular, in the case of the above-mentioned ZIP, since the lead outlets are concentrated on one side, this routing is violent, leading to the inconvenience that the lead cabarancy and inductance are increased, and the bed size is reduced, and the lead is long. In such a case, there is a risk that the lead will be cut due to the stress generated at the time of resin sealing, and further processing of such an elongated lead is relatively difficult, and the manufacturing process is extremely complicated. There is also an inconvenience.

In view of the above, the present invention is capable of not only achieving a large bed size and a small package size, but also in a manufacturing process such as cutting of leads due to stress generated during resin sealing. The object of the present invention is to provide a semiconductor device which can avoid complexity and has high noise resistance and high reliability such as moisture resistance.

[0007]

In order to achieve the above object, the present invention provides a semiconductor device in which a semiconductor chip is mounted on a bed and sealed with a package resin, and a plurality of leads are projected from the package resin. The stacking plate is provided so as to face the bed.

In a semiconductor device in which a semiconductor chip having a plurality of pads on at least one side and the opposite side is mounted on a bed and resin-sealed with a package resin, and a plurality of leads are projected from one side of the package resin. The bed and the plurality of leads are divided into an upper layer portion on which the bed and the first-type leads are formed and a lower layer portion on which the second-type leads are formed, with the bending line as a boundary. After the semiconductor chip is mounted on the bed, the upper layer portion and the lower layer portion are bent along the bending line while the insulating layer is interposed between the bed and the second kind of lead. Due to this bending, the first-type leads are extended to one side of the bed while the first-type leads and the second-type leads are arranged alternately in the lead arrangement direction, while the second-type leads are disconnected. It extends through the lower side of the layer to the other side of the bed, and then the first type leads are wire-connected to the pads on one side of the semiconductor chip, while the second type leads are connected to the other side of the semiconductor chip. It is characterized by wire connection to the side pads.

Further, it is characterized in that a sealing resin is used for the insulating layer. Alternatively, it is characterized in that a dielectric material different from the sealing resin is used for the insulating layer.

In the above-mentioned invention, a semiconductor element for generating a substrate potential on a semiconductor chip, for example, a dynamic R
In the AM, the countermeasure against the noise of the substrate potential is an important issue, but the bed can have a large capacitance with the power supply terminal or the ground terminal, and the substrate potential can be stabilized.

In addition to the first-type leads, the wires are stacked on the opposite side of the semiconductor chip of the bed via an insulating layer, extended to the other side of the bed, and wire-connected to the pad of the other side of the semiconductor chip. Second type of leads are provided. In this way, the second-type leads are arranged so as to overlap the bed, and are also arranged in a hierarchical manner with respect to the first-type leads, so that the second-type leads reach the other side of the bed. A structure is realized in which the wire is extended and connected to a pad on the other side of the chip.

Therefore, even when each wire is connected, this connection work can be performed on both the one side and the other side of the bed. Therefore, in an extreme case, the interval between the leads should be half that of the conventional example. You can Therefore, even when a bed having a desired area is to be obtained, the size of the package resin is half that of the conventional example, unlike the conventional case.
Conversely, even if a fixed package size is to be obtained, a bed twice as large as the conventional example can be secured, and the area of the semiconductor chip can be increased. Therefore, greater freedom can be given to the layout of the lead and the bed. Moreover, in the manufacturing process, the spacing between the leads can be increased, so that the leads can be routed easily. Since the leads are formed relatively short, they can be cut by stress during resin sealing. Further, since the lead is easy to process, the manufacturing operation can be simplified.

The first and second types of leads are arranged alternately in the arrangement direction of the leads, while the first type of leads are extended to one side of the bed, while the second type of leads are under the insulating layer. Side to the other side of the bed. That is, the first type of lead is relatively short and extends to the vicinity of the bed, and the second type of lead adjacent to the first type of lead is relatively long and extends to the far side of the bed. More specifically, the first type and second type leads are arranged such that short ones and long ones are alternately arranged. Therefore, compared with the case where the leads are sequentially arranged, the interval between the leads is relatively large, and the electromotive force induced from one lead to the other lead is extremely reduced. As a result, the electromagnetic induction is reduced. As a result, adverse effects are minimized.

Further, the first and second types of leads are formed by bending an upper layer portion and a lower layer portion which are divided from a single metal plate, and a complicated bending process is not required.
Therefore, the manufacturing operation is easy, and the resin and the like are rarely spread when the sealing resin or the like is filled, and the reliability of the semiconductor device is improved.

[0015]

1 and 2 show an embodiment of the present invention, which is adapted to the above ZIP.

That is, one sheet of metal plate 1 is processed and divided at the folding line 6 into an upper layer portion 1a serving as an upper layer metal film and a lower layer portion 1b serving as a lower layer metal film. . In the upper layer portion 1a, the first type leads 2a, the base 3 and the hanging pins 4 are laid out and formed. The first-type lead 2a is configured to extend to one side of the bed 3 and be wire-connected to the pad 8a on one side of the semiconductor chip 8. In the lower layer portion 1b, second type leads 2b that intersect the overlapping portion 7 with the base 3 are laid out and formed. The second type lead 2b is stacked on the opposite side of the semiconductor chip 8 of the bed 3 via an insulating layer, extends to the other side of the bed 3, and is wired to the pad 8b of the other side of the semiconductor chip 8. It is configured to be wired. At the time of assembly, after mounting the semiconductor chip 8 on the upper surface of the base 3, the semiconductor chip 8 is bent along the bending line 6, and the base 3 and the second metal film 1a, 1b are provided between the bent two metal films 1a, 1b. An insulating material is attached to either one of the superposed surfaces of the seed leads 2b to interpose an insulating layer so as to insulate the metal films 1a and 1b from each other.

After bending in this manner, the pad 8a of the semiconductor chip 8 and the first-type lead 2a are wire-connected by the wire 9, and at the same time, the pad 8b of the semiconductor chip 8 and the second-type lead are simultaneously connected. The wires 2b are wire-connected with the wires 9 and then sealed with the package resin 5. Then, the first type leads 2a, the second type leads 2b, and the bed 3 are separated from the metal plate (frame) 1.

At this time, in addition to the first type lead 2a, the second type
The seed lead 2b is placed on the opposite side of the semiconductor chip of the bed 3 via the insulating layer, extends to the other side of the bed 3, and is wire-connected to the pad 8b of the other side of the semiconductor chip 8. . In this way, the second type lead 2b is
The lead 2a of the first type is arranged so as to overlap with the bed 3.
Also, since the second type leads 2b are extended to the other side of the bed by arranging the leads 2b in a hierarchical manner, a wire connection to the pad 8b on the other side of the semiconductor chip 8 is realized. .

Therefore, even when each wire is connected, this connection work can be performed on both the one side and the other side of the bed 3, so that in the extreme case, the distance between the leads 2a and 2b is the same as that of the conventional example. It can be halved. Therefore, even when the bed 3 having a desired area is to be obtained, the size of the package resin is half that of the conventional example, unlike the conventional case. Conversely, even if it is intended to obtain a fixed package size, the bed 3 which is twice as large as the conventional example can be secured, and the area of the semiconductor chip 8 can be increased. Therefore, a greater degree of freedom can be given to the layout of the first-type and second-type leads 2a and 2b and the bed 3. Moreover, even in the manufacturing process, the distance between the first-type and second-type leads 2a and 2b can be increased, so that the first-type and second-type leads 2 can be formed.
It becomes easy to route a and 2b, and each lead 2a and 2b
Also, since it is formed relatively short, it will not be cut by stress during resin sealing, and the processing of each lead 2a, 2b will be easy, so that the manufacturing work will be facilitated. You can

Further, in this case, when the bent insulating layer between the two layers has a large film thickness and a low dielectric constant, the parasitic capacitance of the second type lead 2b overlapping with the bed 3 can be reduced. preferable.

The insulating film is a metal film 1 when bent.
A space may be formed between a and 1b, and a resin at the time of sealing may be filled in the space to insulate the semiconductor chip. Further, the semiconductor chip 8 is mounted on the bed 3 by bending the metal plate 1. You may do it later. FIG. 3 shows another embodiment, which is an example applied to a so-called DIP (dual in-line package), in which one metal plate 1 is separated by a bending line 6 and an upper layer portion 1a serving as an upper metal film. The lower layer portion 1b serving as a lower layer metal film is divided into two parts, the leads 2 extending in all directions are formed in the upper lower layer portion 1b, and the bed 3 and the upper and lower suspension pins 4 are formed in the lower upper layer portion 1a, respectively. At this time, this is bent along the bending line 6 and an insulating layer is interposed between the overlapping portions of the both, so that the semiconductor device is configured in the same manner as described above.

FIG. 4 shows another embodiment, which is a so-called DIP.
Another embodiment of the (dual in-line package) is shown, in which one metal plate 1 is a fold line 6 as a boundary, and an upper layer portion 1a serving as an upper metal film and a lower layer portion 1 serving as a lower metal film.
b, a bed 3 and a hanging pin 4 are formed on the upper layer portion 1a above it, and a stacking plate 10 with the bed 3 is formed on the lower layer portion 1b below it, and the hanging pin is mounted on this stacking plate 10. 4 are connected to each other, the lead 2 is arranged with the tip close to the overlapping plate 10, and the hanging terminal 4 is further connected to the ground terminal 11 or the power supply terminal.

In this way, in a semiconductor element that generates a substrate potential on a semiconductor chip, such as a dynamic RAM, countermeasures against substrate potential noise become an important issue. A capacitance can be provided, and the substrate potential can be stabilized.

Further, as shown in FIG. 5, the polymer plate 10 shown in FIG. 4 is composed of the two separate polymer plates 10a and 10b, and the hanging pin 4 of one polymer plate 10a is connected to the ground terminal 11.
In addition, by making the suspension pins 4 of the other overlapping plate 10b continuous with the power supply terminals 12, respectively, the bed 3 can be made to have a capacitance with both the ground terminal and the power supply terminal.

Incidentally, not only the substrate potential but also this capacitance can be formed between the power supply terminal and the ground terminal to reduce the power supply noise.

In such a case, it is preferable that the insulating film between the two layers is as thin as possible within the range of withstand voltage, and that the dielectric constant is high.

In the above-mentioned embodiments, all of the examples are provided with two metal layers, but three or more layers may be provided to further enhance the effect.
Further, for example, the one shown in FIG. 5 may be added to the one shown in FIG. 3 to have both effects at the same time.

Further, in the above embodiment, the folding process is included in the assembling process so that the single-layer metal plate is formed into the multi-layer (2
However, for example, a bed or a lead may be formed by using two or more metal layers from the beginning and bonding them.

In this case, it is possible to cope with the conventional assembling process by changing the manufacturing process of the lead tape in which the lead or bed pattern is formed into a tape shape and several chips are connected. In the case of a single metal layer, the lead tape manufacturing process can be dealt with as it is in the past, and one type of die is used, which is inexpensive. Need to be added.

As described above, the second type lead is
By arranging them so as to be stacked on the bed and hierarchically arranged for the first-type lead, even when trying to obtain a bed having a desired area, unlike the conventional case,
The size of the package resin is half that of the conventional example. Conversely, even if a fixed package size is to be obtained, a bed twice as large as the conventional example can be secured, and the area of the semiconductor chip can be increased. Therefore, greater freedom can be given to the layout of the lead and the bed. Moreover, in the manufacturing process as well, the spacing between the leads can be increased,
Since the lead can be easily routed and the lead is formed relatively short, it will not be cut by stress during resin encapsulation, and the lead can be easily processed. Can be facilitated.

Further, in a semiconductor element for generating a substrate potential on a semiconductor chip, for example, a dynamic RAM, countermeasures against substrate potential noise is an important issue, but a bed has a power supply terminal or a ground terminal and a large capacitance. Therefore, the substrate potential can be stabilized.

[0032]

As described above, a semiconductor element, such as a dynamic R, for generating a substrate potential on a semiconductor chip is used.
In the AM, the countermeasure against the noise of the substrate potential is an important issue, but the bed can have a large capacitance with the power supply terminal or the ground terminal, and the substrate potential can be stabilized.

[Brief description of the drawings]

FIG. 1 is a plan view showing a state in which a semiconductor chip is bonded according to an embodiment of the present invention.

FIG. 2 is a plan view showing the layout of a metal plate before bending, showing an embodiment of the present invention.

FIG. 3 is a plan view showing the layout of the metal plate before bending, showing another embodiment of the present invention.

FIG. 4 is a plan view showing the layout of the metal plate before bending, showing another embodiment of the present invention.

FIG. 5 is a plan view showing the layout of the metal plate before bending, showing another embodiment of the present invention.

FIG. 6 is a plan view showing a layout of a conventional metal plate.

7A and 7B show a conventional ZIP, in which FIG. 7A is a plan view, FIG. 7B is a side view, and FIG. 7C is a front view.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 metal plate 1a same upper layer part (metal layer) 1b same lower layer part (metal layer) 2a 1st type lead 2b 2nd type lead 3 bed 4 suspension pin 5 package resin 8 semiconductor chip 10 superposed plate 11 ground terminal 12 power supply Terminal

Claims (1)

[Claims] 1. A semiconductor device in which a semiconductor chip is mounted on a bed and sealed with a package resin, and a plurality of leads are projected from the package resin, wherein a polymer plate is provided so as to face the bed. A semiconductor device characterized in that