JPH09160528A - Micro-controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the image processing speed by generating each address in accordance with the instruction from an instruction decoder in a synchronous manner with strobe signal. SOLUTION: The instruction decoder 5' receives the instruction to read the data, and outputs selected signal to a video memory. When the instruction decoder 5' outputs the address data of line address to an address signal generating circuit 2 at the timing of the output of the line address strobe signal, the video memory receives the address data from the address signal generating circuit 2 to select the corresponding memory region. When a video memory control signal generating circuit 9' generates the column address strobe signal, the instruction decoder 5' outputs the address data of the column address to the address signal generating circuit 2 at the timing, and selects the column address present in the selected line address.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcontroller for controlling an image data control system that handles a large volume image, and more particularly to a microcontroller capable of improving processing speed.

[0002]

2. Description of the Related Art A conventional microcontroller will be described with reference to FIG. FIG. 3 is a configuration block diagram showing a conventional microcontroller and part of its peripheral portion. As shown in FIG. 3, the conventional microcontroller includes a program counter 1 and an address signal generating circuit 2.
A data input / output control circuit 3, an internal data bus 4,
Instruction decoder 5, external memory control signal generation circuit 6, and external input / output data control signal generation circuit 7
And an internal memory 8.

As a peripheral part of the microcontroller, a video memory control signal generating circuit 9 and a switch 1 are provided.
0 is illustrated. Further, although not shown, at least an external memory and a ROM storing instructions as a program are connected.

The functions of the respective parts will be specifically described below. The program counter 1 is a counter, which increments the count value at regular time intervals and outputs it to the address signal generation circuit 2. The program counter 1 resets the count value to a value input from the instruction decoder 5 described later.
Further, the program counter 1 resets the count value to a preset specific value immediately after the power is turned on.

The address signal generating circuit 2 receives an instruction from the instruction decoder 5 and outputs the count value input from the program counter 1 as an address. Further, the address signal generation circuit 2 is
Upon receiving an instruction from the instruction decoder 5, the value input from the instruction decoder 5 and the internal memory 8 is output.

The data input / output control circuit 3 is connected to an external (peripheral portion) data bus of the conventional microcontroller, and exchanges data between the peripheral portion and the internal data bus 4. The internal data bus 4 is connected to the data input / output control circuit 3, the instruction decoder 5, and the internal memory 8 and exchanges data with each other. Although not shown in FIG. 3, the internal data bus 4 is a data bus A for outputting to the outside.
It is usually separated into two (output data bus) and data bus B (input data bus) for input from the outside. Therefore, in the following, when it is necessary to make a distinction between these two, the above-mentioned code, A or B
Will be attached to distinguish.

The instruction decoder 5 receives an instruction input from the ROM in the peripheral portion via the data input / output control circuit 3 and the internal data bus 4, and in accordance with the instruction, the external memory control signal generation circuit 6 and the external input / output. A read signal (hereinafter simply referred to as a read signal) to the data control signal generation circuit 7, or
Write signal (hereinafter simply referred to as write signal), or
It outputs a selection signal. Here, the selection signal is a signal for selecting which of a specific external device, for example, an external memory, a transmission device, a disk device, or the like, to which the write command or the read command is output.

Further, the instruction decoder 5 is
While the selection signal is being output to the peripheral ROM, the address signal generating circuit 2 is caused to output the count value of the program counter 1, and the ROM in the peripheral portion is supplied via the data input / output control circuit 3 and the internal data bus 4. It receives input of instructions from.

When the instruction from the ROM uses the output from the address signal generating circuit 2 as a signal for controlling a device other than the external memory, the instruction decoder 5 is designated by the instruction. Address signal generation circuit 2
Is output to

When the instruction is an instruction to output the value stored in the internal memory 8, the instruction decoder 5 outputs the value stored in the internal memory 8 to the address signal generating circuit. Two
To output.

Further, the instruction decoder 5
Is to instruct the internal memory 8 to store the data input from the internal data bus 4 or to output the stored data to the internal data bus 4.

The external memory control signal generation circuit 6 outputs the read signal or the write signal input from the instruction decoder 5 to the peripheral switch 10 as an external memory control signal. The external input / output data control signal generation circuit 7 outputs a signal for driving an external device such as a transmission device or a disk device. Specifically, the read / write signal input from the instruction decoder 5 is output to the outside. It is output as an input / output data control signal.

The internal memory 8 stores data input from the internal data bus 4 according to an instruction from the instruction decoder 5 or outputs the stored data to the internal data bus 4.

Next, each part of the peripheral part shown in FIG. 3 will be described. Video memory control signal generation circuit 9
Outputs an external memory control signal input from the switch 10 to a video memory (not shown). still,
The video memory may be realized by using a part of an external memory as shown in FIG. FIG. 4 is an explanatory diagram showing an example of the usage pattern of the memory in the image data control system using the conventional microcontroller.

The switch 10 is connected so as to output the output of the external memory control signal generating circuit 6 to the video memory control signal generating circuit 9 when receiving the selection signal and determining that the microcontroller accesses the video memory. To do. Further, the switch 10 is connected so as to output the output of the external memory control signal generating circuit 6 to the external memory when receiving the selection signal and determining that the microcontroller does not access the video memory.

Next, the operation of the conventional microcontroller will be described by taking the case where the microcontroller performs image control as an example. First, the operation of obtaining an instruction from the peripheral ROM will be described. When the instruction decoder 5 outputs a selection signal to the peripheral ROM, the instruction decoder 5 resets the count value of the program counter 1 to a specific value accordingly. The program counter 1 causes the address signal generation circuit 2 to output the count value as an address.

Then, the ROM outputs the instruction stored at the address to the data input / output control circuit 3 via the external data bus. Then, the instruction is output to the internal data bus 4 by the data input / output control circuit 3 and output to the instruction decoder 5.

Next, a case where the instruction is for performing image control will be described. Since the conventional microcontroller does not have a dedicated instruction for performing image control, the contents of the instruction are as follows: the instruction decoder 5 outputs the selection signal for accessing the video memory as the first step, and the external step as the second step. The memory control signal generating circuit 6 is caused to output a read signal or a write signal, and the third step is to cause the address signal generating circuit 2 to output an address to be accessed, and
As the fourth step, data is exchanged with the internal data bus 4.

Therefore, the operation of each stage will be specifically described below. In order to facilitate the description, the case of writing to the video memory will be particularly described below. In the first stage, the instruction decoder 5 outputs a selection signal for accessing the video memory according to the instruction received via the data bus B (input data bus) of the internal data bus 4. Then, the switch 10 receiving the input connects the output of the external memory control signal generating circuit 6 to the video memory control signal generating circuit 9.

Then, in the second stage, the instruction decoder 5 outputs a write signal to the external memory control signal generating circuit 6. The write signal is output from the external memory control signal generation circuit 6 to the video memory control signal generation circuit 9 as an external memory control signal via the switch 10, and the video memory is put into a writable state.

Then, in the third stage, the instruction decoder 5 receives the instruction via the data bus B (input data bus) of the internal data bus 4 and specifies it on the screen by using an arithmetic unit (not shown). In order to draw at the coordinates of, the address at which the data of the coordinates is stored is calculated and obtained, and that address is stored in the internal memory 8.

This operation will be specifically described with reference to FIG. 4. The image on the screen is 1 for each pixel in the scanning direction.
One address is allocated and stored, so that the screen image is linearly expanded in the memory. Then, the instruction decoder 5 outputs the address stored in the internal memory 8 via the address signal generating circuit 2.

Further, in the fourth stage, the instruction decoder 5 transmits data to the data bus A (output data bus) of the internal data bus 4. Then, the data input / output control circuit 3 outputs this data to the video memory, and the data is stored in the address of the video memory.

[0024]

However, in the above-mentioned conventional microcontroller, the process of the operation in the third step, that is, the work of converting the linearly expanded data into the screen image, every time the video memory is accessed. Since it occurs, there is a problem that the efficiency is low and the processing speed is remarkably reduced when controlling the image control system which handles an image having a large capacity.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a microcontroller capable of efficiently controlling an image control system without reducing the processing speed.

[0026]

SUMMARY OF THE INVENTION The present invention for solving the above-mentioned problems of the prior art is to interpret an instruction for accessing a video memory having a two-dimensional array structure consisting of lines and columns in a microcontroller, An instruction decoder that outputs a selection signal to the video memory, a data input / output control circuit that inputs and outputs data to and from the video memory, and selects one of a line and a column of the video memory according to an instruction from the instruction decoder. A video memory control signal generating circuit for generating a strobe signal; and an address signal generating circuit for generating a line and column address in synchronization with the strobe signal in response to an instruction from the instruction decoder. Address and screen image Can be omitted computing of the conversion between, it is possible to speed up the image processing.

[0027]

Embodiments of the present invention will be described with reference to the drawings. The micro controller according to the present invention (the present micro controller) allows the instruction decoder to interpret a dedicated instruction for accessing the video memory so as to adopt different memory access methods between the external memory and the video memory. By utilizing this, the calculation of conversion between the address of the video memory and the screen image can be omitted to improve the processing speed.

The present microcontroller will be described with reference to FIG. FIG. 1 is a configuration block diagram of a microcontroller according to the present invention. As shown in FIG. 1, the present microcontroller includes a program counter 1, an address signal generation circuit 2, a data input / output control circuit 3, an internal data bus 4, an instruction decoder 5 ', and an external memory control signal generation circuit. 6, an external input / output data control signal generation circuit 7, an internal memory 8 and a video memory control signal generation circuit 9 '.

Although not shown, as a peripheral portion of the present microcontroller, at least an external memory, a ROM storing instructions, and a video memory are connected. Here, the video memory is a memory having a two-dimensional array structure, and specifically, two addresses of a first address (line address) and a second address (column address) are designated. In response to this, reading and writing are performed.

Each part will be specifically described below. A program counter 1, an address signal generating circuit 2, a data input / output control circuit 3, an internal data bus 4, an external memory control signal generating circuit 6 and an external circuit. Since the input / output data control signal generating circuit 7 and the internal memory 8 are the same as those of the conventional one, their explanations are omitted here.

The instruction decoder 5'is almost the same as the conventional one, but is different from the conventional one in that it can interpret an instruction dedicated to image control. Therefore, here, only the operation when receiving the instruction dedicated to the image control will be described. The instruction decoder 5'interprets the instruction dedicated to the image control, and if it judges that the video memory needs to be accessed, the instruction memory 5'will be stored in the video memory. A selection signal is output and a read signal or a write signal is output as a control signal to the video memory control signal generation circuit 9 '.

The instruction decoder 5 '
Is outputting an instruction decoder 5'to the address signal generating circuit 2 while the selection signal is being output to the video memory.
Alternatively, the data input from the internal memory 8 is output.

The video memory control signal generating circuit 9'is connected to an external video memory and outputs the input control signal to the video memory as a video memory control signal.

The video memory control signal generation circuit 9 '
Outputs the line address strobe signal and the column address strobe signal to the video memory in this order.

Here, a method in which the instruction decoder 5'outputs address data to the address signal generating circuit 2 to access the video memory will be specifically described below with reference to FIG. FIG. 2 is an explanatory diagram showing the contents of the video memory managed by the microcontroller of this embodiment.

The instruction decoder 5'outputs the line address in synchronization with the timing at which the video memory control signal generating circuit 9'outputs the line address strobe signal. Then, for example, if "0" is output as the line address, "0,0" to "1023,0" are selected on the video memory.

Then, the instruction decoder 5 '
Outputs the column address in synchronization with the timing at which the video memory control signal generation circuit 9'outputs the column address strobe signal. Then, for example,
When “1023” is output as the column address, “1023,0” is selected from the previously selected range of “0,0” to “1023,0” on the video memory.

The video memory is "1023,0".
The pixel information of is output (for reading) or changed (for writing).

Next, the operation of the present microcontroller, which is a characteristic part of the present microcontroller, will be described. Although the operation of reading the contents of the video memory is described below, the writing operation is essentially the same, and therefore the description thereof is omitted.

When the instruction decoder 5'receives, as an instruction, an instruction to read data from the video memory, it outputs a selection signal to the video memory, and the video memory control signal generation circuit 9'uses the read signal as a control signal. Output.

When the video memory control signal generation circuit 9'outputs the line address strobe signal,
At the same timing, the instruction decoder 5'outputs the address data of the line address to the address signal generating circuit 2.

Then, the video memory receives the address data of the line address from the address signal generating circuit 2 and selects the memory area corresponding to the line address. Then, the video memory control signal generation circuit 9 '
When the column address strobe signal is output, the instruction decoder 5 ′ outputs the address data of the column address to the address signal generating circuit 2 at the same timing.

Then, the video memory receives the address data of the column address from the address signal generating circuit 2 and selects the column address existing in the already selected line address. Then, the address corresponding to one pixel on the video memory is selected.

Then, the data input / output control circuit 3 comes to receive data from the video memory via the external data bus (not shown), and outputs it to the internal data bus 4. Then, the instruction decoder 5 ′ receives data from the internal data bus 4 according to the instruction.

According to the microcontroller of the present embodiment, the data storage state in the video memory and the state of the screen image are set in the same manner without performing the process of converting the coordinates on the screen to the address. Since the corresponding address can be accessed, the processing speed of image control can be improved.

[0046]

According to the present invention, an instruction decoder interprets an instruction for accessing a video memory, outputs a selection signal to the video memory, and a data input / output control circuit inputs / outputs data to / from the video memory. ,
The video memory control signal generation circuit generates a strobe signal for selecting either the line or the column of the video memory according to the instruction from the instruction decoder, and the address signal generation circuit generates the address of the line or column according to the instruction from the instruction decoder. Since it is a microcontroller that is generated in synchronism with the strobe signal, the data storage state in the video memory and the screen image state can be made the same, the calculation of conversion between the video memory address and the screen image can be omitted, and the image There is an effect that the processing speed can be improved.

[Brief description of the drawings]

FIG. 1 is a configuration block diagram of a microcontroller according to the present invention.

FIG. 2 is an explanatory diagram showing the contents of a video memory managed by the microcontroller of the present embodiment.

FIG. 3 is a configuration block diagram showing a conventional microcontroller and part of its peripheral portion.

FIG. 4 is an explanatory diagram showing an example of a usage form of a memory in an image data control system using the conventional microcontroller.

[Explanation of symbols]

1 ... Program counter, 2 ... Address signal generation circuit, 3 ... Data input / output circuit, 4 ... Internal data bus,
5, 5 '... Instruction decoder, 6 ... External memory control signal generating circuit, 7 ... External input / output data control signal generating circuit, 8 ... Internal memory, 9, 9' ... Video memory control signal generating circuit, 10 ... Switch

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Isao Teranishi 3-14-20 Higashi-Nakano, Nakano-ku, Tokyo Kokusai Electric Co., Ltd. (72) Inventor Yuichi Kubo 3-14-20 Higashi-Nakano, Nakano-ku, Tokyo Kokusai Electric Within the corporation

Claims (1)

[Claims] 1. An instruction decoder for interpreting an instruction for accessing a video memory having a two-dimensional array structure including lines and columns and outputting a selection signal to the video memory, and inputting / outputting data to / from the video memory. A data input / output control circuit, a video memory control signal generation circuit that generates a strobe signal that selects one of a line and a column of the video memory according to an instruction from the instruction decoder, and a line and a column according to an instruction from the instruction decoder. And an address signal generation circuit for generating the address of 1 in synchronization with the strobe signal.