JPH05197615A - Rom/ram switching circuit for starting cpu - Google Patents

Abstract

PURPOSE:To unnecessitate another RAM by connecting read signals to a ROM and a RAM by switching it at a switching circuit while connecting select signals to the ROM and the RAM. CONSTITUTION:A select signal 11 is operated so as to access a ROM 4 and a RAM 5 at the same time, and a read signal 13 is connected to either the ROM 4 or the RAM 5 by a switching circuit 3A. First, the switching circuit 3A is connected to the ROM 4 and the contents of ROM areas, namely, vector data and programs are written in the ROM 4. When starting a CPU 1, data to be read are data from the ROM 4, and the programs are started by the vector data in the ROM areas. In this case, when data are written in the address spaces of the ROM areas, data are written in the RAM 5. Afterwards, the read signal 13 is switched to the RAM 5 by the switching circuit 3A so that operations can be continued only by the RAM 5 afterwards.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION In a CPU circuit using an external memory, a program stored in a ROM operates at the time of starting the CPU, and after starting, the contents of the ROM area are rewritten to the RAM to operate by the RAM. Switch to RAM. The present invention is a CPU used in such a case.
The present invention relates to a boot ROM / RAM switching circuit.

[0002]

2. Description of the Related Art In a CPU such as 68000, a program start address, a stack pointer, vector table information (hereinafter abbreviated as vector data) of various interrupts, and an execution program are prepared in a unique address space at startup. Therefore, these contents are written in the ROM or the like and arranged at the unique address. However, in an application intended for real-time control or the like, the value of the interrupt vector is dynamically rewritten by a program and used. In this case, the address space of the ROM is changed to the RAM so that the vector table area can be rewritten.
Switch to.

Next, the structure of a ROM / RAM switching circuit according to the prior art will be described with reference to FIG. 1 in FIG. 2 is a CPU,
2 is an address decoding circuit, 3B is a switching circuit, 4 is RO
M, 5 and 6 are RAMs. From the address and control information from the CPU 1, the address decode circuit 2 selects the selection signal 11
And the selection signal 12 is created. The selection signal 11 is a decode signal indicating a unique address space required for the CPU 1 to refer to the vector data at the time of activation, and is sent to the ROM 4 or the RAM 5 by the switching circuit 3B. The selection signal 12 is RA
Sent to M6. Selection signals 11 and 12 are connected to RO
It works so that M4 and RAM5, 6 can be accessed.
In addition to this, the read signal 13 is sent from the CPU 1 to the ROM 4 and the RAMs 5 and 6.

Next, the switching map of FIG. 2 will be described with reference to FIG. The switching circuit 3B is initially connected to the ROM 4, and the contents of the ROM area 41 on the upper left side of FIG. 3, that is, the vector data 4A and the program 4B are written in the ROM 4.

When the CPU 1 is started up, the program 4B is started up by the vector data 4A. In order to move the vector data 4A and the program 4B to the RAM 5 of FIG. 2, they are first copied to the RAM 6 of FIG. Vector data 6A copied to the RAM area 61 on the lower left side of FIG.
Then, the program 6B is stored.

Next, the switching circuit 3B shown in FIG. 2 is switched to the RAM 5. As a result, the ROM area 41 on the upper left side in FIG. 3 disappears, and the RAM area 51 on the upper right side in FIG. 3 appears instead. Next, the vector table 6A and the program 6B copied to the lower left RAM area 61 of FIG. 3 are copied to the upper right RAM area 51 of FIG. ROM by the above operation
4 and RAM 5 can be switched.

[0007]

In FIG. 2, another memory area shown in the upper right of FIG. 3 is required to switch between the ROM 4 and the RAM 5, and since the program 4A is copied twice, the program control is complicated. become. According to the present invention, the ROM 4 and the RAM 5 are simultaneously accessed by the selection signal 11 and the read signal 13 is switched by the switching circuit 3A.
The output of the switching circuit 3A is stored in the ROM when the CPU 1 is started.
4, the output of the switching circuit 3A is connected to the RAM 5 after the CPU 1 is started, and the RAM 6 of FIG. 2 is unnecessary.
An object is to provide a boot ROM / RAM switching circuit.

[0009]

[Means for Solving the Problems] To achieve this object,
According to the present invention, the address decoding circuit 2 for creating the selection signal 11 indicating the unique address space required for the CPU 1 to refer to the vector data at the time of activation from the address and control information from the CPU 1, and the read signal 13 from the CPU 1.
Switching circuit 3A that receives the input, ROM 4 to which the switching output of switching circuit 3A and selection signal 11 are supplied, and switching circuit 3A
And the RAM 5 to which the selection signal 11 is supplied, the ROM 4 and the RAM 5 are simultaneously accessed by the selection signal 11, and when the CPU 1 is started, the output of the switching circuit 3A is connected to the ROM 4 and the data read by the CPU 1 is read. Is the data from the ROM 4, the program is started by the vector data in the area of the ROM 4, and when the program is written in the address space of the area of the ROM 4, the data is written in the RAM 5, and after the CPU 1 is started, the output of the switching circuit 3A is R
The read signal 13 is switched to the RAM 5 by connecting to the AM 5, and the RAM 5 alone continues the operation.

[0010]

Next, the structure of the ROM / RAM switching circuit according to the present invention will be described with reference to FIG. Reference numeral 3A in FIG. 1 is a switching circuit, and the others are the same as those in FIG. That is, FIG.
Then, select signals 11 and 12 are switched by the switching circuit 3B and R
In contrast to the connection to the OM4 and the RAM5, in FIG. 1, the selection signal 11 is left connected to the ROM4 and the RAM5, and the read signal 13 is switched by the switching circuit 3A so that the ROM4 and the RA5 are connected.
Connect to M5. The RAM 6 shown in FIG. 2 is not shown in FIG.

The selection signal 11 acts to simultaneously access the ROM 4 and the RAM 5, and the read signal 13 is connected to either the ROM 4 or the RAM 5 by the switching circuit 3A.

First, the switching circuit 3A is connected to the ROM 4. The contents of the ROM area 41 on the upper left side of FIG. 3, that is, the vector data 4A and the program 4B are written in the ROM 4. When the CPU 1 is activated, the data to be read becomes the data from the ROM 4, and the program 4B is activated by the vector data 4A in the ROM area 41. If data is written in the address space of the ROM area 41, the data is written in the RAM 5 at the upper right of FIG.

That is, the same address is read from the ROM 4 and written in the RAM 5. Therefore, FIG.
The program 4A in the upper left ROM area 41 reads the data in its own ROM area 41 and writes the data in the same address to copy the contents of the ROM area 41 to the RAM area 51 shown in the upper right of FIG. After that, by switching the read signal 13 to the RAM 5 by the switching circuit 3A, the operation can be continued only by the RAW 5 thereafter.

[0014]

According to the present invention, the ROM 4 and the RAM 5 are simultaneously accessed by the selection signal 11, and the read signal 1
2 is switched by the switching circuit 3A, the output of the switching circuit 3A is connected to the ROM 4 when the CPU 1 is started, and the output of the switching circuit 3A is connected to the RAM 5 after the CPU 1 is started, so that the RAM 6 of FIG. 2 is unnecessary. be able to. Also,
Since programs are not moved or transferred twice, simple and fast programs can be created.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a CPU boot ROM / RAM switching circuit according to the present invention.

FIG. 2 is a configuration diagram of a ROM / RAM switching circuit for starting a CPU according to a conventional technique.

FIG. 3 is an address map showing movement of the data area of FIG.

[Explanation of symbols]

 1 CPU 2 Address Decode Circuit 3A Switching Circuit 4 ROM 5 RAM 6 RAM 11 Selection Signal 12 Selection Signal 13 Read Signal

Claims (1)

[Claims] 1. An address decoding circuit (2) for generating a selection signal (11) indicating a unique address space required for the CPU (1) to refer to vector data at the time of activation from the address and control information from the CPU (1). ) And the read signal (13) from the CPU (1) are input
(3A), switching circuit (3A) switching output and selection signal (11) are supplied R
The OM (4), the switching output of the switching circuit (3A) and the selection signal (11) are supplied to the R
The AM (5) is provided, and the ROM (4) and RAM (5) are simultaneously accessed by the selection signal (11), and when the CPU (1) is started, the output of the switching circuit (3A) is changed to RO.
The data that connects to M (4) and reads CPU (1) is RO
The data is written from M (4), the program is started by the vector data in the area of ROM (4), and when the program is written in the address space of the area of ROM (4), the data is written in RAM (5) and the CPU (1 ) Is activated, the output of the switching circuit (3A) is transferred to the RAM (5)
Connect to and switch the read signal (13) to RAM (5).
A ROM / RAM switching circuit for starting a CPU, which continues to operate only by AM (5).