JPH09159734A - Ic testing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate the loss time of an IC testing device between tests and, at the same time, to reduce the labor required for generating a program. SOLUTION: The test signals of the A/D 19 and D/A 20 of an IC 18 to be tested are delivered and received by means of modules 14-17. The modules 14-17 output end signals a-d upon completing the delivery and reception of the signals. In order to select the module which outputs an end signal to be detected in each test, module selecting conditions are stored in advance in a memory 4. Whenever the end signals 1-d are outputted, the corresponding F/Fs 9-12 are set. The F/F corresponding to the module which does not output the end signal is preset under the selecting condition. When all F/Fs 9-12 are set, a gate 13 outputs a final end signal (z) indicating the completion of one test. When an SQPG (sequential pattern generator) 1 detects the signal (z), the SQPG 1 reads out the selecting condition of the next test from the memory 4 by outputting a next test address to a register 2 so that the next test can be executed without loss time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC test apparatus having an improved test time, and more particularly to an apparatus suitable for measuring an IC in which analog and digital circuits are mixed.

[0002]

2. Description of the Related Art In order to measure a mixed signal device (IC under test) provided with an A / D converter and a D / A converter, an A / D converter section and a D / A converter section must be measured, that is, a block unit. You need to test every time.

In the case of testing for each block, in order to continuously test all blocks without any loss time, it is necessary to start the next test immediately after the end of the previous test. To do this, you must accurately determine the end time of each block in the previous test. However, since the test end time differs among the blocks and the test end time differs depending on the test content even in the same block, it is difficult to accurately obtain the test end time for each block in advance. For this reason,
In general, to ensure that the test of the previous block has been completed, sufficient time is waited for between the next test. In addition, it takes extra time for the test time, and when various tests are accumulated, the waiting time cannot be ignored.

[0004] In order to test each block of the IC under test, the IC test apparatus is provided with a module directly connected to the IC under test.
It sends a test signal to C and receives a test signal from the IC under test. As shown in FIG.
The / D module 24 transmits an analog input signal to the A / D converter 27 in the IC 26 to be measured and receives a digital output signal thereof. The D / A module 25 transmits a digital input signal to the D / A converter 28 in the IC under measurement 26 and receives the analog output signal. When the test of the A / D converter 27 is completed, the A / D module 24 outputs a module end signal e.
The D / A module 25 outputs a module end signal f when the test of the D / A converter 28 is completed.

Therefore, instead of detecting the end time directly from the block, by utilizing the module end signals output from these modules 24 and 25,
Although it is indirect, it is possible to accurately know the test end time of the block, so that the module end signals e and f output from the modules 24 and 25 may be detected.

However, simply detecting the module end signal from the module has the following disadvantages.
That is, there are modules selected by the test and modules not selected, and a module end signal is output from the selected module, but an end signal is not output from the unselected module forever. Therefore, if the end of the test is detected after waiting for the end signal from the module, the end of the test may not be detected forever. For this reason,
In the test, it is necessary to set a module selection condition for clarifying which module is selected for each test. That is, by setting the module selection condition, only the module that has been selected waits for the module end signal, and the module that has not been selected does not wait for the end signal.

Therefore, a possible method is to rewrite the selection condition by the CPU every time the test is completed.
This method will be described with reference to FIG.

FIG. 5 is a conceptual diagram of a test circuit for testing the IC 26 to be measured for each block. The CPU 21
The selection conditions for all tests are written in the memory 34 in advance, and the selection conditions for the next test are stored in the register 23 at the end of each test. The register 23 holds the selection condition written by the CPU 21 until it is rewritten next, and outputs the previously written selection condition until the next test. Here, the selection condition is A / D of the IC 26 to be measured.
It is a condition for confirming whether the test of the converter 27 or the D / A converter 28 has been completed without fail, and specifies the modules 24 and 25 used in the test. In the illustrated example, two outputs are output corresponding to the selection condition of one test.

The two selection condition outputs are output to two 2-input OR circuits at the subsequent stage, that is, an OR circuit 29 corresponding to the A / D converter 27 and an O circuit corresponding to the D / A converter 28.
Each of the OR circuits 29 and 30 is input to one input of the R circuit 30, and is enabled or disabled according to the selection condition. For example, when the selection condition output from the register 23 is "0", it is enabled, and when it is "1", it is disabled. When the two OR circuits 29 and 30 are both enabled, the module end signals of the A / D module 24 and the D / A module 25 can be detected, and the A / D converter 27 and the All of the D / A converters 28 are to be tested.

On the other hand, when the OR circuit 29 corresponding to the A / D converter 27 is disabled, the A / D converter 27 is not tested.
When the OR circuit 30 corresponding to the D / A converter 28 is disabled, the D / A converter 28 is excluded from the test. Then, even if a module end signal is not output from the corresponding A / D module 24 and D / A module 25, it is set to have already been output. This is to avoid waiting for a module end signal that should not be output.

The A / D module 24 includes an IC 26 to be measured.
An analog input signal is transmitted to the A / D converter 27, and a digital output signal is received. When the test of the A / D converter 27 is completed, an end signal e is output.
The D / A module 25 transmits a digital input signal to the D / A converter 28 in the IC under test 26, receives the analog output signal, and outputs an end signal f when the test of the D / A converter 28 is completed. I do.

When a module end signal from the selected module 24 or 25 is output to the OR circuit 29 or 30 enabled by the selection condition of the register 23, the enabled OR circuit 2
9 or 30 connected to the flip-flop (F
/ F) Set 31 or 32. The disabled OR circuit 29 or 30 has the F / F 31 or 32 set from the beginning. Therefore, when both F / F31 and F / F32 are set, the test of the converter is completed.

The outputs of the two F / Fs 31 and 32 are input to a two-input AND circuit 33, and when one of the outputs of the two F / Fs 31 and 32 is "0", the output of the AND circuit 33 is " When both F / F outputs are "1", a final end signal g indicating that one test is completed is output from the AND circuit 33.

The output of the AND circuit 33 is input to a sequential pattern generator (SQPG) 22. Where S
The QPG 22 reads out data stored in advance in a local memory (not shown),
C26 is an address generator that generates a sequential test pattern (note that the
QPG). When the final end signal g is output from the AND circuit 33, it is detected by the SQPG 22 and an interrupt is issued from the SQPG 22 to the CPU 21.
The CPU 21 is notified that the test has been completed.

CPU 21 notified of the end of the test
Reads the module selection condition for the next test from the memory 34, stores it in the register 23, and performs the next test based on the stored selection condition. Hereinafter, similarly, each time the test is completed, the CPU 21 rewrites the selection condition of the register 23, and sequentially executes the next test based on the module selection condition stored in the register 23.

In the above-described configuration, when the test is performed for each block, when the test is performed serially,
There are two ways to test in parallel.

First, the case of serial test will be described. As shown in FIG. 6, the CPU 21
The module selection conditions of the first test read from the module No. 4 are written into the register 23 (a) and (b), and the A / D converter 27 is first tested according to the module selection conditions (c). The end of the test of the A / D converter 27 is notified by an end signal of the A / D module.
3. When detected by the SQPG 22 (f), the CPU 2
1 rewrites the module selection condition stored in the register 23 into the module selection condition for the next D / A converter test (a). Next, the D / A converter 28 is tested according to the rewritten module selection condition (c), and the end signal (e) of the D / A module is ANDed.
When detected by the circuit 33 and the SQPG 22 (d),
(F), the CPU 21 rewrites the contents of the register 23 with the next selection condition (a). Hereinafter, the test is performed in the same manner. In this case, the end signal will be equal to the final end signal.

Next, a case where the A / D converter 27 and the D / A converter 28 of the IC under test 26 are tested in parallel will be described. In the serial test of FIG. 6, the end signal is detected as the final end signal. In the case of the parallel test, as shown in FIG. 7, the end signal is the slowest of the two end signals (d) and (e). The other end signal is detected as the final end signal (f). Every time this final end signal is detected, the selection condition of the register 23 is rewritten by the CPU 21 and the next test is executed.

[0019]

However, in either of the serial and parallel test methods, the conventional circuit configuration described above causes the CPU 21 to intervene after the test is executed and before the next test is performed. Since it is necessary to rewrite the module selection condition by software, it is not necessary to have the above-mentioned waiting time, but there is a disadvantage that a loss time occurs between tests and the test time is long.

When the SQPG signal is detected, the module selection condition for the next test is read from the memory 34,
A program for taking this into the CPU 21 and writing it into the register 23 must be written each time the test content changes, so that the program creation is very troublesome.

An object of the present invention is to provide a software-based CP.
An object of the present invention is to provide an IC test apparatus which can solve the above-mentioned drawbacks of the prior art by eliminating the rewriting of the selection condition of U, thereby shortening the total test time and reducing the program creation labor. .

[0022]

SUMMARY OF THE INVENTION An IC test apparatus according to the present invention is an IC test apparatus for testing a plurality of blocks of an IC under test composed of a plurality of blocks which are individually required to be tested, serially or in parallel. Transmitting a test signal for individually testing them to the plurality of blocks, receiving an output signal output from each block based on the transmitted test signal, and transmitting a test signal to each block. A plurality of modules are provided, each of which outputs a module end signal indicating that the test of the block has been completed at the end of signal transmission or reception of an output signal output from each block.

Further, for each test, storage means for storing in advance a module selection condition for selecting a module for which a module end signal is to be detected from the plurality of modules, and a module end signal from the module selected by the selection condition Control means for detecting the output, and outputting an address for outputting the selection condition of the next test, and storing the address output from the control means for each test; A register for accessing the storage means, wherein the storage means is accessed by an address stored in the register, and a selection condition for selecting a next test module stored at the address is output. It is.

In the first invention, module selection conditions in each test for the IC to be measured are stored in the storage means in advance. Then, first, the selection condition of the first test is read from the storage means, and the module for which the end signal is to be detected is selected.

When a test is executed, a module end signal is output from a module selected in the test. This module end signal is detected by the control means. At this time, since only the module for which the end signal is to be detected is selected according to the selection condition, the detection is not completed when the control unit waits forever for a module end signal from an unselected module.

When the module end signal is detected by the control means, the control means outputs an address for outputting a selection condition for the next test, and the address is stored in a register. The selection condition for the next test stored in advance is promptly read from the storage means accessed to the address stored in the register, and the next test is executed according to the selection condition.

As described above, if the selection conditions for all the tests are stored in the storage means in advance, the selection conditions for the next test are read without intervening the CPU every time the module end signal is detected. Therefore, the next test can be executed quickly, and the interval time between tests becomes shorter than when the CPU is interposed.

According to a second aspect of the present invention, in the first aspect of the present invention, the control means selects the first test of a module which is not selected in the test by the selection condition read out from the storage means and which does not output a module end signal. A set signal is output from a plurality of set gate circuits that output a set signal when a module end signal is output from the module, and a set signal output from each set gate circuit is output for each selected module. When the last module end signal among the plurality of flip-flops to be set and the module end signals output from the plurality of modules selected in the test is output and the last flip-flop is set, the final A detection gate circuit that outputs an end signal; By detecting the final end signal from the circuit, those which are constituted by a control circuit for outputting an address for outputting a selection condition of the next test.

In the second invention, when a module end signal is output from a selected module according to a selection condition read from the storage means, a set signal is output from a corresponding set gate circuit. According to the selection condition read from the storage means, a set signal is output in advance from a set gate circuit corresponding to a module not selected so as not to wait for an end signal from the module.

The flip-flops are sequentially set by the set signal from the set gate circuit, except for the flip-flops already set. Then, when the last module end signal of the test is output and the last flip-flop is set, a final end signal is output from the detection gate circuit. The final end signal is detected by the control circuit, and the control circuit that has detected the final end signal outputs an address for outputting the selection condition of the next test to a register, and from the storage means, outputs the address for the next test. Read the selection condition. The next test is executed according to the read selection condition.

As described above, in the test, when the latest end signal among a plurality of module end signals output from the selected module is detected, the selection condition of the next test is read from the storage means. Even if the timings of the module end signals output from a plurality of modules are different, the next test can be performed after the previous test is completed without being switched to the next test during the test.

Further, a third invention is an analog / digital mixed circuit in which the plurality of blocks include an analog section and a digital section. According to this, it is possible to test a mixed analog / digital circuit, which is particularly problematic, without any loss time.

[0033]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a tester circuit for describing an IC test apparatus according to the present invention will be described below. FIG.
FIG. 2 is a diagram showing a circuit around an IC to be measured and a main part of a test circuit.

As described above, in order to measure the IC under test 18 having the A / D converter 19 and the D / A converter 20, it is necessary to perform a test for each block unit.

In order to test for each block unit, for example, an arbitrary waveform generator (AWG) 14 and a receive memory (R)
Each module including a CVM 15, a send memory (SNDM) 16, and a digitizer (DGT) 17 is required.

The AWG 14 receives an A / D signal in response to a start signal.
An arbitrary waveform as an input signal source to the converter 19 is generated. This is usually a sin waveform. The RCVM 15 takes in a digital output signal having analog information from the A / D converter 19. The SNDM 16 generates a digital signal having analog information as an input signal source to the D / A converter 20 according to the start signal. And DGT
Reference numeral 17 fetches the analog output signal of the D / A converter 20, converts it into digital data, and writes it to the memory. These modules output module end signals a, b, c, and d when the module operation ends.

These module end signals a to d are sent to a tester circuit to be described next, and a desired test is repeated.

The SQPG 1 is connected to the register 2, and upon detecting the final end signal output from the AND circuit 13, writes an address for reading the next module selection condition into the register 2 by a macro instruction. I have. In the register 2, an address for reading the module selection condition from the memory 4 for each test is written by the SQPG1, and is held during the test period. The module selection condition is composed of four outputs in accordance with the number of modules 14 to 17, and when "0", OR circuits 5 to 8 at the subsequent stage corresponding to the module contributing to the test.
Is enabled, and when "1", the OR circuits 5 to 8 corresponding to the modules that do not contribute to the test are disabled.

The four selection conditions of the memory 4 are applied to one input of each of the four OR circuits 5 to 8, and the end signals a to d of the modules 14 to 17 are applied to the other input. End signals a to corresponding to the selected module
When d is output, a set signal is output. Specifically, when an end signal is input to the OR circuits 5 to 8 in the enabled state by the output of the memory 4,
A set signal is output from the OR circuits 5 to 8. Conversely, a set signal is output from the OR circuit in the disabled state from the beginning.

Each of the OR circuits 5 to 8 has a flip-flop F
/ F9 to / F12 are connected to enable the OR circuit 5
When the end signal is input to the output circuits 8 to 8, the F / Fs 9 to 12 connected to the outputs of the OR circuits 5 to 8 are set. Note that the OR circuits 5 to 5 in the disabled state are
8 is always "1", so that the F / Fs 9 to 12 are set from the beginning.

The four F / Fs 9-12 are connected to the inputs of the 4-input AND circuit 13, and when all the F / Fs 9-12 are set, the final end signal z = “1” is output. Has become. The output of the AND circuit 13 is input to the SQPG1, and the SQPG1 detects the final end signal z.

The above-mentioned SQPG1 constitutes a control circuit, the memory 4 constitutes storage means, the OR circuits 5 to 8 constitute a set gate circuit, the AND circuit 13 constitutes a detection gate circuit, and the SQPG1 and the OR gates 5 to 8; F / F9 ~
The control circuit 12 and the AND circuit 13 constitute the control means 35 of the present invention.

Now, the operation of the circuit having the above configuration will be described with reference to the timing chart shown in FIG. In the first half of this timing chart, the test of the A / D converter alone is performed, and in the second half, the A / D and D / A parallel tests are performed.

The CPU 3 previously writes in the memory 4 a combination of start of each module, a stop of the AWG 14, and a combination of selection conditions of a module selected in all tests (a).

An address for reading the first module selection condition is specified by the SQPG1 (b), and the address is written to the register 2 (c).

The memory 4 is accessed by the address written in the register 2, the module selection condition stored at the address is read from the memory 4, and the selection condition selects the AWG 14 and the RCVM 15.
It is maintained until the next address is accessed (d).

The AWG 14 and the RCVM 15 start (e) and (g) according to the designation of the start combination of the module written in the memory 4. RCVM15 is AWG
When the reception of the output signal output from the A / D converter 19 in response to the input signal from the
An end signal b is output (h).

After a short delay, the AWG end signal a
Output from the WG 14 (f).

When these end signals a and b are output,
F / F9 and 10 corresponding to the end signal are sequentially set,
When the latest AWG end signal a is output, the final end signal z is output from the AND circuit 13 (m).

When the final end signal z is output from the AND circuit 13, this signal is immediately detected by the SQPG1, and
An address for reading out the selection condition of the next test is output from QPG1 (b).

The address output from the SQPG 1 is written to the register 2 (c), the memory 4 is accessed by the address written to the register 2, and the module stored at the address for the next test is selected. The condition is read from the memory 4 (d). This selection condition is to select all modules 14 to 17 because the next test is to test using all modules 14 to 17. For this test, AWG, RCVM, SN
The DM and DGT end signals are shown in FIGS. 2 (f), (h) and (j).
, (L), the module that issues the last end signal is the SNDM16. This SND
When the module end signal c is output from M16, the gate 13 outputs the final end signal "1". This signal is S
An address which is detected by QPG1 and from which the selection condition of the next test is read out from SQPG1 is output (b). Hereinafter, the test is repeated in the same manner.

The F / Fs 9 to 12 are reset at the timing when an address is written into the register 2 as shown in FIG.

As described above, after the final end signal z is output, until the next selection condition is output, only the SQPG1 is interposed and the CPU 3 is not interposed. It is performed. Therefore, the traverse time from the previous test to the next test, which is performed after the selection condition is switched, can be greatly reduced.

Next, a program for executing the above test will be described. As shown in FIG. 3, the program creates a main program and an A / D pattern (meaning a pattern for testing the A / D converter).
In the A / D pattern, LABEL4 RCVM LABEL5 AWG LABEL6 SNDM LABEL7 DGT The selection conditions are written in the memory in advance.

By coding LABEL4 and LABEL5 in the middle of the pattern 1 in the A / D pattern, the wait designation of the end signal of RCVM and AWG is performed, and the pattern 1 is completed. Will be done.

On the other hand, as shown in FIG.
In the case where a PU is interposed, since the selection condition is not set in advance, the pattern 1 is the pattern 1-1 and the pattern 1
-2. And before the start of the pattern,
The instruction SET REG RCVM SET REG AWG to write the selection condition from U to the register must be added each time.

As can be easily understood by comparing the two, the program of the present embodiment is not divided in pattern compared to the conventional example, and the main program has
Since it is not necessary to write a set instruction to the register before the pattern starts, the program work becomes easier.

The IC under test to which the present invention is applied is mainly an ISD in which analog / digital circuits are mixed.
There are an N interface, an audio signal processing IC such as a VTR / CD, a CODEC, and a microprocessor with a built-in A / D and D / A. However, even if it is composed of only an analog circuit or a digital circuit, it is also included when it is composed of a plurality of blocks that are individually required to be tested.

Further, in the above-described embodiment, the case where the end signal output from the module is four has been described. Therefore, the control means 35 also has a four-circuit configuration. However, neither the end signal nor the control means 35 is limited to four circuits. .

Further, the SQPG1 used in the IC test apparatus is used as the control circuit, but the present invention is not limited to this, and the gate circuit 13 detects the final end signal z and outputs the selection condition for the next test. Any one may be used as long as it outputs an address.

[0061]

According to the present invention, the module selection condition is stored in the storage means in advance, and when the module end signal is output, the selection condition for the next test is read out. CPU after being executed
It is possible to continue the test in real time without rewriting the selection conditions by the. Therefore, the interval time between tests can be shortened, and the total test time can be shortened. Also, for each test, CP
Since it is not necessary to write a program for rewriting the selection condition in U, it is possible to significantly reduce the program creation.

[Brief description of the drawings]

FIG. 1 is a tester circuit configuration diagram for explaining an embodiment of an IC test apparatus of the present invention.

FIG. 2 is a timing chart of each part of the tester circuit of FIG. 1;

FIG. 3 is an explanatory diagram showing a program description format of the present embodiment.

FIG. 4 is an explanatory diagram showing a program description format of a conventional example.

FIG. 5 is a schematic configuration diagram of a tester circuit for explaining a conventional IC test apparatus.

6 is a timing chart of each part of the tester circuit of FIG. 5 under a sequential test.

7 is a timing chart of each part of the tester circuit of FIG. 5 under a parallel test.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 SQPG (control circuit) 2 register 3 CPU 4 memory (storage means) 5 to 8 OR gate (set gate circuit) 9 to 12 F / F 13 AND circuit (detection gate circuit) 14 AWG (module) 15 RCVM (module) Reference Signs List 16 SNDM (module) 17 DGT (module) 18 IC under test 19 A / D converter 20 D / A converter 35 Control means a to d End signal z Final end signal

Claims (3)

[Claims] 1. An IC test apparatus for testing a plurality of blocks of an IC to be measured, each block of which is individually required to be tested, serially or in parallel a plurality of times. The test signal for transmitting, and receiving the output signal output from each block based on the transmitted test signal, and at the end of transmission of the test signal transmitted to each block or output from each block A module for outputting a module end signal indicating that the block test is completed at the end of reception of the output signal, and a module for selecting a module end signal from the plurality of modules for each test. A storage means for storing the module selection conditions in advance and a module selected according to the selection conditions. Control means for detecting when a module end signal is output from the module and outputting an address for outputting a selection condition for the next test; storing the address output from the control means for each test; A register for accessing the storage means with the stored address; and a selection condition for accessing the storage means with the address stored in the register and selecting a next test module stored at the address. An IC tester designed to output. 2. The control means outputs a set signal from the beginning of a test for a module which is not selected in the test and which does not output a module end signal, according to a selection condition read out from the storage means. A plurality of set gate circuits outputting a set signal when a module end signal is output from the module, a plurality of flip-flops each set by the set signal output from each set gate circuit, A detection gate circuit for outputting a final end signal when the last module end signal is output from the plurality of selected modules and the last flip-flop is set; Detects the final end signal from the circuit and 2. The IC test apparatus according to claim 1, further comprising: a control circuit that outputs an address for outputting a test selection condition. 3. The IC test apparatus according to claim 1, wherein the plurality of blocks are an analog / digital mixed circuit including an analog section and a digital section.